m68knommu: merge bit definitions for version 3 ColdFire cache controller

All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 52 insertions, 0 deletions

diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
new file mode 100644
index 000000000000..532fbb91185f
--- /dev/null
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -0,0 +1,52 @@
+/****************************************************************************/
+
+/*
+ * m53xxacr.h -- ColdFire version 3 core cache support
+ *
+ * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
+ */
+
+/****************************************************************************/
+#ifndef m53xxacr_h
+#define m53xxacr_h
+/****************************************************************************/
+
+/*
+ * All varients of the ColdFire using version 3 cores have a similar
+ * cache setup. They have a unified instruction and data cache, with
+ * configurable write-through or copy-back operation.
+ */
+
+/*
+ * Define the Cache Control register flags.
+ */
+#define CACR_EC         0x80000000      /* Enable cache */
+#define CACR_ESB        0x20000000      /* Enable store buffer */
+#define CACR_DPI        0x10000000      /* Disable invalidation by CPUSHL */
+#define CACR_HLCK       0x08000000      /* Half cache lock mode */
+#define CACR_CINVA      0x01000000      /* Invalidate cache */
+#define CACR_DNFB       0x00000400      /* Inhibited fill buffer */
+#define CACR_DCM_WT     0x00000000      /* Cacheable write-through */
+#define CACR_DCM_CB     0x00000100      /* Cacheable copy-back */
+#define CACR_DCM_PRE    0x00000200      /* Cache inhibited, precise */
+#define CACR_DCM_IMPRE  0x00000300      /* Cache inhibited, imprecise */
+#define CACR_WPROTECT   0x00000020      /* Write protect*/
+#define CACR_EUSP       0x00000010      /* Eanble separate user a7 */
+
+/*
+ * Define the Access Control register flags.
+ */
+#define ACR_BASE_POS    24              /* Address Base (upper 8 bits) */
+#define ACR_MASK_POS    16              /* Address Mask (next 8 bits) */
+#define ACR_ENABLE      0x00008000      /* Enable this ACR */
+#define ACR_USER        0x00000000      /* Allow only user accesses */
+#define ACR_SUPER       0x00002000      /* Allow supervisor access only */
+#define ACR_ANY         0x00004000      /* Allow any access type */
+#define ACR_CM_WT       0x00000000      /* Cacheable, write-through */
+#define ACR_CM_CB       0x00000020      /* Cacheable, copy-back */
+#define ACR_CM_PRE      0x00000040      /* Cache inhibited, precise */
+#define ACR_CM_IMPRE    0x00000060      /* Cache inhibited, imprecise */
+#define ACR_WPROTECT    0x00000004      /* Write protect region */
+
+/****************************************************************************/
+#endif  /* m53xxsim_h */