m68knommu: merge bit definitions for version 3 ColdFire cache controller

All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 2 insertions, 27 deletions

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 45c119c072db..e6470f8ca324 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -12,6 +12,8 @@
 #define CPU_NAME                "COLDFIRE(m532x)"
 #define CPU_INSTR_PER_JIFFY     3
 
+#include <asm/m53xxacr.h>
+
 #define MCF_REG32(x) (*(volatile unsigned long  *)(x))
 #define MCF_REG16(x) (*(volatile unsigned short *)(x))
 #define MCF_REG08(x) (*(volatile unsigned char  *)(x))
@@ -77,33 +79,6 @@
 #define MCF_IRQ_PROFILER        (64 + 33)       /* Timer1 */
 
 /*
- *      Define the Cache register flags.
- */
-#define CACR_EC                 (1<<31)
-#define CACR_ESB                (1<<29)
-#define CACR_DPI                (1<<28)
-#define CACR_HLCK               (1<<27)
-#define CACR_CINVA              (1<<24)
-#define CACR_DNFB               (1<<10)
-#define CACR_DCM_WTHRU          (0<<8)
-#define CACR_DCM_WBACK          (1<<8)
-#define CACR_DCM_OFF_PRE        (2<<8)
-#define CACR_DCM_OFF_IMP        (3<<8)
-#define CACR_DW                 (1<<5)
-
-#define ACR_BASE_POS            24
-#define ACR_MASK_POS            16
-#define ACR_ENABLE              (1<<15)
-#define ACR_USER                (0<<13)
-#define ACR_SUPER               (1<<13)
-#define ACR_ANY                 (2<<13)
-#define ACR_CM_WTHRU            (0<<5)
-#define ACR_CM_WBACK            (1<<5)
-#define ACR_CM_OFF_PRE          (2<<5)
-#define ACR_CM_OFF_IMP          (3<<5)
-#define ACR_WPROTECT            (1<<2)
-
-/*
  *  UART module.
  */
 #define MCFUART_BASE1           0xFC060000      /* Base address of UART1 */