m68knommu: make ColdFire watchdog register definitions absolute addresses

Make all definitions of the ColdFire Software watchdog registers absolute
addresses. Currently some are relative to the MBAR peripheral region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 5709de5b8289..a328e1806feb 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -25,8 +25,8 @@
  */
 #define MCFSIM_RSR              (MCF_MBAR + 0x00)       /* Reset Status reg */
 #define MCFSIM_SYPCR            (MCF_MBAR + 0x01)       /* System Protection */
-#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x02)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x03)       /* SW Watchdog service*/
 #define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
 #define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
 #define MCFSIM_PLLCR            0x08            /* PLL Control Reg*/