m68k,m68knommu: merge header files

Merge header files for m68k and m68knommu to the single location:

    arch/m68k/include/asm

The majority of this patch was the result of the
script that is included in the changelog below.

The script was originally written by Arnd Bergman and
exten by me to cover a few more files.

When the header files differed the script uses the following:

The original m68k file is named <file>_mm.h  [mm for memory manager]
The m68knommu file is named <file>_no.h [no for no memory manager]

The files uses the following include guard:

This include gaurd works as the m68knommu toolchain set
the __uClinux__ symbol - so this should work in userspace too.

Merging the header files for m68k and m68knommu exposes the
(unexpected?) ABI differences thus it is easier to actually
identify these and thus to fix them.

The commit has been build tested with both a m68k and
a m68knommu toolchain - with success.

The commit has also been tested with "make headers_check"
and this patch fixes make headers_check for m68knommu.

The script used:
TARGET=arch/m68k/include/asm
SOURCE=arch/m68knommu/include/asm

INCLUDE="cachectl.h errno.h fcntl.h hwtest.h ioctls.h ipcbuf.h \
linkage.h math-emu.h md.h mman.h movs.h msgbuf.h openprom.h \
oplib.h poll.h posix_types.h resource.h rtc.h sembuf.h shmbuf.h \
shm.h shmparam.h socket.h sockios.h spinlock.h statfs.h stat.h \
termbits.h termios.h tlb.h types.h user.h"

EQUAL="auxvec.h cputime.h device.h emergency-restart.h futex.h \
ioctl.h irq_regs.h kdebug.h local.h mutex.h percpu.h \
sections.h topology.h"

NOMUUFILES="anchor.h bootstd.h coldfire.h commproc.h dbg.h \
elia.h flat.h m5206sim.h m520xsim.h m523xsim.h m5249sim.h \
m5272sim.h m527xsim.h m528xsim.h m5307sim.h m532xsim.h \
m5407sim.h m68360_enet.h m68360.h m68360_pram.h m68360_quicc.h \
m68360_regs.h MC68328.h MC68332.h MC68EZ328.h MC68VZ328.h \
mcfcache.h mcfdma.h mcfmbus.h mcfne.h mcfpci.h mcfpit.h \
mcfsim.h mcfsmc.h mcftimer.h mcfuart.h mcfwdebug.h \
nettel.h quicc_simple.h smp.h"

FILES="atomic.h bitops.h bootinfo.h bug.h bugs.h byteorder.h cache.h \
cacheflush.h checksum.h current.h delay.h div64.h \
dma-mapping.h dma.h elf.h entry.h fb.h fpu.h hardirq.h hw_irq.h io.h \
irq.h kmap_types.h machdep.h mc146818rtc.h mmu.h mmu_context.h \
module.h page.h page_offset.h param.h pci.h pgalloc.h \
pgtable.h processor.h ptrace.h scatterlist.h segment.h \
setup.h sigcontext.h siginfo.h signal.h string.h system.h swab.h \
thread_info.h timex.h tlbflush.h traps.h uaccess.h ucontext.h \
unaligned.h unistd.h"

mergefile() {
	BASE=${1%.h}
	git mv ${SOURCE}/$1 ${TARGET}/${BASE}_no.h
	git mv ${TARGET}/$1 ${TARGET}/${BASE}_mm.h

cat << EOF > ${TARGET}/$1
EOF

	git add ${TARGET}/$1
}

set -e

mkdir -p ${TARGET}

git mv include/asm-m68k/* ${TARGET}
rmdir include/asm-m68k

git rm ${SOURCE}/Kbuild
for F in $INCLUDE $EQUAL; do
	git rm ${SOURCE}/$F
done

for F in $NOMUUFILES; do
	git mv ${SOURCE}/$F ${TARGET}/$F
done

for F in $FILES ; do
	mergefile $F
done

rmdir arch/m68knommu/include/asm
rmdir arch/m68knommu/include

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

1 files changed, 181 insertions, 0 deletions

diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
new file mode 100644
index 000000000000..5886728409c0
--- /dev/null
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -0,0 +1,181 @@
+/****************************************************************************/
+
+/*
+ *      m5307sim.h -- ColdFire 5307 System Integration Module support.
+ *
+ *      (C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
+ *      (C) Copyright 1999,  Lineo (www.lineo.com)
+ *
+ *      Modified by David W. Miller for the MCF5307 Eval Board.
+ */
+
+/****************************************************************************/
+#ifndef m5307sim_h
+#define m5307sim_h
+/****************************************************************************/
+
+/*
+ *      Define the 5307 SIM register set addresses.
+ */
+#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
+#define MCFSIM_PAR              0x04            /* Pin Assignment reg (r/w) */
+#define MCFSIM_IRQPAR           0x06            /* Interrupt Assignment reg (r/w) */
+#define MCFSIM_PLLCR            0x08            /* PLL Controll Reg*/
+#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
+#define MCFSIM_AVR              0x4b            /* Autovector Ctrl reg (r/w) */
+#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+
+#ifdef CONFIG_OLDMASK
+#define MCFSIM_CSBAR            0x98            /* CS Base Address reg (r/w) */
+#define MCFSIM_CSBAMR           0x9c            /* CS Base Mask reg (r/w) */
+#define MCFSIM_CSMR2            0x9e            /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSMR3            0xaa            /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSMR4            0xb6            /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+#define MCFSIM_CSMR5            0xc2            /* CS 5 Mask reg (r/w) */
+#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
+#define MCFSIM_CSMR6            0xce            /* CS 6 Mask reg (r/w) */
+#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
+#define MCFSIM_CSMR7            0xda            /* CS 7 Mask reg (r/w) */
+#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#else
+#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
+#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+#define MCFSIM_CSAR5            0xbc            /* CS 5 Address reg (r/w) */
+#define MCFSIM_CSMR5            0xc0            /* CS 5 Mask reg (r/w) */
+#define MCFSIM_CSCR5            0xc6            /* CS 5 Control reg (r/w) */
+#define MCFSIM_CSAR6            0xc8            /* CS 6 Address reg (r/w) */
+#define MCFSIM_CSMR6            0xcc            /* CS 6 Mask reg (r/w) */
+#define MCFSIM_CSCR6            0xd2            /* CS 6 Control reg (r/w) */
+#define MCFSIM_CSAR7            0xd4            /* CS 7 Address reg (r/w) */
+#define MCFSIM_CSMR7            0xd8            /* CS 7 Mask reg (r/w) */
+#define MCFSIM_CSCR7            0xde            /* CS 7 Control reg (r/w) */
+#endif /* CONFIG_OLDMASK */
+
+#define MCFSIM_DCR              0x100           /* DRAM Control reg (r/w) */
+#define MCFSIM_DACR0            0x108           /* DRAM 0 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR0             0x10c           /* DRAM 0 Mask reg (r/w) */
+#define MCFSIM_DACR1            0x110           /* DRAM 1 Addr and Ctrl (r/w) */
+#define MCFSIM_DMR1             0x114           /* DRAM 1 Mask reg (r/w) */
+
+#define MCFSIM_PADDR            0x244           /* Parallel Direction (r/w) */
+#define MCFSIM_PADAT            0x248           /* Parallel Data (r/w) */
+
+
+/* Definition offset address for CS2-7  -- old mask 5307 */
+
+#define MCF5307_CS2             (0x400000)
+#define MCF5307_CS3             (0x600000)
+#define MCF5307_CS4             (0x800000)
+#define MCF5307_CS5             (0xA00000)
+#define MCF5307_CS6             (0xC00000)
+#define MCF5307_CS7             (0xE00000)
+
+
+/*
+ *      Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
+#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
+#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
+#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
+
+#if defined(CONFIG_M5307)
+#define MCFSIM_IMR_MASKALL      0x3fffe         /* All SIM intr sources */
+#endif
+
+/*
+ *      Macro to set IMR register. It is 32 bits on the 5307.
+ */
+#define mcf_getimr()            \
+        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
+
+#define mcf_setimr(imr)         \
+        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
+
+#define mcf_getipr()            \
+        *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
+
+
+/*
+ *      Some symbol defines for the Parallel Port Pin Assignment Register
+ */
+#define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
+                                                /* Clear to select par I/O */
+#define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
+                                                /* Clear to select par I/O */
+
+/*
+ *       Defines for the IRQPAR Register
+ */
+#define IRQ5_LEVEL4     0x80
+#define IRQ3_LEVEL6     0x40
+#define IRQ1_LEVEL2     0x20
+
+
+/*
+ *      Define the Cache register flags.
+ */
+#define CACR_EC                 (1<<31)
+#define CACR_ESB                (1<<29)
+#define CACR_DPI                (1<<28)
+#define CACR_HLCK               (1<<27)
+#define CACR_CINVA              (1<<24)
+#define CACR_DNFB               (1<<10)
+#define CACR_DCM_WTHRU          (0<<8)
+#define CACR_DCM_WBACK          (1<<8)
+#define CACR_DCM_OFF_PRE        (2<<8)
+#define CACR_DCM_OFF_IMP        (3<<8)
+#define CACR_DW                 (1<<5)
+
+#define ACR_BASE_POS            24
+#define ACR_MASK_POS            16
+#define ACR_ENABLE              (1<<15)
+#define ACR_USER                (0<<13)
+#define ACR_SUPER               (1<<13)
+#define ACR_ANY                 (2<<13)
+#define ACR_CM_WTHRU            (0<<5)
+#define ACR_CM_WBACK            (1<<5)
+#define ACR_CM_OFF_PRE          (2<<5)
+#define ACR_CM_OFF_IMP          (3<<5)
+#define ACR_WPROTECT            (1<<2)
+
+/****************************************************************************/
+#endif  /* m5307sim_h */