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author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-05 10:22:45 -0400 |
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committer | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2012-09-05 10:22:45 -0400 |
commit | 593d0a3e9f813db910dc50574532914db21d09ff (patch) | |
tree | 12d8413ee57b4383ca8c906996ffe02be6d377a5 /arch/m68k/include/asm/m528xsim.h | |
parent | 50e900417b8096939d12a46848f965e27a905e36 (diff) | |
parent | 4cb38750d49010ae72e718d46605ac9ba5a851b4 (diff) |
Merge commit '4cb38750d49010ae72e718d46605ac9ba5a851b4' into stable/for-linus-3.6
* commit '4cb38750d49010ae72e718d46605ac9ba5a851b4': (6849 commits)
bcma: fix invalid PMU chip control masks
[libata] pata_cmd64x: whitespace cleanup
libata-acpi: fix up for acpi_pm_device_sleep_state API
sata_dwc_460ex: device tree may specify dma_channel
ahci, trivial: fixed coding style issues related to braces
ahci_platform: add hibernation callbacks
libata-eh.c: local functions should not be exposed globally
libata-transport.c: local functions should not be exposed globally
sata_dwc_460ex: support hardreset
ata: use module_pci_driver
drivers/ata/pata_pcmcia.c: adjust suspicious bit operation
pata_imx: Convert to clk_prepare_enable/clk_disable_unprepare
ahci: Enable SB600 64bit DMA on MSI K9AGM2 (MS-7327) v2
[libata] Prevent interface errors with Seagate FreeAgent GoFlex
drivers/acpi/glue: revert accidental license-related 6b66d95895c bits
libata-acpi: add missing inlines in libata.h
i2c-omap: Add support for I2C_M_STOP message flag
i2c: Fall back to emulated SMBus if the operation isn't supported natively
i2c: Add SCCB support
i2c-tiny-usb: Add support for the Robofuzz OSIF USB/I2C converter
...
Diffstat (limited to 'arch/m68k/include/asm/m528xsim.h')
-rw-r--r-- | arch/m68k/include/asm/m528xsim.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h index 497c31c803ff..4acb3c0a642e 100644 --- a/arch/m68k/include/asm/m528xsim.h +++ b/arch/m68k/include/asm/m528xsim.h | |||
@@ -52,7 +52,7 @@ | |||
52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) | 52 | #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) |
53 | 53 | ||
54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) | 54 | #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) |
55 | 55 | #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) | |
56 | /* | 56 | /* |
57 | * SDRAM configuration registers. | 57 | * SDRAM configuration registers. |
58 | */ | 58 | */ |