diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-08 19:12:29 -0500 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 00:19:18 -0500 |
| commit | a12cf0a8c6e2763ac865aa31f296557e07432b8a (patch) | |
| tree | 5b44bfe7aca132e1a3f0cd2bd7bbe2291b56a663 /arch/m68k/include/asm/m5249sim.h | |
| parent | 63e83c8a52031555b1e724f98a33f1838dee6345 (diff) | |
m68knommu: create bit definitions for the version 2 ColdFire cache controller
The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m5249sim.h')
| -rw-r--r-- | arch/m68k/include/asm/m5249sim.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h index 21d0bbfbc0c9..4908b118f2fd 100644 --- a/arch/m68k/include/asm/m5249sim.h +++ b/arch/m68k/include/asm/m5249sim.h | |||
| @@ -14,6 +14,8 @@ | |||
| 14 | #define CPU_NAME "COLDFIRE(m5249)" | 14 | #define CPU_NAME "COLDFIRE(m5249)" |
| 15 | #define CPU_INSTR_PER_JIFFY 3 | 15 | #define CPU_INSTR_PER_JIFFY 3 |
| 16 | 16 | ||
| 17 | #include <asm/m52xxacr.h> | ||
| 18 | |||
| 17 | /* | 19 | /* |
| 18 | * Define the 5249 SIM register set addresses. | 20 | * Define the 5249 SIM register set addresses. |
| 19 | */ | 21 | */ |