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authorTrond Myklebust <Trond.Myklebust@netapp.com>2006-07-03 13:49:45 -0400
committerTrond Myklebust <Trond.Myklebust@netapp.com>2006-07-03 13:49:45 -0400
commit026477c1141b67e98e3bd8bdedb7d4b88a3ecd09 (patch)
tree2624a44924c625c367f3cebf937853b9da2de282 /arch/m32r
parent9f2fa466383ce100b90fe52cb4489d7a26bf72a9 (diff)
parent29454dde27d8e340bb1987bad9aa504af7081eba (diff)
Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
Diffstat (limited to 'arch/m32r')
-rw-r--r--arch/m32r/boot/compressed/head.S1
-rw-r--r--arch/m32r/boot/compressed/m32r_sio.c1
-rw-r--r--arch/m32r/boot/compressed/misc.c1
-rw-r--r--arch/m32r/boot/compressed/vmlinux.lds.S1
-rw-r--r--arch/m32r/boot/setup.S1
-rw-r--r--arch/m32r/kernel/align.c1
-rw-r--r--arch/m32r/kernel/entry.S1
-rw-r--r--arch/m32r/kernel/head.S1
-rw-r--r--arch/m32r/kernel/io_m32104ut.c1
-rw-r--r--arch/m32r/kernel/io_m32700ut.c1
-rw-r--r--arch/m32r/kernel/io_mappi.c1
-rw-r--r--arch/m32r/kernel/io_mappi2.c1
-rw-r--r--arch/m32r/kernel/io_mappi3.c1
-rw-r--r--arch/m32r/kernel/io_oaks32r.c1
-rw-r--r--arch/m32r/kernel/io_opsput.c1
-rw-r--r--arch/m32r/kernel/io_usrv.c1
-rw-r--r--arch/m32r/kernel/irq.c2
-rw-r--r--arch/m32r/kernel/m32r_ksyms.c1
-rw-r--r--arch/m32r/kernel/module.c1
-rw-r--r--arch/m32r/kernel/process.c1
-rw-r--r--arch/m32r/kernel/ptrace.c1
-rw-r--r--arch/m32r/kernel/semaphore.c1
-rw-r--r--arch/m32r/kernel/setup.c1
-rw-r--r--arch/m32r/kernel/setup_m32104ut.c9
-rw-r--r--arch/m32r/kernel/setup_m32700ut.c29
-rw-r--r--arch/m32r/kernel/setup_mappi.c17
-rw-r--r--arch/m32r/kernel/setup_mappi2.c21
-rw-r--r--arch/m32r/kernel/setup_mappi3.c21
-rw-r--r--arch/m32r/kernel/setup_oaks32r.c13
-rw-r--r--arch/m32r/kernel/setup_opsput.c29
-rw-r--r--arch/m32r/kernel/setup_usrv.c19
-rw-r--r--arch/m32r/kernel/signal.c1
-rw-r--r--arch/m32r/kernel/smpboot.c1
-rw-r--r--arch/m32r/kernel/sys_m32r.c1
-rw-r--r--arch/m32r/kernel/time.c3
-rw-r--r--arch/m32r/kernel/traps.c1
-rw-r--r--arch/m32r/kernel/vmlinux.lds.S1
-rw-r--r--arch/m32r/lib/ashxdi3.S1
-rw-r--r--arch/m32r/lib/checksum.S1
-rw-r--r--arch/m32r/lib/delay.c1
-rw-r--r--arch/m32r/lib/memcpy.S1
-rw-r--r--arch/m32r/lib/memset.S1
-rw-r--r--arch/m32r/lib/strlen.S1
-rw-r--r--arch/m32r/lib/usercopy.c1
-rw-r--r--arch/m32r/mm/cache.c1
-rw-r--r--arch/m32r/mm/discontig.c1
-rw-r--r--arch/m32r/mm/fault-nommu.c1
-rw-r--r--arch/m32r/mm/fault.c3
48 files changed, 78 insertions, 125 deletions
diff --git a/arch/m32r/boot/compressed/head.S b/arch/m32r/boot/compressed/head.S
index 234d8b1e0ac1..95a0563ff076 100644
--- a/arch/m32r/boot/compressed/head.S
+++ b/arch/m32r/boot/compressed/head.S
@@ -7,7 +7,6 @@
7 */ 7 */
8 8
9 .text 9 .text
10#include <linux/config.h>
11#include <linux/linkage.h> 10#include <linux/linkage.h>
12#include <asm/addrspace.h> 11#include <asm/addrspace.h>
13#include <asm/page.h> 12#include <asm/page.h>
diff --git a/arch/m32r/boot/compressed/m32r_sio.c b/arch/m32r/boot/compressed/m32r_sio.c
index 8f9a57271f83..bce8af5e3bb2 100644
--- a/arch/m32r/boot/compressed/m32r_sio.c
+++ b/arch/m32r/boot/compressed/m32r_sio.c
@@ -5,7 +5,6 @@
5 * 5 *
6 */ 6 */
7 7
8#include <linux/config.h>
9#include <asm/processor.h> 8#include <asm/processor.h>
10 9
11static void putc(char c); 10static void putc(char c);
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c
index 70fa799005c3..600d40e33495 100644
--- a/arch/m32r/boot/compressed/misc.c
+++ b/arch/m32r/boot/compressed/misc.c
@@ -12,7 +12,6 @@
12 * This is based on arch/sh/boot/compressed/misc.c. 12 * This is based on arch/sh/boot/compressed/misc.c.
13 */ 13 */
14 14
15#include <linux/config.h>
16#include <linux/string.h> 15#include <linux/string.h>
17 16
18/* 17/*
diff --git a/arch/m32r/boot/compressed/vmlinux.lds.S b/arch/m32r/boot/compressed/vmlinux.lds.S
index a18431759633..dd11963f6939 100644
--- a/arch/m32r/boot/compressed/vmlinux.lds.S
+++ b/arch/m32r/boot/compressed/vmlinux.lds.S
@@ -1,4 +1,3 @@
1#include <linux/config.h>
2 1
3OUTPUT_ARCH(m32r) 2OUTPUT_ARCH(m32r)
4ENTRY(startup) 3ENTRY(startup)
diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
index 398542507d84..ef843d63083d 100644
--- a/arch/m32r/boot/setup.S
+++ b/arch/m32r/boot/setup.S
@@ -11,7 +11,6 @@
11#include <asm/page.h> 11#include <asm/page.h>
12#include <asm/pgtable.h> 12#include <asm/pgtable.h>
13 13
14#include <linux/config.h>
15#include <asm/assembler.h> 14#include <asm/assembler.h>
16#include <asm/mmu_context.h> 15#include <asm/mmu_context.h>
17#include <asm/m32r.h> 16#include <asm/m32r.h>
diff --git a/arch/m32r/kernel/align.c b/arch/m32r/kernel/align.c
index 48ec29714238..ab871ccd33f8 100644
--- a/arch/m32r/kernel/align.c
+++ b/arch/m32r/kernel/align.c
@@ -4,7 +4,6 @@
4 * Copyright (c) 2003 Hitoshi Yamamoto 4 * Copyright (c) 2003 Hitoshi Yamamoto
5 */ 5 */
6 6
7#include <linux/config.h>
8#include <asm/ptrace.h> 7#include <asm/ptrace.h>
9#include <asm/uaccess.h> 8#include <asm/uaccess.h>
10 9
diff --git a/arch/m32r/kernel/entry.S b/arch/m32r/kernel/entry.S
index 920bb742b7a2..ac6d840b382b 100644
--- a/arch/m32r/kernel/entry.S
+++ b/arch/m32r/kernel/entry.S
@@ -54,7 +54,6 @@
54 * @(0x6c,sp) - orig_r0 ditto 54 * @(0x6c,sp) - orig_r0 ditto
55 */ 55 */
56 56
57#include <linux/config.h>
58#include <linux/linkage.h> 57#include <linux/linkage.h>
59#include <asm/irq.h> 58#include <asm/irq.h>
60#include <asm/unistd.h> 59#include <asm/unistd.h>
diff --git a/arch/m32r/kernel/head.S b/arch/m32r/kernel/head.S
index 3e83173995cd..0d3c8ee0e03d 100644
--- a/arch/m32r/kernel/head.S
+++ b/arch/m32r/kernel/head.S
@@ -14,7 +14,6 @@ __INIT
14__INITDATA 14__INITDATA
15 15
16 .text 16 .text
17#include <linux/config.h>
18#include <linux/linkage.h> 17#include <linux/linkage.h>
19#include <asm/segment.h> 18#include <asm/segment.h>
20#include <asm/page.h> 19#include <asm/page.h>
diff --git a/arch/m32r/kernel/io_m32104ut.c b/arch/m32r/kernel/io_m32104ut.c
index d26adab9586c..2189eca30b56 100644
--- a/arch/m32r/kernel/io_m32104ut.c
+++ b/arch/m32r/kernel/io_m32104ut.c
@@ -8,7 +8,6 @@
8 * Naoto Sugai, Hayato Fujiwara 8 * Naoto Sugai, Hayato Fujiwara
9 */ 9 */
10 10
11#include <linux/config.h>
12#include <asm/m32r.h> 11#include <asm/m32r.h>
13#include <asm/page.h> 12#include <asm/page.h>
14#include <asm/io.h> 13#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_m32700ut.c b/arch/m32r/kernel/io_m32700ut.c
index 939932d6cc00..5898f4031a0c 100644
--- a/arch/m32r/kernel/io_m32700ut.c
+++ b/arch/m32r/kernel/io_m32700ut.c
@@ -11,7 +11,6 @@
11 * archive for more details. 11 * archive for more details.
12 */ 12 */
13 13
14#include <linux/config.h>
15#include <asm/m32r.h> 14#include <asm/m32r.h>
16#include <asm/page.h> 15#include <asm/page.h>
17#include <asm/io.h> 16#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_mappi.c b/arch/m32r/kernel/io_mappi.c
index a662b537c5ba..31396789ab1b 100644
--- a/arch/m32r/kernel/io_mappi.c
+++ b/arch/m32r/kernel/io_mappi.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto 7 * Hitoshi Yamamoto
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <asm/m32r.h> 10#include <asm/m32r.h>
12#include <asm/page.h> 11#include <asm/page.h>
13#include <asm/io.h> 12#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_mappi2.c b/arch/m32r/kernel/io_mappi2.c
index e72d725606af..ecc6aa88f9ac 100644
--- a/arch/m32r/kernel/io_mappi2.c
+++ b/arch/m32r/kernel/io_mappi2.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <asm/m32r.h> 10#include <asm/m32r.h>
12#include <asm/page.h> 11#include <asm/page.h>
13#include <asm/io.h> 12#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_mappi3.c b/arch/m32r/kernel/io_mappi3.c
index ed6da930bc64..a13b5f6b07e9 100644
--- a/arch/m32r/kernel/io_mappi3.c
+++ b/arch/m32r/kernel/io_mappi3.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <asm/m32r.h> 10#include <asm/m32r.h>
12#include <asm/page.h> 11#include <asm/page.h>
13#include <asm/io.h> 12#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_oaks32r.c b/arch/m32r/kernel/io_oaks32r.c
index 910dd131c227..068bf47060f8 100644
--- a/arch/m32r/kernel/io_oaks32r.c
+++ b/arch/m32r/kernel/io_oaks32r.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <asm/m32r.h> 10#include <asm/m32r.h>
12#include <asm/page.h> 11#include <asm/page.h>
13#include <asm/io.h> 12#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_opsput.c b/arch/m32r/kernel/io_opsput.c
index bec69297db3c..da6c5f5c1f82 100644
--- a/arch/m32r/kernel/io_opsput.c
+++ b/arch/m32r/kernel/io_opsput.c
@@ -11,7 +11,6 @@
11 * archive for more details. 11 * archive for more details.
12 */ 12 */
13 13
14#include <linux/config.h>
15#include <asm/m32r.h> 14#include <asm/m32r.h>
16#include <asm/page.h> 15#include <asm/page.h>
17#include <asm/io.h> 16#include <asm/io.h>
diff --git a/arch/m32r/kernel/io_usrv.c b/arch/m32r/kernel/io_usrv.c
index 39a379af40bc..a8c0e2eceb4d 100644
--- a/arch/m32r/kernel/io_usrv.c
+++ b/arch/m32r/kernel/io_usrv.c
@@ -12,7 +12,6 @@
12 * 12 *
13 */ 13 */
14 14
15#include <linux/config.h>
16#include <asm/m32r.h> 15#include <asm/m32r.h>
17#include <asm/page.h> 16#include <asm/page.h>
18#include <asm/io.h> 17#include <asm/io.h>
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index a4634b06f675..3841861df6a2 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -54,7 +54,7 @@ int show_interrupts(struct seq_file *p, void *v)
54 for_each_online_cpu(j) 54 for_each_online_cpu(j)
55 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 55 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
56#endif 56#endif
57 seq_printf(p, " %14s", irq_desc[i].handler->typename); 57 seq_printf(p, " %14s", irq_desc[i].chip->typename);
58 seq_printf(p, " %s", action->name); 58 seq_printf(p, " %s", action->name);
59 59
60 for (action=action->next; action; action = action->next) 60 for (action=action->next; action; action = action->next)
diff --git a/arch/m32r/kernel/m32r_ksyms.c b/arch/m32r/kernel/m32r_ksyms.c
index c50330fa83b9..8cbbb0b11e0c 100644
--- a/arch/m32r/kernel/m32r_ksyms.c
+++ b/arch/m32r/kernel/m32r_ksyms.c
@@ -1,4 +1,3 @@
1#include <linux/config.h>
2#include <linux/module.h> 1#include <linux/module.h>
3#include <linux/smp.h> 2#include <linux/smp.h>
4#include <linux/user.h> 3#include <linux/user.h>
diff --git a/arch/m32r/kernel/module.c b/arch/m32r/kernel/module.c
index f6a79a016ce0..8d4205794380 100644
--- a/arch/m32r/kernel/module.c
+++ b/arch/m32r/kernel/module.c
@@ -15,7 +15,6 @@
15 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 15 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
16*/ 16*/
17 17
18#include <linux/config.h>
19#include <linux/moduleloader.h> 18#include <linux/moduleloader.h>
20#include <linux/elf.h> 19#include <linux/elf.h>
21#include <linux/vmalloc.h> 20#include <linux/vmalloc.h>
diff --git a/arch/m32r/kernel/process.c b/arch/m32r/kernel/process.c
index 065f5e719058..44cbe0ce0f8f 100644
--- a/arch/m32r/kernel/process.c
+++ b/arch/m32r/kernel/process.c
@@ -21,7 +21,6 @@
21 */ 21 */
22 22
23#include <linux/fs.h> 23#include <linux/fs.h>
24#include <linux/config.h>
25#include <linux/module.h> 24#include <linux/module.h>
26#include <linux/ptrace.h> 25#include <linux/ptrace.h>
27#include <linux/unistd.h> 26#include <linux/unistd.h>
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index 340a3bf59b88..5f02b3144875 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -14,7 +14,6 @@
14 * Copyright (C) 2000 Russell King 14 * Copyright (C) 2000 Russell King
15 */ 15 */
16 16
17#include <linux/config.h>
18#include <linux/kernel.h> 17#include <linux/kernel.h>
19#include <linux/sched.h> 18#include <linux/sched.h>
20#include <linux/mm.h> 19#include <linux/mm.h>
diff --git a/arch/m32r/kernel/semaphore.c b/arch/m32r/kernel/semaphore.c
index 9a6e6d754ddc..940c2d37cfd1 100644
--- a/arch/m32r/kernel/semaphore.c
+++ b/arch/m32r/kernel/semaphore.c
@@ -21,7 +21,6 @@
21 * 21 *
22 * rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@kvack.org> 22 * rw semaphores implemented November 1999 by Benjamin LaHaise <bcrl@kvack.org>
23 */ 23 */
24#include <linux/config.h>
25#include <linux/sched.h> 24#include <linux/sched.h>
26#include <linux/err.h> 25#include <linux/err.h>
27#include <linux/init.h> 26#include <linux/init.h>
diff --git a/arch/m32r/kernel/setup.c b/arch/m32r/kernel/setup.c
index 1ff483c8a4c9..0a6c6e677afe 100644
--- a/arch/m32r/kernel/setup.c
+++ b/arch/m32r/kernel/setup.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto 7 * Hitoshi Yamamoto
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/init.h> 10#include <linux/init.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/stddef.h> 12#include <linux/stddef.h>
diff --git a/arch/m32r/kernel/setup_m32104ut.c b/arch/m32r/kernel/setup_m32104ut.c
index 6328e1357a80..1692b321f476 100644
--- a/arch/m32r/kernel/setup_m32104ut.c
+++ b/arch/m32r/kernel/setup_m32104ut.c
@@ -8,7 +8,6 @@
8 * Naoto Sugai, Hayato Fujiwara 8 * Naoto Sugai, Hayato Fujiwara
9 */ 9 */
10 10
11#include <linux/config.h>
12#include <linux/irq.h> 11#include <linux/irq.h>
13#include <linux/kernel.h> 12#include <linux/kernel.h>
14#include <linux/init.h> 13#include <linux/init.h>
@@ -87,7 +86,7 @@ void __init init_IRQ(void)
87#if defined(CONFIG_SMC91X) 86#if defined(CONFIG_SMC91X)
88 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
89 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
90 irq_desc[M32R_IRQ_INT0].handler = &m32104ut_irq_type; 89 irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type;
91 irq_desc[M32R_IRQ_INT0].action = 0; 90 irq_desc[M32R_IRQ_INT0].action = 0;
92 irq_desc[M32R_IRQ_INT0].depth = 1; 91 irq_desc[M32R_IRQ_INT0].depth = 1;
93 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */ 92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
@@ -96,7 +95,7 @@ void __init init_IRQ(void)
96 95
97 /* MFT2 : system timer */ 96 /* MFT2 : system timer */
98 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
99 irq_desc[M32R_IRQ_MFT2].handler = &m32104ut_irq_type; 98 irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type;
100 irq_desc[M32R_IRQ_MFT2].action = 0; 99 irq_desc[M32R_IRQ_MFT2].action = 0;
101 irq_desc[M32R_IRQ_MFT2].depth = 1; 100 irq_desc[M32R_IRQ_MFT2].depth = 1;
102 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -105,7 +104,7 @@ void __init init_IRQ(void)
105#ifdef CONFIG_SERIAL_M32R_SIO 104#ifdef CONFIG_SERIAL_M32R_SIO
106 /* SIO0_R : uart receive data */ 105 /* SIO0_R : uart receive data */
107 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
108 irq_desc[M32R_IRQ_SIO0_R].handler = &m32104ut_irq_type; 107 irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type;
109 irq_desc[M32R_IRQ_SIO0_R].action = 0; 108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
110 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
111 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 110 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
@@ -113,7 +112,7 @@ void __init init_IRQ(void)
113 112
114 /* SIO0_S : uart send data */ 113 /* SIO0_S : uart send data */
115 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
116 irq_desc[M32R_IRQ_SIO0_S].handler = &m32104ut_irq_type; 115 irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type;
117 irq_desc[M32R_IRQ_SIO0_S].action = 0; 116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
118 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
119 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 118 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
diff --git a/arch/m32r/kernel/setup_m32700ut.c b/arch/m32r/kernel/setup_m32700ut.c
index fad1fc99bb27..7efc145c74c2 100644
--- a/arch/m32r/kernel/setup_m32700ut.c
+++ b/arch/m32r/kernel/setup_m32700ut.c
@@ -11,7 +11,6 @@
11 * archive for more details. 11 * archive for more details.
12 */ 12 */
13 13
14#include <linux/config.h>
15#include <linux/irq.h> 14#include <linux/irq.h>
16#include <linux/kernel.h> 15#include <linux/kernel.h>
17#include <linux/init.h> 16#include <linux/init.h>
@@ -301,7 +300,7 @@ void __init init_IRQ(void)
301#if defined(CONFIG_SMC91X) 300#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 301 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
303 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; 302 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;
304 irq_desc[M32700UT_LAN_IRQ_LAN].handler = &m32700ut_lanpld_irq_type; 303 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;
305 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0; 304 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
306 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ 305 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 306 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
@@ -310,7 +309,7 @@ void __init init_IRQ(void)
310 309
311 /* MFT2 : system timer */ 310 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 311 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
313 irq_desc[M32R_IRQ_MFT2].handler = &m32700ut_irq_type; 312 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;
314 irq_desc[M32R_IRQ_MFT2].action = 0; 313 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1; 314 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 315 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -318,7 +317,7 @@ void __init init_IRQ(void)
318 317
319 /* SIO0 : receive */ 318 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 319 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
321 irq_desc[M32R_IRQ_SIO0_R].handler = &m32700ut_irq_type; 320 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;
322 irq_desc[M32R_IRQ_SIO0_R].action = 0; 321 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 322 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 323 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -326,7 +325,7 @@ void __init init_IRQ(void)
326 325
327 /* SIO0 : send */ 326 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 327 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
329 irq_desc[M32R_IRQ_SIO0_S].handler = &m32700ut_irq_type; 328 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;
330 irq_desc[M32R_IRQ_SIO0_S].action = 0; 329 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 330 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 331 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -334,7 +333,7 @@ void __init init_IRQ(void)
334 333
335 /* SIO1 : receive */ 334 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 335 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
337 irq_desc[M32R_IRQ_SIO1_R].handler = &m32700ut_irq_type; 336 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;
338 irq_desc[M32R_IRQ_SIO1_R].action = 0; 337 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 338 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 339 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -342,7 +341,7 @@ void __init init_IRQ(void)
342 341
343 /* SIO1 : send */ 342 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 343 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
345 irq_desc[M32R_IRQ_SIO1_S].handler = &m32700ut_irq_type; 344 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;
346 irq_desc[M32R_IRQ_SIO1_S].action = 0; 345 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 346 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 347 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -350,7 +349,7 @@ void __init init_IRQ(void)
350 349
351 /* DMA1 : */ 350 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 351 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
353 irq_desc[M32R_IRQ_DMA1].handler = &m32700ut_irq_type; 352 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;
354 irq_desc[M32R_IRQ_DMA1].action = 0; 353 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1; 354 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0; 355 icu_data[M32R_IRQ_DMA1].icucr = 0;
@@ -359,7 +358,7 @@ void __init init_IRQ(void)
359#ifdef CONFIG_SERIAL_M32R_PLDSIO 358#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */ 359 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 360 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
362 irq_desc[PLD_IRQ_SIO0_RCV].handler = &m32700ut_pld_irq_type; 361 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0; 362 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ 363 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 364 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -367,7 +366,7 @@ void __init init_IRQ(void)
367 366
368 /* INT#1: SIO0 Send on PLD */ 367 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 368 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
370 irq_desc[PLD_IRQ_SIO0_SND].handler = &m32700ut_pld_irq_type; 369 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0; 370 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ 371 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 372 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -376,7 +375,7 @@ void __init init_IRQ(void)
376 375
377 /* INT#1: CFC IREQ on PLD */ 376 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 377 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
379 irq_desc[PLD_IRQ_CFIREQ].handler = &m32700ut_pld_irq_type; 378 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;
380 irq_desc[PLD_IRQ_CFIREQ].action = 0; 379 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ 380 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 381 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
@@ -384,7 +383,7 @@ void __init init_IRQ(void)
384 383
385 /* INT#1: CFC Insert on PLD */ 384 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 385 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
387 irq_desc[PLD_IRQ_CFC_INSERT].handler = &m32700ut_pld_irq_type; 386 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0; 387 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ 388 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 389 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
@@ -392,7 +391,7 @@ void __init init_IRQ(void)
392 391
393 /* INT#1: CFC Eject on PLD */ 392 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 393 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
395 irq_desc[PLD_IRQ_CFC_EJECT].handler = &m32700ut_pld_irq_type; 394 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0; 395 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ 396 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 397 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
@@ -416,7 +415,7 @@ void __init init_IRQ(void)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 415 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417 416
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 417 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].handler = &m32700ut_lcdpld_irq_type; 418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0; 419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
421 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1; 420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 421 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
@@ -434,7 +433,7 @@ void __init init_IRQ(void)
434 * INT3# is used for AR 433 * INT3# is used for AR
435 */ 434 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 435 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
437 irq_desc[M32R_IRQ_INT3].handler = &m32700ut_irq_type; 436 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;
438 irq_desc[M32R_IRQ_INT3].action = 0; 437 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1; 438 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 439 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
diff --git a/arch/m32r/kernel/setup_mappi.c b/arch/m32r/kernel/setup_mappi.c
index 00f253209cb3..67dbbdc9d111 100644
--- a/arch/m32r/kernel/setup_mappi.c
+++ b/arch/m32r/kernel/setup_mappi.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto 7 * Hitoshi Yamamoto
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
@@ -86,7 +85,7 @@ void __init init_IRQ(void)
86#ifdef CONFIG_NE2000 85#ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */ 86 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 87 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
89 irq_desc[M32R_IRQ_INT0].handler = &mappi_irq_type; 88 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;
90 irq_desc[M32R_IRQ_INT0].action = 0; 89 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1; 90 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 91 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
@@ -95,7 +94,7 @@ void __init init_IRQ(void)
95 94
96 /* MFT2 : system timer */ 95 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 96 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
98 irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type; 97 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
99 irq_desc[M32R_IRQ_MFT2].action = 0; 98 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1; 99 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 100 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -104,7 +103,7 @@ void __init init_IRQ(void)
104#ifdef CONFIG_SERIAL_M32R_SIO 103#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 104 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 105 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
107 irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type; 106 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
108 irq_desc[M32R_IRQ_SIO0_R].action = 0; 107 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 108 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 109 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -112,7 +111,7 @@ void __init init_IRQ(void)
112 111
113 /* SIO0_S : uart send data */ 112 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 113 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
115 irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type; 114 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
116 irq_desc[M32R_IRQ_SIO0_S].action = 0; 115 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 116 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 117 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -120,7 +119,7 @@ void __init init_IRQ(void)
120 119
121 /* SIO1_R : uart receive data */ 120 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
123 irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type; 122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
124 irq_desc[M32R_IRQ_SIO1_R].action = 0; 123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 125 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -128,7 +127,7 @@ void __init init_IRQ(void)
128 127
129 /* SIO1_S : uart send data */ 128 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
131 irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type; 130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
132 irq_desc[M32R_IRQ_SIO1_S].action = 0; 131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 133 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -138,7 +137,7 @@ void __init init_IRQ(void)
138#if defined(CONFIG_M32R_PCC) 137#if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */ 138 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
141 irq_desc[M32R_IRQ_INT1].handler = &mappi_irq_type; 140 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
142 irq_desc[M32R_IRQ_INT1].action = 0; 141 irq_desc[M32R_IRQ_INT1].action = 0;
143 irq_desc[M32R_IRQ_INT1].depth = 1; 142 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
@@ -146,7 +145,7 @@ void __init init_IRQ(void)
146 145
147 /* INT2 : pccard1 interrupt */ 146 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; 147 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;
149 irq_desc[M32R_IRQ_INT2].handler = &mappi_irq_type; 148 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;
150 irq_desc[M32R_IRQ_INT2].action = 0; 149 irq_desc[M32R_IRQ_INT2].action = 0;
151 irq_desc[M32R_IRQ_INT2].depth = 1; 150 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 151 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
diff --git a/arch/m32r/kernel/setup_mappi2.c b/arch/m32r/kernel/setup_mappi2.c
index eebc9d8b4e72..55abb2102750 100644
--- a/arch/m32r/kernel/setup_mappi2.c
+++ b/arch/m32r/kernel/setup_mappi2.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
@@ -87,7 +86,7 @@ void __init init_IRQ(void)
87#if defined(CONFIG_SMC91X) 86#if defined(CONFIG_SMC91X)
88 /* INT0 : LAN controller (SMC91111) */ 87 /* INT0 : LAN controller (SMC91111) */
89 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
90 irq_desc[M32R_IRQ_INT0].handler = &mappi2_irq_type; 89 irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type;
91 irq_desc[M32R_IRQ_INT0].action = 0; 90 irq_desc[M32R_IRQ_INT0].action = 0;
92 irq_desc[M32R_IRQ_INT0].depth = 1; 91 irq_desc[M32R_IRQ_INT0].depth = 1;
93 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
@@ -96,7 +95,7 @@ void __init init_IRQ(void)
96 95
97 /* MFT2 : system timer */ 96 /* MFT2 : system timer */
98 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
99 irq_desc[M32R_IRQ_MFT2].handler = &mappi2_irq_type; 98 irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type;
100 irq_desc[M32R_IRQ_MFT2].action = 0; 99 irq_desc[M32R_IRQ_MFT2].action = 0;
101 irq_desc[M32R_IRQ_MFT2].depth = 1; 100 irq_desc[M32R_IRQ_MFT2].depth = 1;
102 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -105,7 +104,7 @@ void __init init_IRQ(void)
105#ifdef CONFIG_SERIAL_M32R_SIO 104#ifdef CONFIG_SERIAL_M32R_SIO
106 /* SIO0_R : uart receive data */ 105 /* SIO0_R : uart receive data */
107 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
108 irq_desc[M32R_IRQ_SIO0_R].handler = &mappi2_irq_type; 107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type;
109 irq_desc[M32R_IRQ_SIO0_R].action = 0; 108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
110 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
111 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 110 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -113,14 +112,14 @@ void __init init_IRQ(void)
113 112
114 /* SIO0_S : uart send data */ 113 /* SIO0_S : uart send data */
115 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
116 irq_desc[M32R_IRQ_SIO0_S].handler = &mappi2_irq_type; 115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type;
117 irq_desc[M32R_IRQ_SIO0_S].action = 0; 116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
118 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
119 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 118 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
120 disable_mappi2_irq(M32R_IRQ_SIO0_S); 119 disable_mappi2_irq(M32R_IRQ_SIO0_S);
121 /* SIO1_R : uart receive data */ 120 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
123 irq_desc[M32R_IRQ_SIO1_R].handler = &mappi2_irq_type; 122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type;
124 irq_desc[M32R_IRQ_SIO1_R].action = 0; 123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 125 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -128,7 +127,7 @@ void __init init_IRQ(void)
128 127
129 /* SIO1_S : uart send data */ 128 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
131 irq_desc[M32R_IRQ_SIO1_S].handler = &mappi2_irq_type; 130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type;
132 irq_desc[M32R_IRQ_SIO1_S].action = 0; 131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 133 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -138,7 +137,7 @@ void __init init_IRQ(void)
138#if defined(CONFIG_USB) 137#if defined(CONFIG_USB)
139 /* INT1 : USB Host controller interrupt */ 138 /* INT1 : USB Host controller interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
141 irq_desc[M32R_IRQ_INT1].handler = &mappi2_irq_type; 140 irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;
142 irq_desc[M32R_IRQ_INT1].action = 0; 141 irq_desc[M32R_IRQ_INT1].action = 0;
143 irq_desc[M32R_IRQ_INT1].depth = 1; 142 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
@@ -147,7 +146,7 @@ void __init init_IRQ(void)
147 146
148 /* ICUCR40: CFC IREQ */ 147 /* ICUCR40: CFC IREQ */
149 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
150 irq_desc[PLD_IRQ_CFIREQ].handler = &mappi2_irq_type; 149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type;
151 irq_desc[PLD_IRQ_CFIREQ].action = 0; 150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
152 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ 151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
153 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
@@ -156,7 +155,7 @@ void __init init_IRQ(void)
156#if defined(CONFIG_M32R_CFC) 155#if defined(CONFIG_M32R_CFC)
157 /* ICUCR41: CFC Insert */ 156 /* ICUCR41: CFC Insert */
158 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
159 irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi2_irq_type; 158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type;
160 irq_desc[PLD_IRQ_CFC_INSERT].action = 0; 159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
161 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ 160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
162 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
@@ -164,7 +163,7 @@ void __init init_IRQ(void)
164 163
165 /* ICUCR42: CFC Eject */ 164 /* ICUCR42: CFC Eject */
166 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 165 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
167 irq_desc[PLD_IRQ_CFC_EJECT].handler = &mappi2_irq_type; 166 irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type;
168 irq_desc[PLD_IRQ_CFC_EJECT].action = 0; 167 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
169 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ 168 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
170 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 169 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
diff --git a/arch/m32r/kernel/setup_mappi3.c b/arch/m32r/kernel/setup_mappi3.c
index d2ff021e2d3d..93dc010c7fc3 100644
--- a/arch/m32r/kernel/setup_mappi3.c
+++ b/arch/m32r/kernel/setup_mappi3.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
@@ -87,7 +86,7 @@ void __init init_IRQ(void)
87#if defined(CONFIG_SMC91X) 86#if defined(CONFIG_SMC91X)
88 /* INT0 : LAN controller (SMC91111) */ 87 /* INT0 : LAN controller (SMC91111) */
89 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;
90 irq_desc[M32R_IRQ_INT0].handler = &mappi3_irq_type; 89 irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type;
91 irq_desc[M32R_IRQ_INT0].action = 0; 90 irq_desc[M32R_IRQ_INT0].action = 0;
92 irq_desc[M32R_IRQ_INT0].depth = 1; 91 irq_desc[M32R_IRQ_INT0].depth = 1;
93 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
@@ -96,7 +95,7 @@ void __init init_IRQ(void)
96 95
97 /* MFT2 : system timer */ 96 /* MFT2 : system timer */
98 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
99 irq_desc[M32R_IRQ_MFT2].handler = &mappi3_irq_type; 98 irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type;
100 irq_desc[M32R_IRQ_MFT2].action = 0; 99 irq_desc[M32R_IRQ_MFT2].action = 0;
101 irq_desc[M32R_IRQ_MFT2].depth = 1; 100 irq_desc[M32R_IRQ_MFT2].depth = 1;
102 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -105,7 +104,7 @@ void __init init_IRQ(void)
105#ifdef CONFIG_SERIAL_M32R_SIO 104#ifdef CONFIG_SERIAL_M32R_SIO
106 /* SIO0_R : uart receive data */ 105 /* SIO0_R : uart receive data */
107 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
108 irq_desc[M32R_IRQ_SIO0_R].handler = &mappi3_irq_type; 107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type;
109 irq_desc[M32R_IRQ_SIO0_R].action = 0; 108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
110 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
111 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 110 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -113,14 +112,14 @@ void __init init_IRQ(void)
113 112
114 /* SIO0_S : uart send data */ 113 /* SIO0_S : uart send data */
115 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
116 irq_desc[M32R_IRQ_SIO0_S].handler = &mappi3_irq_type; 115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type;
117 irq_desc[M32R_IRQ_SIO0_S].action = 0; 116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
118 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
119 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 118 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
120 disable_mappi3_irq(M32R_IRQ_SIO0_S); 119 disable_mappi3_irq(M32R_IRQ_SIO0_S);
121 /* SIO1_R : uart receive data */ 120 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
123 irq_desc[M32R_IRQ_SIO1_R].handler = &mappi3_irq_type; 122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type;
124 irq_desc[M32R_IRQ_SIO1_R].action = 0; 123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 125 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -128,7 +127,7 @@ void __init init_IRQ(void)
128 127
129 /* SIO1_S : uart send data */ 128 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
131 irq_desc[M32R_IRQ_SIO1_S].handler = &mappi3_irq_type; 130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type;
132 irq_desc[M32R_IRQ_SIO1_S].action = 0; 131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 133 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -138,7 +137,7 @@ void __init init_IRQ(void)
138#if defined(CONFIG_USB) 137#if defined(CONFIG_USB)
139 /* INT1 : USB Host controller interrupt */ 138 /* INT1 : USB Host controller interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
141 irq_desc[M32R_IRQ_INT1].handler = &mappi3_irq_type; 140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
142 irq_desc[M32R_IRQ_INT1].action = 0; 141 irq_desc[M32R_IRQ_INT1].action = 0;
143 irq_desc[M32R_IRQ_INT1].depth = 1; 142 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
@@ -147,7 +146,7 @@ void __init init_IRQ(void)
147 146
148 /* CFC IREQ */ 147 /* CFC IREQ */
149 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
150 irq_desc[PLD_IRQ_CFIREQ].handler = &mappi3_irq_type; 149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type;
151 irq_desc[PLD_IRQ_CFIREQ].action = 0; 150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
152 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ 151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
153 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
@@ -156,7 +155,7 @@ void __init init_IRQ(void)
156#if defined(CONFIG_M32R_CFC) 155#if defined(CONFIG_M32R_CFC)
157 /* ICUCR41: CFC Insert & eject */ 156 /* ICUCR41: CFC Insert & eject */
158 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
159 irq_desc[PLD_IRQ_CFC_INSERT].handler = &mappi3_irq_type; 158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type;
160 irq_desc[PLD_IRQ_CFC_INSERT].action = 0; 159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
161 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ 160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
162 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
@@ -166,7 +165,7 @@ void __init init_IRQ(void)
166 165
167 /* IDE IREQ */ 166 /* IDE IREQ */
168 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; 167 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED;
169 irq_desc[PLD_IRQ_IDEIREQ].handler = &mappi3_irq_type; 168 irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type;
170 irq_desc[PLD_IRQ_IDEIREQ].action = 0; 169 irq_desc[PLD_IRQ_IDEIREQ].action = 0;
171 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */ 170 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
172 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 171 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
diff --git a/arch/m32r/kernel/setup_oaks32r.c b/arch/m32r/kernel/setup_oaks32r.c
index 0e9e63538c0f..cd62598e3cea 100644
--- a/arch/m32r/kernel/setup_oaks32r.c
+++ b/arch/m32r/kernel/setup_oaks32r.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto, Mamoru Sakugawa 7 * Hitoshi Yamamoto, Mamoru Sakugawa
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
@@ -85,7 +84,7 @@ void __init init_IRQ(void)
85#ifdef CONFIG_NE2000 84#ifdef CONFIG_NE2000
86 /* INT3 : LAN controller (RTL8019AS) */ 85 /* INT3 : LAN controller (RTL8019AS) */
87 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 86 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
88 irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type; 87 irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
89 irq_desc[M32R_IRQ_INT3].action = 0; 88 irq_desc[M32R_IRQ_INT3].action = 0;
90 irq_desc[M32R_IRQ_INT3].depth = 1; 89 irq_desc[M32R_IRQ_INT3].depth = 1;
91 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 90 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
@@ -94,7 +93,7 @@ void __init init_IRQ(void)
94 93
95 /* MFT2 : system timer */ 94 /* MFT2 : system timer */
96 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 95 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
97 irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type; 96 irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
98 irq_desc[M32R_IRQ_MFT2].action = 0; 97 irq_desc[M32R_IRQ_MFT2].action = 0;
99 irq_desc[M32R_IRQ_MFT2].depth = 1; 98 irq_desc[M32R_IRQ_MFT2].depth = 1;
100 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 99 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -103,7 +102,7 @@ void __init init_IRQ(void)
103#ifdef CONFIG_SERIAL_M32R_SIO 102#ifdef CONFIG_SERIAL_M32R_SIO
104 /* SIO0_R : uart receive data */ 103 /* SIO0_R : uart receive data */
105 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 104 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
106 irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type; 105 irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
107 irq_desc[M32R_IRQ_SIO0_R].action = 0; 106 irq_desc[M32R_IRQ_SIO0_R].action = 0;
108 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 107 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
109 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 108 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -111,7 +110,7 @@ void __init init_IRQ(void)
111 110
112 /* SIO0_S : uart send data */ 111 /* SIO0_S : uart send data */
113 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 112 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
114 irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type; 113 irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
115 irq_desc[M32R_IRQ_SIO0_S].action = 0; 114 irq_desc[M32R_IRQ_SIO0_S].action = 0;
116 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 115 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
117 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 116 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -119,7 +118,7 @@ void __init init_IRQ(void)
119 118
120 /* SIO1_R : uart receive data */ 119 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 120 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
122 irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type; 121 irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
123 irq_desc[M32R_IRQ_SIO1_R].action = 0; 122 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 123 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 124 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -127,7 +126,7 @@ void __init init_IRQ(void)
127 126
128 /* SIO1_S : uart send data */ 127 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 128 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
130 irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type; 129 irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
131 irq_desc[M32R_IRQ_SIO1_S].action = 0; 130 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 131 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 132 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
diff --git a/arch/m32r/kernel/setup_opsput.c b/arch/m32r/kernel/setup_opsput.c
index 548e8fc7949b..61d3b01cbe07 100644
--- a/arch/m32r/kernel/setup_opsput.c
+++ b/arch/m32r/kernel/setup_opsput.c
@@ -12,7 +12,6 @@
12 * archive for more details. 12 * archive for more details.
13 */ 13 */
14 14
15#include <linux/config.h>
16#include <linux/irq.h> 15#include <linux/irq.h>
17#include <linux/kernel.h> 16#include <linux/kernel.h>
18#include <linux/init.h> 17#include <linux/init.h>
@@ -302,7 +301,7 @@ void __init init_IRQ(void)
302#if defined(CONFIG_SMC91X) 301#if defined(CONFIG_SMC91X)
303 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
304 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; 303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
305 irq_desc[OPSPUT_LAN_IRQ_LAN].handler = &opsput_lanpld_irq_type; 304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0; 305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
307 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */ 306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
308 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 307 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
@@ -311,7 +310,7 @@ void __init init_IRQ(void)
311 310
312 /* MFT2 : system timer */ 311 /* MFT2 : system timer */
313 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
314 irq_desc[M32R_IRQ_MFT2].handler = &opsput_irq_type; 313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type;
315 irq_desc[M32R_IRQ_MFT2].action = 0; 314 irq_desc[M32R_IRQ_MFT2].action = 0;
316 irq_desc[M32R_IRQ_MFT2].depth = 1; 315 irq_desc[M32R_IRQ_MFT2].depth = 1;
317 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -319,7 +318,7 @@ void __init init_IRQ(void)
319 318
320 /* SIO0 : receive */ 319 /* SIO0 : receive */
321 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
322 irq_desc[M32R_IRQ_SIO0_R].handler = &opsput_irq_type; 321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type;
323 irq_desc[M32R_IRQ_SIO0_R].action = 0; 322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
324 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
325 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 324 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -327,7 +326,7 @@ void __init init_IRQ(void)
327 326
328 /* SIO0 : send */ 327 /* SIO0 : send */
329 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
330 irq_desc[M32R_IRQ_SIO0_S].handler = &opsput_irq_type; 329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type;
331 irq_desc[M32R_IRQ_SIO0_S].action = 0; 330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
332 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
333 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 332 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -335,7 +334,7 @@ void __init init_IRQ(void)
335 334
336 /* SIO1 : receive */ 335 /* SIO1 : receive */
337 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
338 irq_desc[M32R_IRQ_SIO1_R].handler = &opsput_irq_type; 337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type;
339 irq_desc[M32R_IRQ_SIO1_R].action = 0; 338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
340 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
341 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 340 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -343,7 +342,7 @@ void __init init_IRQ(void)
343 342
344 /* SIO1 : send */ 343 /* SIO1 : send */
345 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
346 irq_desc[M32R_IRQ_SIO1_S].handler = &opsput_irq_type; 345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type;
347 irq_desc[M32R_IRQ_SIO1_S].action = 0; 346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
348 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
349 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 348 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -351,7 +350,7 @@ void __init init_IRQ(void)
351 350
352 /* DMA1 : */ 351 /* DMA1 : */
353 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
354 irq_desc[M32R_IRQ_DMA1].handler = &opsput_irq_type; 353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type;
355 irq_desc[M32R_IRQ_DMA1].action = 0; 354 irq_desc[M32R_IRQ_DMA1].action = 0;
356 irq_desc[M32R_IRQ_DMA1].depth = 1; 355 irq_desc[M32R_IRQ_DMA1].depth = 1;
357 icu_data[M32R_IRQ_DMA1].icucr = 0; 356 icu_data[M32R_IRQ_DMA1].icucr = 0;
@@ -360,7 +359,7 @@ void __init init_IRQ(void)
360#ifdef CONFIG_SERIAL_M32R_PLDSIO 359#ifdef CONFIG_SERIAL_M32R_PLDSIO
361 /* INT#1: SIO0 Receive on PLD */ 360 /* INT#1: SIO0 Receive on PLD */
362 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
363 irq_desc[PLD_IRQ_SIO0_RCV].handler = &opsput_pld_irq_type; 362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type;
364 irq_desc[PLD_IRQ_SIO0_RCV].action = 0; 363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
365 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */ 364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
366 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -368,7 +367,7 @@ void __init init_IRQ(void)
368 367
369 /* INT#1: SIO0 Send on PLD */ 368 /* INT#1: SIO0 Send on PLD */
370 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
371 irq_desc[PLD_IRQ_SIO0_SND].handler = &opsput_pld_irq_type; 370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type;
372 irq_desc[PLD_IRQ_SIO0_SND].action = 0; 371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
373 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */ 372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
374 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
@@ -378,7 +377,7 @@ void __init init_IRQ(void)
378#if defined(CONFIG_M32R_CFC) 377#if defined(CONFIG_M32R_CFC)
379 /* INT#1: CFC IREQ on PLD */ 378 /* INT#1: CFC IREQ on PLD */
380 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 379 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
381 irq_desc[PLD_IRQ_CFIREQ].handler = &opsput_pld_irq_type; 380 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type;
382 irq_desc[PLD_IRQ_CFIREQ].action = 0; 381 irq_desc[PLD_IRQ_CFIREQ].action = 0;
383 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */ 382 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
384 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 383 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
@@ -386,7 +385,7 @@ void __init init_IRQ(void)
386 385
387 /* INT#1: CFC Insert on PLD */ 386 /* INT#1: CFC Insert on PLD */
388 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 387 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
389 irq_desc[PLD_IRQ_CFC_INSERT].handler = &opsput_pld_irq_type; 388 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type;
390 irq_desc[PLD_IRQ_CFC_INSERT].action = 0; 389 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
391 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */ 390 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
392 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 391 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
@@ -394,7 +393,7 @@ void __init init_IRQ(void)
394 393
395 /* INT#1: CFC Eject on PLD */ 394 /* INT#1: CFC Eject on PLD */
396 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 395 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
397 irq_desc[PLD_IRQ_CFC_EJECT].handler = &opsput_pld_irq_type; 396 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type;
398 irq_desc[PLD_IRQ_CFC_EJECT].action = 0; 397 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
399 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */ 398 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
400 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 399 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
@@ -420,7 +419,7 @@ void __init init_IRQ(void)
420 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 419 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
421 420
422 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
423 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].handler = &opsput_lcdpld_irq_type; 422 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type;
424 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; 423 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
425 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1; 424 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
426 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 425 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
@@ -438,7 +437,7 @@ void __init init_IRQ(void)
438 * INT3# is used for AR 437 * INT3# is used for AR
439 */ 438 */
440 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 439 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
441 irq_desc[M32R_IRQ_INT3].handler = &opsput_irq_type; 440 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type;
442 irq_desc[M32R_IRQ_INT3].action = 0; 441 irq_desc[M32R_IRQ_INT3].action = 0;
443 irq_desc[M32R_IRQ_INT3].depth = 1; 442 irq_desc[M32R_IRQ_INT3].depth = 1;
444 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 443 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
diff --git a/arch/m32r/kernel/setup_usrv.c b/arch/m32r/kernel/setup_usrv.c
index 64be659a23e7..f5b4b5ac31e7 100644
--- a/arch/m32r/kernel/setup_usrv.c
+++ b/arch/m32r/kernel/setup_usrv.c
@@ -7,7 +7,6 @@
7 * Hitoshi Yamamoto 7 * Hitoshi Yamamoto
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/kernel.h> 11#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
@@ -158,7 +157,7 @@ void __init init_IRQ(void)
158 157
159 /* MFT2 : system timer */ 158 /* MFT2 : system timer */
160 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
161 irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type; 160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
162 irq_desc[M32R_IRQ_MFT2].action = 0; 161 irq_desc[M32R_IRQ_MFT2].action = 0;
163 irq_desc[M32R_IRQ_MFT2].depth = 1; 162 irq_desc[M32R_IRQ_MFT2].depth = 1;
164 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
@@ -167,7 +166,7 @@ void __init init_IRQ(void)
167#if defined(CONFIG_SERIAL_M32R_SIO) 166#if defined(CONFIG_SERIAL_M32R_SIO)
168 /* SIO0_R : uart receive data */ 167 /* SIO0_R : uart receive data */
169 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
170 irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type; 169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
171 irq_desc[M32R_IRQ_SIO0_R].action = 0; 170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
172 irq_desc[M32R_IRQ_SIO0_R].depth = 1; 171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
173 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 172 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
@@ -175,7 +174,7 @@ void __init init_IRQ(void)
175 174
176 /* SIO0_S : uart send data */ 175 /* SIO0_S : uart send data */
177 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
178 irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type; 177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
179 irq_desc[M32R_IRQ_SIO0_S].action = 0; 178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
180 irq_desc[M32R_IRQ_SIO0_S].depth = 1; 179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
181 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 180 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
@@ -183,7 +182,7 @@ void __init init_IRQ(void)
183 182
184 /* SIO1_R : uart receive data */ 183 /* SIO1_R : uart receive data */
185 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
186 irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type; 185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
187 irq_desc[M32R_IRQ_SIO1_R].action = 0; 186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
188 irq_desc[M32R_IRQ_SIO1_R].depth = 1; 187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
189 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 188 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
@@ -191,7 +190,7 @@ void __init init_IRQ(void)
191 190
192 /* SIO1_S : uart send data */ 191 /* SIO1_S : uart send data */
193 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
194 irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type; 193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
195 irq_desc[M32R_IRQ_SIO1_S].action = 0; 194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
196 irq_desc[M32R_IRQ_SIO1_S].depth = 1; 195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
197 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 196 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
@@ -201,7 +200,7 @@ void __init init_IRQ(void)
201 /* INT#67-#71: CFC#0 IREQ on PLD */ 200 /* INT#67-#71: CFC#0 IREQ on PLD */
202 for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) { 201 for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) {
203 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; 202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
204 irq_desc[PLD_IRQ_CF0 + i].handler = &m32700ut_pld_irq_type; 203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
205 irq_desc[PLD_IRQ_CF0 + i].action = 0; 204 irq_desc[PLD_IRQ_CF0 + i].action = 0;
206 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ 205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
207 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
@@ -212,7 +211,7 @@ void __init init_IRQ(void)
212#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
213 /* INT#76: 16552D#0 IREQ on PLD */ 212 /* INT#76: 16552D#0 IREQ on PLD */
214 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; 213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
215 irq_desc[PLD_IRQ_UART0].handler = &m32700ut_pld_irq_type; 214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
216 irq_desc[PLD_IRQ_UART0].action = 0; 215 irq_desc[PLD_IRQ_UART0].action = 0;
217 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ 216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
218 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
@@ -221,7 +220,7 @@ void __init init_IRQ(void)
221 220
222 /* INT#77: 16552D#1 IREQ on PLD */ 221 /* INT#77: 16552D#1 IREQ on PLD */
223 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; 222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
224 irq_desc[PLD_IRQ_UART1].handler = &m32700ut_pld_irq_type; 223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
225 irq_desc[PLD_IRQ_UART1].action = 0; 224 irq_desc[PLD_IRQ_UART1].action = 0;
226 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ 225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
227 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
@@ -232,7 +231,7 @@ void __init init_IRQ(void)
232#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
233 /* INT#80: AK4524 IREQ on PLD */ 232 /* INT#80: AK4524 IREQ on PLD */
234 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; 233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
235 irq_desc[PLD_IRQ_SNDINT].handler = &m32700ut_pld_irq_type; 234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
236 irq_desc[PLD_IRQ_SNDINT].action = 0; 235 irq_desc[PLD_IRQ_SNDINT].action = 0;
237 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ 236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
238 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
index 6498ee70bb73..a9174efe80cb 100644
--- a/arch/m32r/kernel/signal.c
+++ b/arch/m32r/kernel/signal.c
@@ -10,7 +10,6 @@
10 * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes 10 * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes
11 */ 11 */
12 12
13#include <linux/config.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/mm.h> 14#include <linux/mm.h>
16#include <linux/smp.h> 15#include <linux/smp.h>
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index 840b4348bf0c..fa7865609495 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -40,7 +40,6 @@
40 */ 40 */
41 41
42#include <linux/module.h> 42#include <linux/module.h>
43#include <linux/config.h>
44#include <linux/init.h> 43#include <linux/init.h>
45#include <linux/kernel.h> 44#include <linux/kernel.h>
46#include <linux/mm.h> 45#include <linux/mm.h>
diff --git a/arch/m32r/kernel/sys_m32r.c b/arch/m32r/kernel/sys_m32r.c
index 670cb49210af..a9cea32eb824 100644
--- a/arch/m32r/kernel/sys_m32r.c
+++ b/arch/m32r/kernel/sys_m32r.c
@@ -7,7 +7,6 @@
7 * Taken from i386 version. 7 * Taken from i386 version.
8 */ 8 */
9 9
10#include <linux/config.h>
11#include <linux/errno.h> 10#include <linux/errno.h>
12#include <linux/sched.h> 11#include <linux/sched.h>
13#include <linux/mm.h> 12#include <linux/mm.h>
diff --git a/arch/m32r/kernel/time.c b/arch/m32r/kernel/time.c
index b8e68b542302..ded0be07a476 100644
--- a/arch/m32r/kernel/time.c
+++ b/arch/m32r/kernel/time.c
@@ -17,7 +17,6 @@
17 17
18#undef DEBUG_TIMER 18#undef DEBUG_TIMER
19 19
20#include <linux/config.h>
21#include <linux/errno.h> 20#include <linux/errno.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/module.h> 22#include <linux/module.h>
@@ -238,7 +237,7 @@ irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
238 return IRQ_HANDLED; 237 return IRQ_HANDLED;
239} 238}
240 239
241struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, 240struct irqaction irq0 = { timer_interrupt, IRQF_DISABLED, CPU_MASK_NONE,
242 "MFT2", NULL, NULL }; 241 "MFT2", NULL, NULL };
243 242
244void __init time_init(void) 243void __init time_init(void)
diff --git a/arch/m32r/kernel/traps.c b/arch/m32r/kernel/traps.c
index 5fe8ed6d62dc..c1daf2c40c7c 100644
--- a/arch/m32r/kernel/traps.c
+++ b/arch/m32r/kernel/traps.c
@@ -9,7 +9,6 @@
9 * 'traps.c' handles hardware traps and faults after we have saved some 9 * 'traps.c' handles hardware traps and faults after we have saved some
10 * state in 'entry.S'. 10 * state in 'entry.S'.
11 */ 11 */
12#include <linux/config.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/kallsyms.h> 14#include <linux/kallsyms.h>
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
index 729a2645a03f..13c7bb698e37 100644
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ b/arch/m32r/kernel/vmlinux.lds.S
@@ -1,7 +1,6 @@
1/* ld script to make M32R Linux kernel 1/* ld script to make M32R Linux kernel
2 */ 2 */
3 3
4#include <linux/config.h>
5#include <asm-generic/vmlinux.lds.h> 4#include <asm-generic/vmlinux.lds.h>
6#include <asm/addrspace.h> 5#include <asm/addrspace.h>
7#include <asm/page.h> 6#include <asm/page.h>
diff --git a/arch/m32r/lib/ashxdi3.S b/arch/m32r/lib/ashxdi3.S
index 78effca9d97a..107594b65d58 100644
--- a/arch/m32r/lib/ashxdi3.S
+++ b/arch/m32r/lib/ashxdi3.S
@@ -6,7 +6,6 @@
6 */ 6 */
7/* $Id$ */ 7/* $Id$ */
8 8
9#include <linux/config.h>
10 9
11; 10;
12; input (r0,r1) src 11; input (r0,r1) src
diff --git a/arch/m32r/lib/checksum.S b/arch/m32r/lib/checksum.S
index f6fc1bdb87e4..cfbe00e5184a 100644
--- a/arch/m32r/lib/checksum.S
+++ b/arch/m32r/lib/checksum.S
@@ -28,7 +28,6 @@
28/* $Id$ */ 28/* $Id$ */
29 29
30 30
31#include <linux/config.h>
32#include <linux/linkage.h> 31#include <linux/linkage.h>
33#include <asm/assembler.h> 32#include <asm/assembler.h>
34#include <asm/errno.h> 33#include <asm/errno.h>
diff --git a/arch/m32r/lib/delay.c b/arch/m32r/lib/delay.c
index fb29632c7eaa..06382a38c318 100644
--- a/arch/m32r/lib/delay.c
+++ b/arch/m32r/lib/delay.c
@@ -7,7 +7,6 @@
7 7
8/* $Id$ */ 8/* $Id$ */
9 9
10#include <linux/config.h>
11#include <linux/param.h> 10#include <linux/param.h>
12#ifdef CONFIG_SMP 11#ifdef CONFIG_SMP
13#include <linux/sched.h> 12#include <linux/sched.h>
diff --git a/arch/m32r/lib/memcpy.S b/arch/m32r/lib/memcpy.S
index 800898a2d2e3..2089a215314e 100644
--- a/arch/m32r/lib/memcpy.S
+++ b/arch/m32r/lib/memcpy.S
@@ -14,7 +14,6 @@
14 14
15 15
16 .text 16 .text
17#include <linux/config.h>
18#include <linux/linkage.h> 17#include <linux/linkage.h>
19#include <asm/assembler.h> 18#include <asm/assembler.h>
20 19
diff --git a/arch/m32r/lib/memset.S b/arch/m32r/lib/memset.S
index 6e26df120acb..b47fa3537aa4 100644
--- a/arch/m32r/lib/memset.S
+++ b/arch/m32r/lib/memset.S
@@ -14,7 +14,6 @@
14 */ 14 */
15/* $Id$ */ 15/* $Id$ */
16 16
17#include <linux/config.h>
18 17
19 .text 18 .text
20 .global memset 19 .global memset
diff --git a/arch/m32r/lib/strlen.S b/arch/m32r/lib/strlen.S
index 8d23cfbd600c..5f41aacd7b3e 100644
--- a/arch/m32r/lib/strlen.S
+++ b/arch/m32r/lib/strlen.S
@@ -9,7 +9,6 @@
9/* $Id$ */ 9/* $Id$ */
10 10
11 11
12#include <linux/config.h>
13#include <linux/linkage.h> 12#include <linux/linkage.h>
14#include <asm/assembler.h> 13#include <asm/assembler.h>
15 14
diff --git a/arch/m32r/lib/usercopy.c b/arch/m32r/lib/usercopy.c
index 2d1dd2106c4d..896cef1aca5f 100644
--- a/arch/m32r/lib/usercopy.c
+++ b/arch/m32r/lib/usercopy.c
@@ -6,7 +6,6 @@
6 * Copyright 1997 Linus Torvalds 6 * Copyright 1997 Linus Torvalds
7 * Copyright 2001, 2002, 2004 Hirokazu Takata 7 * Copyright 2001, 2002, 2004 Hirokazu Takata
8 */ 8 */
9#include <linux/config.h>
10#include <linux/prefetch.h> 9#include <linux/prefetch.h>
11#include <linux/string.h> 10#include <linux/string.h>
12#include <linux/thread_info.h> 11#include <linux/thread_info.h>
diff --git a/arch/m32r/mm/cache.c b/arch/m32r/mm/cache.c
index 9f54dd937013..fac759584875 100644
--- a/arch/m32r/mm/cache.c
+++ b/arch/m32r/mm/cache.c
@@ -4,7 +4,6 @@
4 * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara 4 * Copyright (C) 2002-2005 Hirokazu Takata, Hayato Fujiwara
5 */ 5 */
6 6
7#include <linux/config.h>
8#include <asm/pgtable.h> 7#include <asm/pgtable.h>
9 8
10#undef MCCR 9#undef MCCR
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index cf610a7c5ff0..abb34ccd5986 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -6,7 +6,6 @@
6 * Copyright (c) 2003 Hitoshi Yamamoto 6 * Copyright (c) 2003 Hitoshi Yamamoto
7 */ 7 */
8 8
9#include <linux/config.h>
10#include <linux/mm.h> 9#include <linux/mm.h>
11#include <linux/bootmem.h> 10#include <linux/bootmem.h>
12#include <linux/mmzone.h> 11#include <linux/mmzone.h>
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c
index d9d488d782e8..03fc4c858e0e 100644
--- a/arch/m32r/mm/fault-nommu.c
+++ b/arch/m32r/mm/fault-nommu.c
@@ -9,7 +9,6 @@
9 9
10/* $Id: fault-nommu.c,v 1.1 2004/03/30 06:40:59 sakugawa Exp $ */ 10/* $Id: fault-nommu.c,v 1.1 2004/03/30 06:40:59 sakugawa Exp $ */
11 11
12#include <linux/config.h>
13#include <linux/signal.h> 12#include <linux/signal.h>
14#include <linux/sched.h> 13#include <linux/sched.h>
15#include <linux/kernel.h> 14#include <linux/kernel.h>
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
index bf7fb58ef02c..dc18a33eefef 100644
--- a/arch/m32r/mm/fault.c
+++ b/arch/m32r/mm/fault.c
@@ -8,7 +8,6 @@
8 * Copyright (C) 1995 Linus Torvalds 8 * Copyright (C) 1995 Linus Torvalds
9 */ 9 */
10 10
11#include <linux/config.h>
12#include <linux/signal.h> 11#include <linux/signal.h>
13#include <linux/sched.h> 12#include <linux/sched.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -148,7 +147,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
148 /* When running in the kernel we expect faults to occur only to 147 /* When running in the kernel we expect faults to occur only to
149 * addresses in user space. All other faults represent errors in the 148 * addresses in user space. All other faults represent errors in the
150 * kernel and should generate an OOPS. Unfortunatly, in the case of an 149 * kernel and should generate an OOPS. Unfortunatly, in the case of an
151 * erroneous fault occuring in a code path which already holds mmap_sem 150 * erroneous fault occurring in a code path which already holds mmap_sem
152 * we will deadlock attempting to validate the fault against the 151 * we will deadlock attempting to validate the fault against the
153 * address space. Luckily the kernel only validly references user 152 * address space. Luckily the kernel only validly references user
154 * space from well defined areas of code, which are listed in the 153 * space from well defined areas of code, which are listed in the
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 05:26:10 -0500