diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-21 17:37:27 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-10-21 17:37:27 -0400 |
commit | e36f561a2c88394ef2708f1ab300fe8a79e9f651 (patch) | |
tree | 385f378c4240955e4356d49686a8ef606a82a7c1 /arch/m32r | |
parent | 70ada77920723fbc2b35e9b301022fb1e166b41b (diff) | |
parent | df9ee29270c11dba7d0fe0b83ce47a4d8e8d2101 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags
* git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-irqflags:
Fix IRQ flag handling naming
MIPS: Add missing #inclusions of <linux/irq.h>
smc91x: Add missing #inclusion of <linux/irq.h>
Drop a couple of unnecessary asm/system.h inclusions
SH: Add missing consts to sys_execve() declaration
Blackfin: Rename IRQ flags handling functions
Blackfin: Add missing dep to asm/irqflags.h
Blackfin: Rename DES PC2() symbol to avoid collision
Blackfin: Split the BF532 BFIN_*_FIO_FLAG() functions to their own header
Blackfin: Split PLL code from mach-specific cdef headers
Diffstat (limited to 'arch/m32r')
-rw-r--r-- | arch/m32r/include/asm/irqflags.h | 104 | ||||
-rw-r--r-- | arch/m32r/include/asm/system.h | 66 |
2 files changed, 105 insertions, 65 deletions
diff --git a/arch/m32r/include/asm/irqflags.h b/arch/m32r/include/asm/irqflags.h new file mode 100644 index 000000000000..1f92d29982ae --- /dev/null +++ b/arch/m32r/include/asm/irqflags.h | |||
@@ -0,0 +1,104 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto | ||
7 | * Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org> | ||
8 | */ | ||
9 | |||
10 | #ifndef _ASM_M32R_IRQFLAGS_H | ||
11 | #define _ASM_M32R_IRQFLAGS_H | ||
12 | |||
13 | #include <linux/types.h> | ||
14 | |||
15 | static inline unsigned long arch_local_save_flags(void) | ||
16 | { | ||
17 | unsigned long flags; | ||
18 | asm volatile("mvfc %0,psw" : "=r"(flags)); | ||
19 | return flags; | ||
20 | } | ||
21 | |||
22 | static inline void arch_local_irq_disable(void) | ||
23 | { | ||
24 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) | ||
25 | asm volatile ( | ||
26 | "clrpsw #0x40 -> nop" | ||
27 | : : : "memory"); | ||
28 | #else | ||
29 | unsigned long tmpreg0, tmpreg1; | ||
30 | asm volatile ( | ||
31 | "ld24 %0, #0 ; Use 32-bit insn. \n\t" | ||
32 | "mvfc %1, psw ; No interrupt can be accepted here. \n\t" | ||
33 | "mvtc %0, psw \n\t" | ||
34 | "and3 %0, %1, #0xffbf \n\t" | ||
35 | "mvtc %0, psw \n\t" | ||
36 | : "=&r" (tmpreg0), "=&r" (tmpreg1) | ||
37 | : | ||
38 | : "cbit", "memory"); | ||
39 | #endif | ||
40 | } | ||
41 | |||
42 | static inline void arch_local_irq_enable(void) | ||
43 | { | ||
44 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) | ||
45 | asm volatile ( | ||
46 | "setpsw #0x40 -> nop" | ||
47 | : : : "memory"); | ||
48 | #else | ||
49 | unsigned long tmpreg; | ||
50 | asm volatile ( | ||
51 | "mvfc %0, psw; \n\t" | ||
52 | "or3 %0, %0, #0x0040; \n\t" | ||
53 | "mvtc %0, psw; \n\t" | ||
54 | : "=&r" (tmpreg) | ||
55 | : | ||
56 | : "cbit", "memory"); | ||
57 | #endif | ||
58 | } | ||
59 | |||
60 | static inline unsigned long arch_local_irq_save(void) | ||
61 | { | ||
62 | unsigned long flags; | ||
63 | |||
64 | #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) | ||
65 | asm volatile ( | ||
66 | "mvfc %0, psw; \n\t" | ||
67 | "clrpsw #0x40 -> nop; \n\t" | ||
68 | : "=r" (flags) | ||
69 | : | ||
70 | : "memory"); | ||
71 | #else | ||
72 | unsigned long tmpreg; | ||
73 | asm volatile ( | ||
74 | "ld24 %1, #0 \n\t" | ||
75 | "mvfc %0, psw \n\t" | ||
76 | "mvtc %1, psw \n\t" | ||
77 | "and3 %1, %0, #0xffbf \n\t" | ||
78 | "mvtc %1, psw \n\t" | ||
79 | : "=r" (flags), "=&r" (tmpreg) | ||
80 | : | ||
81 | : "cbit", "memory"); | ||
82 | #endif | ||
83 | return flags; | ||
84 | } | ||
85 | |||
86 | static inline void arch_local_irq_restore(unsigned long flags) | ||
87 | { | ||
88 | asm volatile("mvtc %0,psw" | ||
89 | : | ||
90 | : "r" (flags) | ||
91 | : "cbit", "memory"); | ||
92 | } | ||
93 | |||
94 | static inline bool arch_irqs_disabled_flags(unsigned long flags) | ||
95 | { | ||
96 | return !(flags & 0x40); | ||
97 | } | ||
98 | |||
99 | static inline bool arch_irqs_disabled(void) | ||
100 | { | ||
101 | return arch_irqs_disabled_flags(arch_local_save_flags()); | ||
102 | } | ||
103 | |||
104 | #endif /* _ASM_M32R_IRQFLAGS_H */ | ||
diff --git a/arch/m32r/include/asm/system.h b/arch/m32r/include/asm/system.h index c980f5ba8de7..13c46794ccb1 100644 --- a/arch/m32r/include/asm/system.h +++ b/arch/m32r/include/asm/system.h | |||
@@ -11,6 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/compiler.h> | 13 | #include <linux/compiler.h> |
14 | #include <linux/irqflags.h> | ||
14 | #include <asm/assembler.h> | 15 | #include <asm/assembler.h> |
15 | 16 | ||
16 | #ifdef __KERNEL__ | 17 | #ifdef __KERNEL__ |
@@ -54,71 +55,6 @@ | |||
54 | ); \ | 55 | ); \ |
55 | } while(0) | 56 | } while(0) |
56 | 57 | ||
57 | /* Interrupt Control */ | ||
58 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) | ||
59 | #define local_irq_enable() \ | ||
60 | __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") | ||
61 | #define local_irq_disable() \ | ||
62 | __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") | ||
63 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | ||
64 | static inline void local_irq_enable(void) | ||
65 | { | ||
66 | unsigned long tmpreg; | ||
67 | __asm__ __volatile__( | ||
68 | "mvfc %0, psw; \n\t" | ||
69 | "or3 %0, %0, #0x0040; \n\t" | ||
70 | "mvtc %0, psw; \n\t" | ||
71 | : "=&r" (tmpreg) : : "cbit", "memory"); | ||
72 | } | ||
73 | |||
74 | static inline void local_irq_disable(void) | ||
75 | { | ||
76 | unsigned long tmpreg0, tmpreg1; | ||
77 | __asm__ __volatile__( | ||
78 | "ld24 %0, #0 ; Use 32-bit insn. \n\t" | ||
79 | "mvfc %1, psw ; No interrupt can be accepted here. \n\t" | ||
80 | "mvtc %0, psw \n\t" | ||
81 | "and3 %0, %1, #0xffbf \n\t" | ||
82 | "mvtc %0, psw \n\t" | ||
83 | : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); | ||
84 | } | ||
85 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | ||
86 | |||
87 | #define local_save_flags(x) \ | ||
88 | __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) | ||
89 | |||
90 | #define local_irq_restore(x) \ | ||
91 | __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ | ||
92 | : "r" (x) : "cbit", "memory") | ||
93 | |||
94 | #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) | ||
95 | #define local_irq_save(x) \ | ||
96 | __asm__ __volatile__( \ | ||
97 | "mvfc %0, psw; \n\t" \ | ||
98 | "clrpsw #0x40 -> nop; \n\t" \ | ||
99 | : "=r" (x) : /* no input */ : "memory") | ||
100 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | ||
101 | #define local_irq_save(x) \ | ||
102 | ({ \ | ||
103 | unsigned long tmpreg; \ | ||
104 | __asm__ __volatile__( \ | ||
105 | "ld24 %1, #0 \n\t" \ | ||
106 | "mvfc %0, psw \n\t" \ | ||
107 | "mvtc %1, psw \n\t" \ | ||
108 | "and3 %1, %0, #0xffbf \n\t" \ | ||
109 | "mvtc %1, psw \n\t" \ | ||
110 | : "=r" (x), "=&r" (tmpreg) \ | ||
111 | : : "cbit", "memory"); \ | ||
112 | }) | ||
113 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | ||
114 | |||
115 | #define irqs_disabled() \ | ||
116 | ({ \ | ||
117 | unsigned long flags; \ | ||
118 | local_save_flags(flags); \ | ||
119 | !(flags & 0x40); \ | ||
120 | }) | ||
121 | |||
122 | #define nop() __asm__ __volatile__ ("nop" : : ) | 58 | #define nop() __asm__ __volatile__ ("nop" : : ) |
123 | 59 | ||
124 | #define xchg(ptr, x) \ | 60 | #define xchg(ptr, x) \ |