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authorThomas Gleixner <tglx@linutronix.de>2011-01-19 12:44:10 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-01-21 05:55:28 -0500
commitce1104ce67ea186bf5c23de66a2eeaf65823e1ce (patch)
tree18155f12ec909572e8d3093a9125b6c9199b424c /arch/m32r
parentb82727ec646578bdd3a6f31f6451f67784874675 (diff)
m32r: Convert oaks32r irq chips
Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r')
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c47
1 files changed, 22 insertions, 25 deletions
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index 43bf5a0c9515..19a02db7b818 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_oaks32r(struct irq_data *data)
41{ 41{
42 disable_oaks32r_irq(irq); 42 disable_oaks32r_irq(data->irq);
43} 43}
44 44
45static void end_oaks32r_irq(unsigned int irq) 45static void unmask_oaks32r(struct irq_data *data)
46{ 46{
47 enable_oaks32r_irq(irq); 47 enable_oaks32r_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_oaks32r_irq(unsigned int irq) 50static void shutdown_oaks32r(struct irq_data *data)
51{
52 enable_oaks32r_irq(irq);
53 return (0);
54}
55
56static void shutdown_oaks32r_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip oaks32r_irq_type = 58static struct irq_chip oaks32r_irq_type =
65{ 59{
66 .name = "OAKS32R-IRQ", 60 .name = "OAKS32R-IRQ",
67 .startup = startup_oaks32r_irq, 61 .irq_shutdown = shutdown_oaks32r,
68 .shutdown = shutdown_oaks32r_irq, 62 .irq_mask = mask_oaks32r,
69 .enable = enable_oaks32r_irq, 63 .irq_unmask = unmask_oaks32r,
70 .disable = disable_oaks32r_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_oaks32r_irq
73}; 64};
74 65
75void __init init_IRQ(void) 66void __init init_IRQ(void)
@@ -83,34 +74,40 @@ void __init init_IRQ(void)
83 74
84#ifdef CONFIG_NE2000 75#ifdef CONFIG_NE2000
85 /* INT3 : LAN controller (RTL8019AS) */ 76 /* INT3 : LAN controller (RTL8019AS) */
86 set_irq_chip(M32R_IRQ_INT3, &oaks32r_irq_type); 77 set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
78 handle_level_irq);
87 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
88 disable_oaks32r_irq(M32R_IRQ_INT3); 80 disable_oaks32r_irq(M32R_IRQ_INT3);
89#endif /* CONFIG_M32R_NE2000 */ 81#endif /* CONFIG_M32R_NE2000 */
90 82
91 /* MFT2 : system timer */ 83 /* MFT2 : system timer */
92 set_irq_chip(M32R_IRQ_MFT2, &oaks32r_irq_type); 84 set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
85 handle_level_irq);
93 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
94 disable_oaks32r_irq(M32R_IRQ_MFT2); 87 disable_oaks32r_irq(M32R_IRQ_MFT2);
95 88
96#ifdef CONFIG_SERIAL_M32R_SIO 89#ifdef CONFIG_SERIAL_M32R_SIO
97 /* SIO0_R : uart receive data */ 90 /* SIO0_R : uart receive data */
98 set_irq_chip(M32R_IRQ_SIO0_R, &oaks32r_irq_type); 91 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
92 handle_level_irq);
99 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
100 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R);
101 95
102 /* SIO0_S : uart send data */ 96 /* SIO0_S : uart send data */
103 set_irq_chip(M32R_IRQ_SIO0_S, &oaks32r_irq_type); 97 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
98 handle_level_irq);
104 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
105 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S);
106 101
107 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
108 set_irq_chip(M32R_IRQ_SIO1_R, &oaks32r_irq_type); 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
104 handle_level_irq);
109 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
110 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R);
111 107
112 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
113 set_irq_chip(M32R_IRQ_SIO1_S, &oaks32r_irq_type); 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
110 handle_level_irq);
114 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
115 disable_oaks32r_irq(M32R_IRQ_SIO1_S); 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
116#endif /* CONFIG_SERIAL_M32R_SIO */ 113#endif /* CONFIG_SERIAL_M32R_SIO */