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authorThomas Gleixner <tglx@linutronix.de>2011-01-19 12:55:09 -0500
committerThomas Gleixner <tglx@linutronix.de>2011-01-21 05:55:29 -0500
commit22cbc9384a495f2e6eb0d0fda91692431a28468e (patch)
treea8a4d692ae9d58799e6b01068f7b0a77486e3268 /arch/m32r/platforms
parent883c0ccde1e12e7721966626983d61ccdbd0ae99 (diff)
m32r: Convert opsput pld irq chip
Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r/platforms')
-rw-r--r--arch/m32r/platforms/opsput/setup.c46
1 files changed, 20 insertions, 26 deletions
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index 8c0907dd771b..00eb3b82bd95 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -107,44 +107,33 @@ static void enable_opsput_pld_irq(unsigned int irq)
107 outw(data, port); 107 outw(data, port);
108} 108}
109 109
110static void mask_and_ack_opsput_pld(unsigned int irq) 110static void mask_opsput_pld(struct irq_data *data)
111{ 111{
112 disable_opsput_pld_irq(irq); 112 disable_opsput_pld_irq(data->irq);
113// mask_and_ack_opsput(M32R_IRQ_INT1);
114} 113}
115 114
116static void end_opsput_pld_irq(unsigned int irq) 115static void unmask_opsput_pld(struct irq_data *data)
117{ 116{
118 enable_opsput_pld_irq(irq); 117 enable_opsput_pld_irq(data->irq);
119 enable_opsput_irq(M32R_IRQ_INT1); 118 enable_opsput_irq(M32R_IRQ_INT1);
120} 119}
121 120
122static unsigned int startup_opsput_pld_irq(unsigned int irq) 121static void shutdown_opsput_pld(struct irq_data *data)
123{
124 enable_opsput_pld_irq(irq);
125 return (0);
126}
127
128static void shutdown_opsput_pld_irq(unsigned int irq)
129{ 122{
130 unsigned long port; 123 unsigned long port;
131 unsigned int pldirq; 124 unsigned int pldirq;
132 125
133 pldirq = irq2pldirq(irq); 126 pldirq = irq2pldirq(data->irq);
134// shutdown_opsput_irq(M32R_IRQ_INT1);
135 port = pldirq2port(pldirq); 127 port = pldirq2port(pldirq);
136 outw(PLD_ICUCR_ILEVEL7, port); 128 outw(PLD_ICUCR_ILEVEL7, port);
137} 129}
138 130
139static struct irq_chip opsput_pld_irq_type = 131static struct irq_chip opsput_pld_irq_type =
140{ 132{
141 .name = "OPSPUT-PLD-IRQ", 133 .name = "OPSPUT-PLD-IRQ",
142 .startup = startup_opsput_pld_irq, 134 .irq_shutdown = shutdown_opsput_pld,
143 .shutdown = shutdown_opsput_pld_irq, 135 .irq_mask = mask_opsput_pld,
144 .enable = enable_opsput_pld_irq, 136 .irq_unmask = unmask_opsput_pld,
145 .disable = disable_opsput_pld_irq,
146 .ack = mask_and_ack_opsput_pld,
147 .end = end_opsput_pld_irq
148}; 137};
149 138
150/* 139/*
@@ -332,28 +321,33 @@ void __init init_IRQ(void)
332 321
333#ifdef CONFIG_SERIAL_M32R_PLDSIO 322#ifdef CONFIG_SERIAL_M32R_PLDSIO
334 /* INT#1: SIO0 Receive on PLD */ 323 /* INT#1: SIO0 Receive on PLD */
335 set_irq_chip(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type); 324 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
325 handle_level_irq);
336 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 326 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
337 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 327 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
338 328
339 /* INT#1: SIO0 Send on PLD */ 329 /* INT#1: SIO0 Send on PLD */
340 set_irq_chip(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type); 330 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
331 handle_level_irq);
341 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 332 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
342 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 333 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
343#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 334#endif /* CONFIG_SERIAL_M32R_PLDSIO */
344 335
345 /* INT#1: CFC IREQ on PLD */ 336 /* INT#1: CFC IREQ on PLD */
346 set_irq_chip(PLD_IRQ_CFIREQ, &opsput_pld_irq_type); 337 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
338 handle_level_irq);
347 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 339 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
348 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 340 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
349 341
350 /* INT#1: CFC Insert on PLD */ 342 /* INT#1: CFC Insert on PLD */
351 set_irq_chip(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type); 343 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
344 handle_level_irq);
352 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 345 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
353 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 346 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
354 347
355 /* INT#1: CFC Eject on PLD */ 348 /* INT#1: CFC Eject on PLD */
356 set_irq_chip(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type); 349 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
350 handle_level_irq);
357 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 351 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
358 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); 352 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
359 353