diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-01-19 12:27:59 -0500 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-01-21 05:55:27 -0500 |
commit | 1f12681ab1419a68da0f066b95e3e6e9270eb730 (patch) | |
tree | fa5760eacaff180a905247dc7d9fa77683dac170 /arch/m32r/platforms | |
parent | 37808e47eab064006eb17d46cf15a098655940c4 (diff) |
m32r: Convert mappi irq chips
Convert the irq chips to the new functions and use proper flow
handlers. handle_level_irq is appropriate.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r/platforms')
-rw-r--r-- | arch/m32r/platforms/mappi/setup.c | 53 |
1 files changed, 26 insertions, 27 deletions
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c index bc3fdaf21ca2..cdd8c4574027 100644 --- a/arch/m32r/platforms/mappi/setup.c +++ b/arch/m32r/platforms/mappi/setup.c | |||
@@ -38,39 +38,30 @@ static void enable_mappi_irq(unsigned int irq) | |||
38 | outl(data, port); | 38 | outl(data, port); |
39 | } | 39 | } |
40 | 40 | ||
41 | static void mask_and_ack_mappi(unsigned int irq) | 41 | static void mask_mappi(struct irq_data *data) |
42 | { | 42 | { |
43 | disable_mappi_irq(irq); | 43 | disable_mappi_irq(data->irq); |
44 | } | 44 | } |
45 | 45 | ||
46 | static void end_mappi_irq(unsigned int irq) | 46 | static void unmask_mappi(struct irq_data *data) |
47 | { | 47 | { |
48 | enable_mappi_irq(irq); | 48 | enable_mappi_irq(data->irq); |
49 | } | 49 | } |
50 | 50 | ||
51 | static unsigned int startup_mappi_irq(unsigned int irq) | 51 | static void shutdown_mappi(struct irq_data *data) |
52 | { | ||
53 | enable_mappi_irq(irq); | ||
54 | return (0); | ||
55 | } | ||
56 | |||
57 | static void shutdown_mappi_irq(unsigned int irq) | ||
58 | { | 52 | { |
59 | unsigned long port; | 53 | unsigned long port; |
60 | 54 | ||
61 | port = irq2port(irq); | 55 | port = irq2port(data->irq); |
62 | outl(M32R_ICUCR_ILEVEL7, port); | 56 | outl(M32R_ICUCR_ILEVEL7, port); |
63 | } | 57 | } |
64 | 58 | ||
65 | static struct irq_chip mappi_irq_type = | 59 | static struct irq_chip mappi_irq_type = |
66 | { | 60 | { |
67 | .name = "MAPPI-IRQ", | 61 | .name = "MAPPI-IRQ", |
68 | .startup = startup_mappi_irq, | 62 | .irq_shutdown = shutdown_mappi, |
69 | .shutdown = shutdown_mappi_irq, | 63 | .irq_mask = mask_mappi, |
70 | .enable = enable_mappi_irq, | 64 | .irq_unmask = unmask_mappi, |
71 | .disable = disable_mappi_irq, | ||
72 | .ack = mask_and_ack_mappi, | ||
73 | .end = end_mappi_irq | ||
74 | }; | 65 | }; |
75 | 66 | ||
76 | void __init init_IRQ(void) | 67 | void __init init_IRQ(void) |
@@ -84,46 +75,54 @@ void __init init_IRQ(void) | |||
84 | 75 | ||
85 | #ifdef CONFIG_NE2000 | 76 | #ifdef CONFIG_NE2000 |
86 | /* INT0 : LAN controller (RTL8019AS) */ | 77 | /* INT0 : LAN controller (RTL8019AS) */ |
87 | set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type); | 78 | set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, |
79 | handle_level_irq); | ||
88 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; | 80 | icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; |
89 | disable_mappi_irq(M32R_IRQ_INT0); | 81 | disable_mappi_irq(M32R_IRQ_INT0); |
90 | #endif /* CONFIG_M32R_NE2000 */ | 82 | #endif /* CONFIG_M32R_NE2000 */ |
91 | 83 | ||
92 | /* MFT2 : system timer */ | 84 | /* MFT2 : system timer */ |
93 | set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); | 85 | set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, |
86 | handle_level_irq); | ||
94 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 87 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
95 | disable_mappi_irq(M32R_IRQ_MFT2); | 88 | disable_mappi_irq(M32R_IRQ_MFT2); |
96 | 89 | ||
97 | #ifdef CONFIG_SERIAL_M32R_SIO | 90 | #ifdef CONFIG_SERIAL_M32R_SIO |
98 | /* SIO0_R : uart receive data */ | 91 | /* SIO0_R : uart receive data */ |
99 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); | 92 | set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, |
93 | handle_level_irq); | ||
100 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 94 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
101 | disable_mappi_irq(M32R_IRQ_SIO0_R); | 95 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
102 | 96 | ||
103 | /* SIO0_S : uart send data */ | 97 | /* SIO0_S : uart send data */ |
104 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); | 98 | set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, |
99 | handle_level_irq); | ||
105 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 100 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
106 | disable_mappi_irq(M32R_IRQ_SIO0_S); | 101 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
107 | 102 | ||
108 | /* SIO1_R : uart receive data */ | 103 | /* SIO1_R : uart receive data */ |
109 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); | 104 | set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, |
105 | handle_level_irq); | ||
110 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 106 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
111 | disable_mappi_irq(M32R_IRQ_SIO1_R); | 107 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
112 | 108 | ||
113 | /* SIO1_S : uart send data */ | 109 | /* SIO1_S : uart send data */ |
114 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); | 110 | set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, |
111 | handle_level_irq); | ||
115 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 112 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
116 | disable_mappi_irq(M32R_IRQ_SIO1_S); | 113 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
117 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 114 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
118 | 115 | ||
119 | #if defined(CONFIG_M32R_PCC) | 116 | #if defined(CONFIG_M32R_PCC) |
120 | /* INT1 : pccard0 interrupt */ | 117 | /* INT1 : pccard0 interrupt */ |
121 | set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type); | 118 | set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, |
119 | handle_level_irq); | ||
122 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 120 | icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
123 | disable_mappi_irq(M32R_IRQ_INT1); | 121 | disable_mappi_irq(M32R_IRQ_INT1); |
124 | 122 | ||
125 | /* INT2 : pccard1 interrupt */ | 123 | /* INT2 : pccard1 interrupt */ |
126 | set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type); | 124 | set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, |
125 | handle_level_irq); | ||
127 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; | 126 | icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; |
128 | disable_mappi_irq(M32R_IRQ_INT2); | 127 | disable_mappi_irq(M32R_IRQ_INT2); |
129 | #endif /* CONFIG_M32RPCC */ | 128 | #endif /* CONFIG_M32RPCC */ |