diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2010-09-22 13:13:16 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2011-01-21 05:55:26 -0500 |
commit | 863018a7a24a29c0862c62e70c89244fdd5a08bf (patch) | |
tree | 951f3e7bc9a6829183f322c34deb0e250e52a2d9 /arch/m32r/platforms/usrv | |
parent | 30139785e615c97497864a89511db02839fa7bf5 (diff) |
m32r: Cleanup direct irq_desc access
The irq descriptors are already initialized by the generic
code. Remove the redundant init code and set the irq chip with the
proper accessor function.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r/platforms/usrv')
-rw-r--r-- | arch/m32r/platforms/usrv/setup.c | 45 |
1 files changed, 9 insertions, 36 deletions
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c index 1beac7a51ed4..d6eb586a099e 100644 --- a/arch/m32r/platforms/usrv/setup.c +++ b/arch/m32r/platforms/usrv/setup.c | |||
@@ -156,53 +156,35 @@ void __init init_IRQ(void) | |||
156 | once++; | 156 | once++; |
157 | 157 | ||
158 | /* MFT2 : system timer */ | 158 | /* MFT2 : system timer */ |
159 | irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; | 159 | set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type); |
160 | irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; | ||
161 | irq_desc[M32R_IRQ_MFT2].action = 0; | ||
162 | irq_desc[M32R_IRQ_MFT2].depth = 1; | ||
163 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; | 160 | icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; |
164 | disable_mappi_irq(M32R_IRQ_MFT2); | 161 | disable_mappi_irq(M32R_IRQ_MFT2); |
165 | 162 | ||
166 | #if defined(CONFIG_SERIAL_M32R_SIO) | 163 | #if defined(CONFIG_SERIAL_M32R_SIO) |
167 | /* SIO0_R : uart receive data */ | 164 | /* SIO0_R : uart receive data */ |
168 | irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; | 165 | set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type); |
169 | irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; | ||
170 | irq_desc[M32R_IRQ_SIO0_R].action = 0; | ||
171 | irq_desc[M32R_IRQ_SIO0_R].depth = 1; | ||
172 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; | 166 | icu_data[M32R_IRQ_SIO0_R].icucr = 0; |
173 | disable_mappi_irq(M32R_IRQ_SIO0_R); | 167 | disable_mappi_irq(M32R_IRQ_SIO0_R); |
174 | 168 | ||
175 | /* SIO0_S : uart send data */ | 169 | /* SIO0_S : uart send data */ |
176 | irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; | 170 | set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type); |
177 | irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; | ||
178 | irq_desc[M32R_IRQ_SIO0_S].action = 0; | ||
179 | irq_desc[M32R_IRQ_SIO0_S].depth = 1; | ||
180 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; | 171 | icu_data[M32R_IRQ_SIO0_S].icucr = 0; |
181 | disable_mappi_irq(M32R_IRQ_SIO0_S); | 172 | disable_mappi_irq(M32R_IRQ_SIO0_S); |
182 | 173 | ||
183 | /* SIO1_R : uart receive data */ | 174 | /* SIO1_R : uart receive data */ |
184 | irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; | 175 | set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type); |
185 | irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; | ||
186 | irq_desc[M32R_IRQ_SIO1_R].action = 0; | ||
187 | irq_desc[M32R_IRQ_SIO1_R].depth = 1; | ||
188 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; | 176 | icu_data[M32R_IRQ_SIO1_R].icucr = 0; |
189 | disable_mappi_irq(M32R_IRQ_SIO1_R); | 177 | disable_mappi_irq(M32R_IRQ_SIO1_R); |
190 | 178 | ||
191 | /* SIO1_S : uart send data */ | 179 | /* SIO1_S : uart send data */ |
192 | irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; | 180 | set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type); |
193 | irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; | ||
194 | irq_desc[M32R_IRQ_SIO1_S].action = 0; | ||
195 | irq_desc[M32R_IRQ_SIO1_S].depth = 1; | ||
196 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; | 181 | icu_data[M32R_IRQ_SIO1_S].icucr = 0; |
197 | disable_mappi_irq(M32R_IRQ_SIO1_S); | 182 | disable_mappi_irq(M32R_IRQ_SIO1_S); |
198 | #endif /* CONFIG_SERIAL_M32R_SIO */ | 183 | #endif /* CONFIG_SERIAL_M32R_SIO */ |
199 | 184 | ||
200 | /* INT#67-#71: CFC#0 IREQ on PLD */ | 185 | /* INT#67-#71: CFC#0 IREQ on PLD */ |
201 | for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { | 186 | for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { |
202 | irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; | 187 | set_irq_chip(PLD_IRQ_CF0 + i, &m32700ut_pld_irq_type); |
203 | irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; | ||
204 | irq_desc[PLD_IRQ_CF0 + i].action = 0; | ||
205 | irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */ | ||
206 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr | 188 | pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr |
207 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 189 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
208 | disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); | 190 | disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); |
@@ -210,19 +192,13 @@ void __init init_IRQ(void) | |||
210 | 192 | ||
211 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | 193 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) |
212 | /* INT#76: 16552D#0 IREQ on PLD */ | 194 | /* INT#76: 16552D#0 IREQ on PLD */ |
213 | irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; | 195 | set_irq_chip(PLD_IRQ_UART0, &m32700ut_pld_irq_type); |
214 | irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; | ||
215 | irq_desc[PLD_IRQ_UART0].action = 0; | ||
216 | irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */ | ||
217 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr | 196 | pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr |
218 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ | 197 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
219 | disable_m32700ut_pld_irq(PLD_IRQ_UART0); | 198 | disable_m32700ut_pld_irq(PLD_IRQ_UART0); |
220 | 199 | ||
221 | /* INT#77: 16552D#1 IREQ on PLD */ | 200 | /* INT#77: 16552D#1 IREQ on PLD */ |
222 | irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; | 201 | set_irq_chip(PLD_IRQ_UART1, &m32700ut_pld_irq_type); |
223 | irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; | ||
224 | irq_desc[PLD_IRQ_UART1].action = 0; | ||
225 | irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */ | ||
226 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr | 202 | pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr |
227 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ | 203 | = PLD_ICUCR_ISMOD03; /* 'H' level sense */ |
228 | disable_m32700ut_pld_irq(PLD_IRQ_UART1); | 204 | disable_m32700ut_pld_irq(PLD_IRQ_UART1); |
@@ -230,10 +206,7 @@ void __init init_IRQ(void) | |||
230 | 206 | ||
231 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) | 207 | #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) |
232 | /* INT#80: AK4524 IREQ on PLD */ | 208 | /* INT#80: AK4524 IREQ on PLD */ |
233 | irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; | 209 | set_irq_chip(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type); |
234 | irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; | ||
235 | irq_desc[PLD_IRQ_SNDINT].action = 0; | ||
236 | irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */ | ||
237 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr | 210 | pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr |
238 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ | 211 | = PLD_ICUCR_ISMOD01; /* 'L' level sense */ |
239 | disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); | 212 | disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); |