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authorHirokazu Takata <takata@linux-m32r.org>2007-08-01 08:09:31 -0400
committerHirokazu Takata <takata@linux-m32r.org>2007-09-02 22:30:18 -0400
commit3264f976d3188bea80819793c13a3220b8a4867c (patch)
treee451b9179430ddbbe1102050ebf391433248c1e1 /arch/m32r/platforms/opsput
parente6a7ba7efddbb393b726453eae8601ef02b9a610 (diff)
m32r: Rearrange platform-dependent codes
Rearrange platform-dependent codes from arch/m32r/kernel/*.c to arch/m32r/platforms/{platform}/. Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Diffstat (limited to 'arch/m32r/platforms/opsput')
-rw-r--r--arch/m32r/platforms/opsput/Makefile1
-rw-r--r--arch/m32r/platforms/opsput/io.c395
-rw-r--r--arch/m32r/platforms/opsput/setup.c519
3 files changed, 915 insertions, 0 deletions
diff --git a/arch/m32r/platforms/opsput/Makefile b/arch/m32r/platforms/opsput/Makefile
new file mode 100644
index 000000000000..0de59084f21c
--- /dev/null
+++ b/arch/m32r/platforms/opsput/Makefile
@@ -0,0 +1 @@
obj-y := setup.o io.o
diff --git a/arch/m32r/platforms/opsput/io.c b/arch/m32r/platforms/opsput/io.c
new file mode 100644
index 000000000000..379efb77123d
--- /dev/null
+++ b/arch/m32r/platforms/opsput/io.c
@@ -0,0 +1,395 @@
1/*
2 * linux/arch/m32r/platforms/opsput/io.c
3 *
4 * Typical I/O routines for OPSPUT board.
5 *
6 * Copyright (c) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto, Takeo Takahashi
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 */
13
14#include <asm/m32r.h>
15#include <asm/page.h>
16#include <asm/io.h>
17#include <asm/byteorder.h>
18
19#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
20#include <linux/types.h>
21
22#define M32R_PCC_IOMAP_SIZE 0x1000
23
24#define M32R_PCC_IOSTART0 0x1000
25#define M32R_PCC_IOEND0 (M32R_PCC_IOSTART0 + M32R_PCC_IOMAP_SIZE - 1)
26
27extern void pcc_ioread_byte(int, unsigned long, void *, size_t, size_t, int);
28extern void pcc_ioread_word(int, unsigned long, void *, size_t, size_t, int);
29extern void pcc_iowrite_byte(int, unsigned long, void *, size_t, size_t, int);
30extern void pcc_iowrite_word(int, unsigned long, void *, size_t, size_t, int);
31#endif /* CONFIG_PCMCIA && CONFIG_M32R_CFC */
32
33#define PORT2ADDR(port) _port2addr(port)
34#define PORT2ADDR_USB(port) _port2addr_usb(port)
35
36static inline void *_port2addr(unsigned long port)
37{
38 return (void *)(port | NONCACHE_OFFSET);
39}
40
41#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
42static inline void *__port2addr_ata(unsigned long port)
43{
44 static int dummy_reg;
45
46 switch (port) {
47 case 0x1f0: return (void *)(0x0c002000 | NONCACHE_OFFSET);
48 case 0x1f1: return (void *)(0x0c012800 | NONCACHE_OFFSET);
49 case 0x1f2: return (void *)(0x0c012002 | NONCACHE_OFFSET);
50 case 0x1f3: return (void *)(0x0c012802 | NONCACHE_OFFSET);
51 case 0x1f4: return (void *)(0x0c012004 | NONCACHE_OFFSET);
52 case 0x1f5: return (void *)(0x0c012804 | NONCACHE_OFFSET);
53 case 0x1f6: return (void *)(0x0c012006 | NONCACHE_OFFSET);
54 case 0x1f7: return (void *)(0x0c012806 | NONCACHE_OFFSET);
55 case 0x3f6: return (void *)(0x0c01200e | NONCACHE_OFFSET);
56 default: return (void *)&dummy_reg;
57 }
58}
59#endif
60
61/*
62 * OPSPUT-LAN is located in the extended bus space
63 * from 0x10000000 to 0x13ffffff on physical address.
64 * The base address of LAN controller(LAN91C111) is 0x300.
65 */
66#define LAN_IOSTART (0x300 | NONCACHE_OFFSET)
67#define LAN_IOEND (0x320 | NONCACHE_OFFSET)
68static inline void *_port2addr_ne(unsigned long port)
69{
70 return (void *)(port + 0x10000000);
71}
72static inline void *_port2addr_usb(unsigned long port)
73{
74 return (void *)((port & 0x0f) + NONCACHE_OFFSET + 0x10303000);
75}
76
77static inline void delay(void)
78{
79 __asm__ __volatile__ ("push r0; \n\t pop r0;" : : :"memory");
80}
81
82/*
83 * NIC I/O function
84 */
85
86#define PORT2ADDR_NE(port) _port2addr_ne(port)
87
88static inline unsigned char _ne_inb(void *portp)
89{
90 return *(volatile unsigned char *)portp;
91}
92
93static inline unsigned short _ne_inw(void *portp)
94{
95 return (unsigned short)le16_to_cpu(*(volatile unsigned short *)portp);
96}
97
98static inline void _ne_insb(void *portp, void *addr, unsigned long count)
99{
100 unsigned char *buf = (unsigned char *)addr;
101
102 while (count--)
103 *buf++ = _ne_inb(portp);
104}
105
106static inline void _ne_outb(unsigned char b, void *portp)
107{
108 *(volatile unsigned char *)portp = b;
109}
110
111static inline void _ne_outw(unsigned short w, void *portp)
112{
113 *(volatile unsigned short *)portp = cpu_to_le16(w);
114}
115
116unsigned char _inb(unsigned long port)
117{
118 if (port >= LAN_IOSTART && port < LAN_IOEND)
119 return _ne_inb(PORT2ADDR_NE(port));
120
121#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
122 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
123 return *(volatile unsigned char *)__port2addr_ata(port);
124 }
125#endif
126#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
127 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
128 unsigned char b;
129 pcc_ioread_byte(0, port, &b, sizeof(b), 1, 0);
130 return b;
131 } else
132#endif
133
134 return *(volatile unsigned char *)PORT2ADDR(port);
135}
136
137unsigned short _inw(unsigned long port)
138{
139 if (port >= LAN_IOSTART && port < LAN_IOEND)
140 return _ne_inw(PORT2ADDR_NE(port));
141#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
142 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
143 return *(volatile unsigned short *)__port2addr_ata(port);
144 }
145#endif
146#if defined(CONFIG_USB)
147 else if(port >= 0x340 && port < 0x3a0)
148 return *(volatile unsigned short *)PORT2ADDR_USB(port);
149#endif
150#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
151 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
152 unsigned short w;
153 pcc_ioread_word(0, port, &w, sizeof(w), 1, 0);
154 return w;
155 } else
156#endif
157 return *(volatile unsigned short *)PORT2ADDR(port);
158}
159
160unsigned long _inl(unsigned long port)
161{
162#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
163 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
164 unsigned long l;
165 pcc_ioread_word(0, port, &l, sizeof(l), 1, 0);
166 return l;
167 } else
168#endif
169 return *(volatile unsigned long *)PORT2ADDR(port);
170}
171
172unsigned char _inb_p(unsigned long port)
173{
174 unsigned char v = _inb(port);
175 delay();
176 return (v);
177}
178
179unsigned short _inw_p(unsigned long port)
180{
181 unsigned short v = _inw(port);
182 delay();
183 return (v);
184}
185
186unsigned long _inl_p(unsigned long port)
187{
188 unsigned long v = _inl(port);
189 delay();
190 return (v);
191}
192
193void _outb(unsigned char b, unsigned long port)
194{
195 if (port >= LAN_IOSTART && port < LAN_IOEND)
196 _ne_outb(b, PORT2ADDR_NE(port));
197 else
198#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
199 if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
200 *(volatile unsigned char *)__port2addr_ata(port) = b;
201 } else
202#endif
203#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
204 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
205 pcc_iowrite_byte(0, port, &b, sizeof(b), 1, 0);
206 } else
207#endif
208 *(volatile unsigned char *)PORT2ADDR(port) = b;
209}
210
211void _outw(unsigned short w, unsigned long port)
212{
213 if (port >= LAN_IOSTART && port < LAN_IOEND)
214 _ne_outw(w, PORT2ADDR_NE(port));
215 else
216#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
217 if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
218 *(volatile unsigned short *)__port2addr_ata(port) = w;
219 } else
220#endif
221#if defined(CONFIG_USB)
222 if(port >= 0x340 && port < 0x3a0)
223 *(volatile unsigned short *)PORT2ADDR_USB(port) = w;
224 else
225#endif
226#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
227 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
228 pcc_iowrite_word(0, port, &w, sizeof(w), 1, 0);
229 } else
230#endif
231 *(volatile unsigned short *)PORT2ADDR(port) = w;
232}
233
234void _outl(unsigned long l, unsigned long port)
235{
236#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
237 if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
238 pcc_iowrite_word(0, port, &l, sizeof(l), 1, 0);
239 } else
240#endif
241 *(volatile unsigned long *)PORT2ADDR(port) = l;
242}
243
244void _outb_p(unsigned char b, unsigned long port)
245{
246 _outb(b, port);
247 delay();
248}
249
250void _outw_p(unsigned short w, unsigned long port)
251{
252 _outw(w, port);
253 delay();
254}
255
256void _outl_p(unsigned long l, unsigned long port)
257{
258 _outl(l, port);
259 delay();
260}
261
262void _insb(unsigned int port, void *addr, unsigned long count)
263{
264 if (port >= LAN_IOSTART && port < LAN_IOEND)
265 _ne_insb(PORT2ADDR_NE(port), addr, count);
266#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
267 else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
268 unsigned char *buf = addr;
269 unsigned char *portp = __port2addr_ata(port);
270 while (count--)
271 *buf++ = *(volatile unsigned char *)portp;
272 }
273#endif
274#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
275 else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
276 pcc_ioread_byte(0, port, (void *)addr, sizeof(unsigned char),
277 count, 1);
278 }
279#endif
280 else {
281 unsigned char *buf = addr;
282 unsigned char *portp = PORT2ADDR(port);
283 while (count--)
284 *buf++ = *(volatile unsigned char *)portp;
285 }
286}
287
288void _insw(unsigned int port, void *addr, unsigned long count)
289{
290 unsigned short *buf = addr;
291 unsigned short *portp;
292
293 if (port >= LAN_IOSTART && port < LAN_IOEND) {
294 /*
295 * This portion is only used by smc91111.c to read data
296 * from the DATA_REG. Do not swap the data.
297 */
298 portp = PORT2ADDR_NE(port);
299 while (count--)
300 *buf++ = *(volatile unsigned short *)portp;
301#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
302 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
303 pcc_ioread_word(9, port, (void *)addr, sizeof(unsigned short),
304 count, 1);
305#endif
306#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
307 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
308 portp = __port2addr_ata(port);
309 while (count--)
310 *buf++ = *(volatile unsigned short *)portp;
311#endif
312 } else {
313 portp = PORT2ADDR(port);
314 while (count--)
315 *buf++ = *(volatile unsigned short *)portp;
316 }
317}
318
319void _insl(unsigned int port, void *addr, unsigned long count)
320{
321 unsigned long *buf = addr;
322 unsigned long *portp;
323
324 portp = PORT2ADDR(port);
325 while (count--)
326 *buf++ = *(volatile unsigned long *)portp;
327}
328
329void _outsb(unsigned int port, const void *addr, unsigned long count)
330{
331 const unsigned char *buf = addr;
332 unsigned char *portp;
333
334 if (port >= LAN_IOSTART && port < LAN_IOEND) {
335 portp = PORT2ADDR_NE(port);
336 while (count--)
337 _ne_outb(*buf++, portp);
338#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
339 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
340 portp = __port2addr_ata(port);
341 while (count--)
342 *(volatile unsigned char *)portp = *buf++;
343#endif
344#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
345 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
346 pcc_iowrite_byte(0, port, (void *)addr, sizeof(unsigned char),
347 count, 1);
348#endif
349 } else {
350 portp = PORT2ADDR(port);
351 while (count--)
352 *(volatile unsigned char *)portp = *buf++;
353 }
354}
355
356void _outsw(unsigned int port, const void *addr, unsigned long count)
357{
358 const unsigned short *buf = addr;
359 unsigned short *portp;
360
361 if (port >= LAN_IOSTART && port < LAN_IOEND) {
362 /*
363 * This portion is only used by smc91111.c to write data
364 * into the DATA_REG. Do not swap the data.
365 */
366 portp = PORT2ADDR_NE(port);
367 while (count--)
368 *(volatile unsigned short *)portp = *buf++;
369#if defined(CONFIG_IDE) && !defined(CONFIG_M32R_CFC)
370 } else if ((port >= 0x1f0 && port <=0x1f7) || port == 0x3f6) {
371 portp = __port2addr_ata(port);
372 while (count--)
373 *(volatile unsigned short *)portp = *buf++;
374#endif
375#if defined(CONFIG_PCMCIA) && defined(CONFIG_M32R_CFC)
376 } else if (port >= M32R_PCC_IOSTART0 && port <= M32R_PCC_IOEND0) {
377 pcc_iowrite_word(9, port, (void *)addr, sizeof(unsigned short),
378 count, 1);
379#endif
380 } else {
381 portp = PORT2ADDR(port);
382 while (count--)
383 *(volatile unsigned short *)portp = *buf++;
384 }
385}
386
387void _outsl(unsigned int port, const void *addr, unsigned long count)
388{
389 const unsigned long *buf = addr;
390 unsigned char *portp;
391
392 portp = PORT2ADDR(port);
393 while (count--)
394 *(volatile unsigned long *)portp = *buf++;
395}
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
new file mode 100644
index 000000000000..fab13fd85422
--- /dev/null
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -0,0 +1,519 @@
1/*
2 * linux/arch/m32r/platforms/opsput/setup.c
3 *
4 * Setup routines for Renesas OPSPUT Board
5 *
6 * Copyright (c) 2002-2005
7 * Hiroyuki Kondo, Hirokazu Takata,
8 * Hitoshi Yamamoto, Takeo Takahashi, Mamoru Sakugawa
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file "COPYING" in the main directory of this
12 * archive for more details.
13 */
14
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19
20#include <asm/system.h>
21#include <asm/m32r.h>
22#include <asm/io.h>
23
24/*
25 * OPSP Interrupt Control Unit (Level 1)
26 */
27#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
28
29icu_data_t icu_data[OPSPUT_NUM_CPU_IRQ];
30
31static void disable_opsput_irq(unsigned int irq)
32{
33 unsigned long port, data;
34
35 port = irq2port(irq);
36 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
37 outl(data, port);
38}
39
40static void enable_opsput_irq(unsigned int irq)
41{
42 unsigned long port, data;
43
44 port = irq2port(irq);
45 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
46 outl(data, port);
47}
48
49static void mask_and_ack_opsput(unsigned int irq)
50{
51 disable_opsput_irq(irq);
52}
53
54static void end_opsput_irq(unsigned int irq)
55{
56 enable_opsput_irq(irq);
57}
58
59static unsigned int startup_opsput_irq(unsigned int irq)
60{
61 enable_opsput_irq(irq);
62 return (0);
63}
64
65static void shutdown_opsput_irq(unsigned int irq)
66{
67 unsigned long port;
68
69 port = irq2port(irq);
70 outl(M32R_ICUCR_ILEVEL7, port);
71}
72
73static struct hw_interrupt_type opsput_irq_type =
74{
75 .typename = "OPSPUT-IRQ",
76 .startup = startup_opsput_irq,
77 .shutdown = shutdown_opsput_irq,
78 .enable = enable_opsput_irq,
79 .disable = disable_opsput_irq,
80 .ack = mask_and_ack_opsput,
81 .end = end_opsput_irq
82};
83
84/*
85 * Interrupt Control Unit of PLD on OPSPUT (Level 2)
86 */
87#define irq2pldirq(x) ((x) - OPSPUT_PLD_IRQ_BASE)
88#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
89 (((x) - 1) * sizeof(unsigned short)))
90
91typedef struct {
92 unsigned short icucr; /* ICU Control Register */
93} pld_icu_data_t;
94
95static pld_icu_data_t pld_icu_data[OPSPUT_NUM_PLD_IRQ];
96
97static void disable_opsput_pld_irq(unsigned int irq)
98{
99 unsigned long port, data;
100 unsigned int pldirq;
101
102 pldirq = irq2pldirq(irq);
103// disable_opsput_irq(M32R_IRQ_INT1);
104 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
106 outw(data, port);
107}
108
109static void enable_opsput_pld_irq(unsigned int irq)
110{
111 unsigned long port, data;
112 unsigned int pldirq;
113
114 pldirq = irq2pldirq(irq);
115// enable_opsput_irq(M32R_IRQ_INT1);
116 port = pldirq2port(pldirq);
117 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
118 outw(data, port);
119}
120
121static void mask_and_ack_opsput_pld(unsigned int irq)
122{
123 disable_opsput_pld_irq(irq);
124// mask_and_ack_opsput(M32R_IRQ_INT1);
125}
126
127static void end_opsput_pld_irq(unsigned int irq)
128{
129 enable_opsput_pld_irq(irq);
130 end_opsput_irq(M32R_IRQ_INT1);
131}
132
133static unsigned int startup_opsput_pld_irq(unsigned int irq)
134{
135 enable_opsput_pld_irq(irq);
136 return (0);
137}
138
139static void shutdown_opsput_pld_irq(unsigned int irq)
140{
141 unsigned long port;
142 unsigned int pldirq;
143
144 pldirq = irq2pldirq(irq);
145// shutdown_opsput_irq(M32R_IRQ_INT1);
146 port = pldirq2port(pldirq);
147 outw(PLD_ICUCR_ILEVEL7, port);
148}
149
150static struct hw_interrupt_type opsput_pld_irq_type =
151{
152 .typename = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq,
154 .shutdown = shutdown_opsput_pld_irq,
155 .enable = enable_opsput_pld_irq,
156 .disable = disable_opsput_pld_irq,
157 .ack = mask_and_ack_opsput_pld,
158 .end = end_opsput_pld_irq
159};
160
161/*
162 * Interrupt Control Unit of PLD on OPSPUT-LAN (Level 2)
163 */
164#define irq2lanpldirq(x) ((x) - OPSPUT_LAN_PLD_IRQ_BASE)
165#define lanpldirq2port(x) (unsigned long)((int)OPSPUT_LAN_ICUCR1 + \
166 (((x) - 1) * sizeof(unsigned short)))
167
168static pld_icu_data_t lanpld_icu_data[OPSPUT_NUM_LAN_PLD_IRQ];
169
170static void disable_opsput_lanpld_irq(unsigned int irq)
171{
172 unsigned long port, data;
173 unsigned int pldirq;
174
175 pldirq = irq2lanpldirq(irq);
176 port = lanpldirq2port(pldirq);
177 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
178 outw(data, port);
179}
180
181static void enable_opsput_lanpld_irq(unsigned int irq)
182{
183 unsigned long port, data;
184 unsigned int pldirq;
185
186 pldirq = irq2lanpldirq(irq);
187 port = lanpldirq2port(pldirq);
188 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
189 outw(data, port);
190}
191
192static void mask_and_ack_opsput_lanpld(unsigned int irq)
193{
194 disable_opsput_lanpld_irq(irq);
195}
196
197static void end_opsput_lanpld_irq(unsigned int irq)
198{
199 enable_opsput_lanpld_irq(irq);
200 end_opsput_irq(M32R_IRQ_INT0);
201}
202
203static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
204{
205 enable_opsput_lanpld_irq(irq);
206 return (0);
207}
208
209static void shutdown_opsput_lanpld_irq(unsigned int irq)
210{
211 unsigned long port;
212 unsigned int pldirq;
213
214 pldirq = irq2lanpldirq(irq);
215 port = lanpldirq2port(pldirq);
216 outw(PLD_ICUCR_ILEVEL7, port);
217}
218
219static struct hw_interrupt_type opsput_lanpld_irq_type =
220{
221 .typename = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq,
223 .shutdown = shutdown_opsput_lanpld_irq,
224 .enable = enable_opsput_lanpld_irq,
225 .disable = disable_opsput_lanpld_irq,
226 .ack = mask_and_ack_opsput_lanpld,
227 .end = end_opsput_lanpld_irq
228};
229
230/*
231 * Interrupt Control Unit of PLD on OPSPUT-LCD (Level 2)
232 */
233#define irq2lcdpldirq(x) ((x) - OPSPUT_LCD_PLD_IRQ_BASE)
234#define lcdpldirq2port(x) (unsigned long)((int)OPSPUT_LCD_ICUCR1 + \
235 (((x) - 1) * sizeof(unsigned short)))
236
237static pld_icu_data_t lcdpld_icu_data[OPSPUT_NUM_LCD_PLD_IRQ];
238
239static void disable_opsput_lcdpld_irq(unsigned int irq)
240{
241 unsigned long port, data;
242 unsigned int pldirq;
243
244 pldirq = irq2lcdpldirq(irq);
245 port = lcdpldirq2port(pldirq);
246 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
247 outw(data, port);
248}
249
250static void enable_opsput_lcdpld_irq(unsigned int irq)
251{
252 unsigned long port, data;
253 unsigned int pldirq;
254
255 pldirq = irq2lcdpldirq(irq);
256 port = lcdpldirq2port(pldirq);
257 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
258 outw(data, port);
259}
260
261static void mask_and_ack_opsput_lcdpld(unsigned int irq)
262{
263 disable_opsput_lcdpld_irq(irq);
264}
265
266static void end_opsput_lcdpld_irq(unsigned int irq)
267{
268 enable_opsput_lcdpld_irq(irq);
269 end_opsput_irq(M32R_IRQ_INT2);
270}
271
272static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
273{
274 enable_opsput_lcdpld_irq(irq);
275 return (0);
276}
277
278static void shutdown_opsput_lcdpld_irq(unsigned int irq)
279{
280 unsigned long port;
281 unsigned int pldirq;
282
283 pldirq = irq2lcdpldirq(irq);
284 port = lcdpldirq2port(pldirq);
285 outw(PLD_ICUCR_ILEVEL7, port);
286}
287
288static struct hw_interrupt_type opsput_lcdpld_irq_type =
289{
290 "OPSPUT-PLD-LCD-IRQ",
291 startup_opsput_lcdpld_irq,
292 shutdown_opsput_lcdpld_irq,
293 enable_opsput_lcdpld_irq,
294 disable_opsput_lcdpld_irq,
295 mask_and_ack_opsput_lcdpld,
296 end_opsput_lcdpld_irq
297};
298
299void __init init_IRQ(void)
300{
301#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED;
304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type;
305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
308 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
309#endif /* CONFIG_SMC91X */
310
311 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type;
314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
317 disable_opsput_irq(M32R_IRQ_MFT2);
318
319 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type;
322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
325 disable_opsput_irq(M32R_IRQ_SIO0_R);
326
327 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type;
330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
333 disable_opsput_irq(M32R_IRQ_SIO0_S);
334
335 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type;
338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
341 disable_opsput_irq(M32R_IRQ_SIO1_R);
342
343 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type;
346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
349 disable_opsput_irq(M32R_IRQ_SIO1_S);
350
351 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;
353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type;
354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0;
357 disable_opsput_irq(M32R_IRQ_DMA1);
358
359#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;
362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type;
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
366 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
367
368 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;
370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type;
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
374 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
375#endif /* CONFIG_SERIAL_M32R_PLDSIO */
376
377 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;
379 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type;
380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
383 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
384
385 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;
387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type;
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
391 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
392
393 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;
395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type;
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
399 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
400
401 /*
402 * INT0# is used for LAN, DIO
403 * We enable it here.
404 */
405 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
406 enable_opsput_irq(M32R_IRQ_INT0);
407
408 /*
409 * INT1# is used for UART, MMC, CF Controller in FPGA.
410 * We enable it here.
411 */
412 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
413 enable_opsput_irq(M32R_IRQ_INT1);
414
415#if defined(CONFIG_USB)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417
418 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;
419 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type;
420 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0;
421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
423 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
424#endif
425 /*
426 * INT2# is used for BAT, USB, AUDIO
427 * We enable it here.
428 */
429 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
430 enable_opsput_irq(M32R_IRQ_INT2);
431
432#if defined(CONFIG_VIDEO_M32R_AR)
433 /*
434 * INT3# is used for AR
435 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
437 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type;
438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
441 disable_opsput_irq(M32R_IRQ_INT3);
442#endif /* CONFIG_VIDEO_M32R_AR */
443}
444
445#if defined(CONFIG_SMC91X)
446
447#define LAN_IOSTART 0x300
448#define LAN_IOEND 0x320
449static struct resource smc91x_resources[] = {
450 [0] = {
451 .start = (LAN_IOSTART),
452 .end = (LAN_IOEND),
453 .flags = IORESOURCE_MEM,
454 },
455 [1] = {
456 .start = OPSPUT_LAN_IRQ_LAN,
457 .end = OPSPUT_LAN_IRQ_LAN,
458 .flags = IORESOURCE_IRQ,
459 }
460};
461
462static struct platform_device smc91x_device = {
463 .name = "smc91x",
464 .id = 0,
465 .num_resources = ARRAY_SIZE(smc91x_resources),
466 .resource = smc91x_resources,
467};
468#endif
469
470#if defined(CONFIG_FB_S1D13XXX)
471
472#include <video/s1d13xxxfb.h>
473#include <asm/s1d13806.h>
474
475static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
476 .initregs = s1d13xxxfb_initregs,
477 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
478 .platform_init_video = NULL,
479#ifdef CONFIG_PM
480 .platform_suspend_video = NULL,
481 .platform_resume_video = NULL,
482#endif
483};
484
485static struct resource s1d13xxxfb_resources[] = {
486 [0] = {
487 .start = 0x10600000UL,
488 .end = 0x1073FFFFUL,
489 .flags = IORESOURCE_MEM,
490 },
491 [1] = {
492 .start = 0x10400000UL,
493 .end = 0x104001FFUL,
494 .flags = IORESOURCE_MEM,
495 }
496};
497
498static struct platform_device s1d13xxxfb_device = {
499 .name = S1D_DEVICENAME,
500 .id = 0,
501 .dev = {
502 .platform_data = &s1d13xxxfb_data,
503 },
504 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
505 .resource = s1d13xxxfb_resources,
506};
507#endif
508
509static int __init platform_init(void)
510{
511#if defined(CONFIG_SMC91X)
512 platform_device_register(&smc91x_device);
513#endif
514#if defined(CONFIG_FB_S1D13XXX)
515 platform_device_register(&s1d13xxxfb_device);
516#endif
517 return 0;
518}
519arch_initcall(platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 16:53:21 -0500