[PATCH] m32r: Support M32104UT target platform

This patch is for supporting a new target platform, Renesas M32104UT
evaluation board.

The M32104UT is an eval board based on an uT-Engine specification.  This board
has an MMU-less M32R family processor, M32104.
http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf

This board is one of the most popular M32R platform, so we have ported
Linux/M32R to it.

Signed-off-by: Naoto Sugai <Sugai.Naoto@ak.MitsubishiElectric.co.jp>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 10 insertions, 0 deletions

diff --git a/arch/m32r/mm/cache.c b/arch/m32r/mm/cache.c
index 31b0789c1992..c6f72a64ae12 100644
--- a/arch/m32r/mm/cache.c
+++ b/arch/m32r/mm/cache.c
@@ -26,6 +26,16 @@
 #define MCCR            ((volatile unsigned char*)0xfffffffe)
 #define MCCR_IIV        (1UL << 0)      /* I-cache invalidate */
 #define MCCR_ICACHE_INV         MCCR_IIV
+#elif defined(CONFIG_CHIP_M32104)
+#define MCCR            ((volatile unsigned long*)0xfffffffc)
+#define MCCR_IIV        (1UL << 8)      /* I-cache invalidate */
+#define MCCR_DIV        (1UL << 9)      /* D-cache invalidate */
+#define MCCR_DCB        (1UL << 10)     /* D-cache copy back */
+#define MCCR_ICM        (1UL << 0)      /* I-cache mode [0:off,1:on] */
+#define MCCR_DCM        (1UL << 1)      /* D-cache mode [0:off,1:on] */
+#define MCCR_ICACHE_INV         MCCR_IIV
+#define MCCR_DCACHE_CB          MCCR_DCB
+#define MCCR_DCACHE_CBINV       (MCCR_DIV|MCCR_DCB)
 #endif /* CONFIG_CHIP_XNUX2 || CONFIG_CHIP_M32700 */
 
 #ifndef MCCR