litmus-rt.git - The LITMUS^RT kernel.

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author	Linus Torvalds <torvalds@g5.osdl.org>	2005-10-29 00:09:26 -0400
committer	Linus Torvalds <torvalds@g5.osdl.org>	2005-10-29 00:09:26 -0400
commit	8a212ab6b8a4ccc6f3c3d1beba5f92655c576404 (patch)
tree	525271129ff9c692defdd20566f1f7203b18ff24 /arch/m32r/mm
parent	1f419cadff55f548e7356ffebdb9e1b5a8c22275 (diff)
parent	0e1f60609258e18ec0a0477c646101212822d387 (diff)

Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6

Diffstat (limited to 'arch/m32r/mm')

0 files changed, 0 insertions, 0 deletions

/* * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include <nvgpu/types.h> #include <nvgpu/sort.h> #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> #include <nvgpu/bios.h> #include <nvgpu/kmem.h> #include <nvgpu/gk20a.h> #include "gp106/bios_gp106.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" #include "ctrl/ctrlvolt.h" #include "volt.h" #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U static int volt_device_pmu_data_init_super(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) { int status; struct voltage_device *pdev; struct nv_pmu_volt_volt_device_boardobj_set *pset; status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); if (status) { return status; } pdev = (struct voltage_device *)pboard_obj; pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata; pset->switch_delay_us = pdev->switch_delay_us; pset->voltage_min_uv = pdev->voltage_min_uv; pset->voltage_max_uv = pdev->voltage_max_uv; pset->volt_step_uv = pdev->volt_step_uv; return status; } static int volt_device_pmu_data_init_pwm(struct gk20a *g, struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) { int status = 0; struct voltage_device_pwm *pdev; struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset; status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata); if (status) { return status; } pdev = (struct voltage_device_pwm *)pboard_obj; pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata; pset->raw_period = pdev->raw_period; pset->voltage_base_uv = pdev->voltage_base_uv; pset->voltage_offset_scale_uv = pdev->voltage_offset_scale_uv; pset->pwm_source = pdev->source; return status; } static int construct_volt_device(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct voltage_device *ptmp_dev = (struct voltage_device *)pargs; struct voltage_device *pvolt_dev = NULL; int status = 0; status = boardobj_construct_super(g, ppboardobj, size, pargs); if (status) { return status; } pvolt_dev = (struct voltage_device *)*ppboardobj; pvolt_dev->volt_domain = ptmp_dev->volt_domain; pvolt_dev->i2c_dev_idx = ptmp_dev->i2c_dev_idx; pvolt_dev->switch_delay_us = ptmp_dev->switch_delay_us; pvolt_dev->rsvd_0 = VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID; pvolt_dev->rsvd_1 = VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID; pvolt_dev->operation_type = ptmp_dev->operation_type; pvolt_dev->voltage_min_uv = ptmp_dev->voltage_min_uv; pvolt_dev->voltage_max_uv = ptmp_dev->voltage_max_uv; pvolt_dev->super.pmudatainit = volt_device_pmu_data_init_super; return status; } static int construct_pwm_volt_device(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *pargs) { struct boardobj *pboard_obj = NULL; struct voltage_device_pwm *ptmp_dev = (struct voltage_device_pwm *)pargs; struct voltage_device_pwm *pdev = NULL; int status = 0; status = construct_volt_device(g, ppboardobj, size, pargs); if (status) { return status; } pboard_obj = (*ppboardobj); pdev = (struct voltage_device_pwm *)*ppboardobj; pboard_obj->pmudatainit = volt_device_pmu_data_init_pwm; /* Set VOLTAGE_DEVICE_PWM-specific parameters */ pdev->voltage_base_uv = ptmp_dev->voltage_base_uv; pdev->voltage_offset_scale_uv = ptmp_dev->voltage_offset_scale_uv; pdev->source = ptmp_dev->source; pdev->raw_period = ptmp_dev->raw_period; return status; } static struct voltage_device_entry *volt_dev_construct_dev_entry_pwm( struct gk20a *g, u32 voltage_uv, void *pargs) { struct voltage_device_pwm_entry *pentry = NULL; struct voltage_device_pwm_entry *ptmp_entry = (struct voltage_device_pwm_entry *)pargs; pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry)); if (pentry == NULL) { return NULL; } memset(pentry, 0, sizeof(struct voltage_device_pwm_entry)); pentry->super.voltage_uv = voltage_uv; pentry->duty_cycle = ptmp_entry->duty_cycle; return (struct voltage_device_entry *)pentry; } static u8 volt_dev_operation_type_convert(u8 vbios_type) { switch (vbios_type) { case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT: return CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT; case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE: return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE; case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE: return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE; } return CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID; } static struct voltage_device *volt_volt_device_construct(struct gk20a *g, void *pargs) { struct boardobj *pboard_obj = NULL; if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) { int status = construct_pwm_volt_device(g, &pboard_obj, sizeof(struct voltage_device_pwm), pargs); if (status) { nvgpu_err(g, " Could not allocate memory for VOLTAGE_DEVICE type (%x).", BOARDOBJ_GET_TYPE(pargs)); pboard_obj = NULL; } } return (struct voltage_device *)pboard_obj; } static int volt_get_voltage_device_table_1x_psv(struct gk20a *g, struct vbios_voltage_device_table_1x_entry *p_bios_entry, struct voltage_device_metadata *p_Volt_Device_Meta_Data, u8 entry_Idx) { int status = 0; u32 entry_cnt = 0; struct voltage_device *pvolt_dev = NULL; struct voltage_device_pwm *pvolt_dev_pwm = NULL; struct voltage_device_pwm *ptmp_dev = NULL; u32 duty_cycle; u32 frequency_hz; u32 voltage_uv; u8 ext_dev_idx; u8 steps; u8 volt_domain = 0; struct voltage_device_pwm_entry pwm_entry = { { 0 } }; ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm)); if (ptmp_dev == NULL) { return -ENOMEM; } frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0, NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); ext_dev_idx = (u8)BIOS_GET_FIELD(p_bios_entry->param0, NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX); ptmp_dev->super.operation_type = volt_dev_operation_type_convert( (u8)BIOS_GET_FIELD(p_bios_entry->param1, NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE)); if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID) { nvgpu_err(g, " Invalid Voltage Device Operation Type."); status = -EINVAL; goto done; } ptmp_dev->super.voltage_min_uv = (u32)BIOS_GET_FIELD(p_bios_entry->param1, NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM); ptmp_dev->super.voltage_max_uv = (u32)BIOS_GET_FIELD(p_bios_entry->param2, NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM); ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(p_bios_entry->param3, NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE); steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3, NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) { steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT; } ptmp_dev->voltage_offset_scale_uv = BIOS_GET_FIELD(p_bios_entry->param4, NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE); volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, (u8)p_bios_entry->volt_domain); if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) { nvgpu_err(g, "invalid voltage domain = %d", (u8)p_bios_entry->volt_domain); status = -EINVAL; goto done; } if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) { ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; } if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) { ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; } ptmp_dev->raw_period = g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; } else if (ptmp_dev->super.operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) {


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