diff options
| author | Hirokazu Takata <takata@linux-m32r.org> | 2007-02-10 04:43:37 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-11 13:51:20 -0500 |
| commit | 9b87ed790714bd3a8d492feb24f6c48f8bb59c3a (patch) | |
| tree | f8915b927d4617200e7828c14a4335380d05c0be /arch/m32r/mm/fault.c | |
| parent | 9674dcf795a4c7384e4e42c8f38fcb87517b1a43 (diff) | |
[PATCH] m32r: fix do_page_fault and update_mmu_cache
Fix do_page_fault and update_mmu_cache.
* Fix do_page_fault (vmalloc_fault:) to pass error_code correctly
to update_mmu_cache by using a thread-fault code for all m32r chips.
* Fix update_mmu_cache for OPSP chip
- #ifdef CONFIG_CHIP_OPSP portion is a workaround of OPSP;
Add a notfound-case operation to update_mmu_cache for OPSP
like other m32r chip.
- Fix pte_data that was not initialized if no entry found.
Signed-off-by: Kazuhiro Inaoka <inaoka@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/m32r/mm/fault.c')
| -rw-r--r-- | arch/m32r/mm/fault.c | 40 |
1 files changed, 19 insertions, 21 deletions
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c index 9b9feb0f1610..fc7ccdf829e2 100644 --- a/arch/m32r/mm/fault.c +++ b/arch/m32r/mm/fault.c | |||
| @@ -362,8 +362,10 @@ vmalloc_fault: | |||
| 362 | if (!pte_present(*pte_k)) | 362 | if (!pte_present(*pte_k)) |
| 363 | goto no_context; | 363 | goto no_context; |
| 364 | 364 | ||
| 365 | addr = (address & PAGE_MASK) | (error_code & ACE_INSTRUCTION); | 365 | addr = (address & PAGE_MASK); |
| 366 | set_thread_fault_code(error_code); | ||
| 366 | update_mmu_cache(NULL, addr, *pte_k); | 367 | update_mmu_cache(NULL, addr, *pte_k); |
| 368 | set_thread_fault_code(0); | ||
| 367 | return; | 369 | return; |
| 368 | } | 370 | } |
| 369 | } | 371 | } |
| @@ -377,7 +379,7 @@ vmalloc_fault: | |||
| 377 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, | 379 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, |
| 378 | pte_t pte) | 380 | pte_t pte) |
| 379 | { | 381 | { |
| 380 | unsigned long *entry1, *entry2; | 382 | volatile unsigned long *entry1, *entry2; |
| 381 | unsigned long pte_data, flags; | 383 | unsigned long pte_data, flags; |
| 382 | unsigned int *entry_dat; | 384 | unsigned int *entry_dat; |
| 383 | int inst = get_thread_fault_code() & ACE_INSTRUCTION; | 385 | int inst = get_thread_fault_code() & ACE_INSTRUCTION; |
| @@ -391,30 +393,26 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, | |||
| 391 | 393 | ||
| 392 | vaddr = (vaddr & PAGE_MASK) | get_asid(); | 394 | vaddr = (vaddr & PAGE_MASK) | get_asid(); |
| 393 | 395 | ||
| 396 | pte_data = pte_val(pte); | ||
| 397 | |||
| 394 | #ifdef CONFIG_CHIP_OPSP | 398 | #ifdef CONFIG_CHIP_OPSP |
| 395 | entry1 = (unsigned long *)ITLB_BASE; | 399 | entry1 = (unsigned long *)ITLB_BASE; |
| 396 | for(i = 0 ; i < NR_TLB_ENTRIES; i++) { | 400 | for (i = 0; i < NR_TLB_ENTRIES; i++) { |
| 397 | if(*entry1++ == vaddr) { | 401 | if (*entry1++ == vaddr) { |
| 398 | pte_data = pte_val(pte); | 402 | set_tlb_data(entry1, pte_data); |
| 399 | set_tlb_data(entry1, pte_data); | 403 | break; |
| 400 | break; | 404 | } |
| 401 | } | 405 | entry1++; |
| 402 | entry1++; | ||
| 403 | } | 406 | } |
| 404 | entry2 = (unsigned long *)DTLB_BASE; | 407 | entry2 = (unsigned long *)DTLB_BASE; |
| 405 | for(i = 0 ; i < NR_TLB_ENTRIES ; i++) { | 408 | for (i = 0; i < NR_TLB_ENTRIES; i++) { |
| 406 | if(*entry2++ == vaddr) { | 409 | if (*entry2++ == vaddr) { |
| 407 | pte_data = pte_val(pte); | 410 | set_tlb_data(entry2, pte_data); |
| 408 | set_tlb_data(entry2, pte_data); | 411 | break; |
| 409 | break; | 412 | } |
| 410 | } | 413 | entry2++; |
| 411 | entry2++; | ||
| 412 | } | 414 | } |
| 413 | local_irq_restore(flags); | ||
| 414 | return; | ||
| 415 | #else | 415 | #else |
| 416 | pte_data = pte_val(pte); | ||
| 417 | |||
| 418 | /* | 416 | /* |
| 419 | * Update TLB entries | 417 | * Update TLB entries |
| 420 | * entry1: ITLB entry address | 418 | * entry1: ITLB entry address |
| @@ -439,6 +437,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr, | |||
| 439 | "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset) | 437 | "i" (MSVA_offset), "i" (MTOP_offset), "i" (MIDXI_offset) |
| 440 | : "r4", "memory" | 438 | : "r4", "memory" |
| 441 | ); | 439 | ); |
| 440 | #endif | ||
| 442 | 441 | ||
| 443 | if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END)) | 442 | if ((!inst && entry2 >= DTLB_END) || (inst && entry1 >= ITLB_END)) |
| 444 | goto notfound; | 443 | goto notfound; |
| @@ -482,7 +481,6 @@ notfound: | |||
| 482 | set_tlb_data(entry1, pte_data); | 481 | set_tlb_data(entry1, pte_data); |
| 483 | 482 | ||
| 484 | goto found; | 483 | goto found; |
| 485 | #endif | ||
| 486 | } | 484 | } |
| 487 | 485 | ||
| 488 | /*======================================================================* | 486 | /*======================================================================* |
