[PATCH] spinlock consolidation

This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code.  It does the following
things:

 - consolidates and enhances the spinlock/rwlock debugging code

 - simplifies the asm/spinlock.h files

 - encapsulates the raw spinlock type and moves generic spinlock
   features (such as ->break_lock) into the generic code.

 - cleans up the spinlock code hierarchy to get rid of the spaghetti.

Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c.  (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)

Also, i've enhanced the rwlock debugging facility, it will now track
write-owners.  There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.

The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:

 include/asm-i386/spinlock_types.h       |   16
 include/asm-x86_64/spinlock_types.h     |   16

I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:

   SMP                         |  UP
   ----------------------------|-----------------------------------
   asm/spinlock_types_smp.h    |  linux/spinlock_types_up.h
   linux/spinlock_types.h      |  linux/spinlock_types.h
   asm/spinlock_smp.h          |  linux/spinlock_up.h
   linux/spinlock_api_smp.h    |  linux/spinlock_api_up.h
   linux/spinlock.h            |  linux/spinlock.h

/*
 * here's the role of the various spinlock/rwlock related include files:
 *
 * on SMP builds:
 *
 *  asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
 *                        initializers
 *
 *  linux/spinlock_types.h:
 *                        defines the generic type and initializers
 *
 *  asm/spinlock.h:       contains the __raw_spin_*()/etc. lowlevel
 *                        implementations, mostly inline assembly code
 *
 *   (also included on UP-debug builds:)
 *
 *  linux/spinlock_api_smp.h:
 *                        contains the prototypes for the _spin_*() APIs.
 *
 *  linux/spinlock.h:     builds the final spin_*() APIs.
 *
 * on UP builds:
 *
 *  linux/spinlock_type_up.h:
 *                        contains the generic, simplified UP spinlock type.
 *                        (which is an empty structure on non-debug builds)
 *
 *  linux/spinlock_types.h:
 *                        defines the generic type and initializers
 *
 *  linux/spinlock_up.h:
 *                        contains the __raw_spin_*()/etc. version of UP
 *                        builds. (which are NOPs on non-debug, non-preempt
 *                        builds)
 *
 *   (included on UP-non-debug builds:)
 *
 *  linux/spinlock_api_up.h:
 *                        builds the _spin_*() APIs.
 *
 *  linux/spinlock.h:     builds the final spin_*() APIs.
 */

All SMP and UP architectures are converted by this patch.

arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers.  m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.

From: Grant Grundler <grundler@parisc-linux.org>

  Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
  Builds 32-bit SMP kernel (not booted or tested).  I did not try to build
  non-SMP kernels.  That should be trivial to fix up later if necessary.

  I converted bit ops atomic_hash lock to raw_spinlock_t.  Doing so avoids
  some ugly nesting of linux/*.h and asm/*.h files.  Those particular locks
  are well tested and contained entirely inside arch specific code.  I do NOT
  expect any new issues to arise with them.

 If someone does ever need to use debug/metrics with them, then they will
  need to unravel this hairball between spinlocks, atomic ops, and bit ops
  that exist only because parisc has exactly one atomic instruction: LDCW
  (load and clear word).

From: "Luck, Tony" <tony.luck@intel.com>

   ia64 fix

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 12 insertions, 36 deletions

diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
index 48b187f2d2b3..a4576ac7e870 100644
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -892,7 +892,6 @@ unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,
         int try)
 {
         spinlock_t *ipilock;
-        unsigned long flags = 0;
         volatile unsigned long *ipicr_addr;
         unsigned long ipicr_val;
         unsigned long my_physid_mask;
@@ -916,50 +915,27 @@ unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,
          * write IPICRi (send IPIi)
          * unlock ipi_lock[i]
          */
+        spin_lock(ipilock);
         __asm__ __volatile__ (
-                ";; LOCK ipi_lock[i]            \n\t"
+                ";; CHECK IPICRi == 0           \n\t"
                 ".fillinsn                      \n"
                 "1:                             \n\t"
-                "mvfc   %1, psw                 \n\t"
-                "clrpsw #0x40 -> nop            \n\t"
-                DCACHE_CLEAR("r4", "r5", "%2")
-                "lock   r4, @%2                 \n\t"
-                "addi   r4, #-1                 \n\t"
-                "unlock r4, @%2                 \n\t"
-                "mvtc   %1, psw                 \n\t"
-                "bnez   r4, 2f                  \n\t"
-                LOCK_SECTION_START(".balign 4 \n\t")
-                ".fillinsn                      \n"
-                "2:                             \n\t"
-                "ld     r4, @%2                 \n\t"
-                "blez   r4, 2b                  \n\t"
+                "ld     %0, @%1                 \n\t"
+                "and    %0, %4                  \n\t"
+                "beqz   %0, 2f                  \n\t"
+                "bnez   %3, 3f                  \n\t"
                 "bra    1b                      \n\t"
-                LOCK_SECTION_END
-                ";; CHECK IPICRi == 0           \n\t"
-                ".fillinsn                      \n"
-                "3:                             \n\t"
-                "ld     %0, @%3                 \n\t"
-                "and    %0, %6                  \n\t"
-                "beqz   %0, 4f                  \n\t"
-                "bnez   %5, 5f                  \n\t"
-                "bra    3b                      \n\t"
                 ";; WRITE IPICRi (send IPIi)    \n\t"
                 ".fillinsn                      \n"
-                "4:                             \n\t"
-                "st     %4, @%3                 \n\t"
-                ";; UNLOCK ipi_lock[i]          \n\t"
+                "2:                             \n\t"
+                "st     %2, @%1                 \n\t"
                 ".fillinsn                      \n"
-                "5:                             \n\t"
-                "ldi    r4, #1                  \n\t"
-                "st     r4, @%2                 \n\t"
+                "3:                             \n\t"
                 : "=&r"(ipicr_val)
-                : "r"(flags), "r"(&ipilock->slock), "r"(ipicr_addr),
-                  "r"(mask), "r"(try), "r"(my_physid_mask)
-                : "memory", "r4"
-#ifdef CONFIG_CHIP_M32700_TS1
-                , "r5"
-#endif  /* CONFIG_CHIP_M32700_TS1 */
+                : "r"(ipicr_addr), "r"(mask), "r"(try), "r"(my_physid_mask)
+                : "memory"
         );
+        spin_unlock(ipilock);
 
         return ipicr_val;
 }