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authorHirokazu Takata <takata@linux-m32r.org>2007-08-01 08:09:31 -0400
committerHirokazu Takata <takata@linux-m32r.org>2007-09-02 22:30:18 -0400
commit3264f976d3188bea80819793c13a3220b8a4867c (patch)
treee451b9179430ddbbe1102050ebf391433248c1e1 /arch/m32r/kernel/setup_usrv.c
parente6a7ba7efddbb393b726453eae8601ef02b9a610 (diff)
m32r: Rearrange platform-dependent codes
Rearrange platform-dependent codes from arch/m32r/kernel/*.c to arch/m32r/platforms/{platform}/. Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Diffstat (limited to 'arch/m32r/kernel/setup_usrv.c')
-rw-r--r--arch/m32r/kernel/setup_usrv.c249
1 files changed, 0 insertions, 249 deletions
diff --git a/arch/m32r/kernel/setup_usrv.c b/arch/m32r/kernel/setup_usrv.c
deleted file mode 100644
index f5b4b5ac31e7..000000000000
--- a/arch/m32r/kernel/setup_usrv.c
+++ /dev/null
@@ -1,249 +0,0 @@
1/*
2 * linux/arch/m32r/kernel/setup_usrv.c
3 *
4 * Setup routines for MITSUBISHI uServer
5 *
6 * Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
7 * Hitoshi Yamamoto
8 */
9
10#include <linux/irq.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/system.h>
15#include <asm/m32r.h>
16#include <asm/io.h>
17
18#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
19
20icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
21
22static void disable_mappi_irq(unsigned int irq)
23{
24 unsigned long port, data;
25
26 port = irq2port(irq);
27 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
28 outl(data, port);
29}
30
31static void enable_mappi_irq(unsigned int irq)
32{
33 unsigned long port, data;
34
35 port = irq2port(irq);
36 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
37 outl(data, port);
38}
39
40static void mask_and_ack_mappi(unsigned int irq)
41{
42 disable_mappi_irq(irq);
43}
44
45static void end_mappi_irq(unsigned int irq)
46{
47 enable_mappi_irq(irq);
48}
49
50static unsigned int startup_mappi_irq(unsigned int irq)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{
58 unsigned long port;
59
60 port = irq2port(irq);
61 outl(M32R_ICUCR_ILEVEL7, port);
62}
63
64static struct hw_interrupt_type mappi_irq_type =
65{
66 .typename = "M32700-IRQ",
67 .startup = startup_mappi_irq,
68 .shutdown = shutdown_mappi_irq,
69 .enable = enable_mappi_irq,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
73};
74
75/*
76 * Interrupt Control Unit of PLD on M32700UT (Level 2)
77 */
78#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
79#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
80 (((x) - 1) * sizeof(unsigned short)))
81
82typedef struct {
83 unsigned short icucr; /* ICU Control Register */
84} pld_icu_data_t;
85
86static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
87
88static void disable_m32700ut_pld_irq(unsigned int irq)
89{
90 unsigned long port, data;
91 unsigned int pldirq;
92
93 pldirq = irq2pldirq(irq);
94 port = pldirq2port(pldirq);
95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
96 outw(data, port);
97}
98
99static void enable_m32700ut_pld_irq(unsigned int irq)
100{
101 unsigned long port, data;
102 unsigned int pldirq;
103
104 pldirq = irq2pldirq(irq);
105 port = pldirq2port(pldirq);
106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
107 outw(data, port);
108}
109
110static void mask_and_ack_m32700ut_pld(unsigned int irq)
111{
112 disable_m32700ut_pld_irq(irq);
113}
114
115static void end_m32700ut_pld_irq(unsigned int irq)
116{
117 enable_m32700ut_pld_irq(irq);
118 end_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125}
126
127static void shutdown_m32700ut_pld_irq(unsigned int irq)
128{
129 unsigned long port;
130 unsigned int pldirq;
131
132 pldirq = irq2pldirq(irq);
133 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port);
135}
136
137static struct hw_interrupt_type m32700ut_pld_irq_type =
138{
139 .typename = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq,
141 .shutdown = shutdown_m32700ut_pld_irq,
142 .enable = enable_m32700ut_pld_irq,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
146};
147
148void __init init_IRQ(void)
149{
150 static int once = 0;
151 int i;
152
153 if (once)
154 return;
155 else
156 once++;
157
158 /* MFT2 : system timer */
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
164 disable_mappi_irq(M32R_IRQ_MFT2);
165
166#if defined(CONFIG_SERIAL_M32R_SIO)
167 /* SIO0_R : uart receive data */
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
172 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
173 disable_mappi_irq(M32R_IRQ_SIO0_R);
174
175 /* SIO0_S : uart send data */
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
180 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
181 disable_mappi_irq(M32R_IRQ_SIO0_S);
182
183 /* SIO1_R : uart receive data */
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
188 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
189 disable_mappi_irq(M32R_IRQ_SIO1_R);
190
191 /* SIO1_S : uart send data */
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
196 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
197 disable_mappi_irq(M32R_IRQ_SIO1_S);
198#endif /* CONFIG_SERIAL_M32R_SIO */
199
200 /* INT#67-#71: CFC#0 IREQ on PLD */
201 for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) {
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
204 irq_desc[PLD_IRQ_CF0 + i].action = 0;
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
207 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
208 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
209 }
210
211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
212 /* INT#76: 16552D#0 IREQ on PLD */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
218 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
219 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
220
221 /* INT#77: 16552D#1 IREQ on PLD */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
227 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
228 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
229#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
230
231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
232 /* INT#80: AK4524 IREQ on PLD */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
238 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
239 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
240#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
241
242 /*
243 * INT1# is used for UART, MMC, CF Controller in FPGA.
244 * We enable it here.
245 */
246 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
247 enable_mappi_irq(M32R_IRQ_INT1);
248}
249
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