[PATCH] m32r: Fix M32104 cache flushing routines

This patch fixes cache memory parameter setting for the M32104 target.  So
far, its performance seemed to have been degraded due to incorrect cache
parameter setting.

  * arch/m32r/boot/setup.S: Set SFR(Special Fuction Registers) region
    to be non-cachable explicitly.
  * arch/m32r/mm/cache.c: Fix cache flushing routines not to switch off
    the M32104 cache.

Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 12 insertions, 3 deletions

diff --git a/arch/m32r/boot/setup.S b/arch/m32r/boot/setup.S
index 742669fab8a9..398542507d84 100644
--- a/arch/m32r/boot/setup.S
+++ b/arch/m32r/boot/setup.S
@@ -1,11 +1,10 @@
 /*
  *  linux/arch/m32r/boot/setup.S -- A setup code.
  *
- *  Copyright (C) 2001, 2002  Hiroyuki Kondo, Hirokazu Takata,
- *  and Hitoshi Yamamoto
+ *  Copyright (C) 2001-2005   Hiroyuki Kondo, Hirokazu Takata,
+ *                            Hitoshi Yamamoto, Hayato Fujiwara
  *
  */
-/* $Id$ */
 
 #include <linux/linkage.h>
 #include <asm/segment.h>
@@ -81,6 +80,16 @@ ENTRY(boot)
 ;       ldi     r1, #0x00               ; cache off
         st      r1, @r0
 #elif defined(CONFIG_CHIP_M32104)
+        ldi     r0, #-96                ; DNCR0
+        seth    r1, #0x0060             ;  from 0x00600000
+        or3     r1, r1, #0x0005         ;  size 2MB
+        st      r1, @r0
+        seth    r1, #0x0100             ;  from 0x01000000
+        or3     r1, r1, #0x0003         ;  size 16MB
+        st      r1, @+r0
+        seth    r1, #0x0200             ;  from 0x02000000
+        or3     r1, r1, #0x0002         ;  size 32MB
+        st      r1, @+r0
         ldi     r0, #-4              ;LDIMM     (r0, M32R_MCCR)
         ldi     r1, #0x703              ; cache on (with invalidation)
         st      r1, @r0