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authorJack Steiner <steiner@sgi.com>2009-04-02 19:59:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-02 22:05:05 -0400
commitc7296700edc8a0ff49126a4af0bfca6d546c470a (patch)
treedaf4fd74f39247615530c7522cdf39f6dd7ae1e6 /arch/ia64
parenta4c3155719c2a68b6293bc69ce3521018550dd40 (diff)
sgi-gru: add definitions of ia64 GRU MMRs
Add definitions for IA64 GRU MMRs. Signed-off-by: Jack Steiner <steiner@sgi.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/include/asm/uv/uv_mmrs.h158
1 files changed, 155 insertions, 3 deletions
diff --git a/arch/ia64/include/asm/uv/uv_mmrs.h b/arch/ia64/include/asm/uv/uv_mmrs.h
index c149ef085437..fe0b8f05e1a8 100644
--- a/arch/ia64/include/asm/uv/uv_mmrs.h
+++ b/arch/ia64/include/asm/uv/uv_mmrs.h
@@ -8,8 +8,8 @@
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */ 9 */
10 10
11#ifndef __ASM_IA64_UV_MMRS__ 11#ifndef _ASM_IA64_UV_UV_MMRS_H
12#define __ASM_IA64_UV_MMRS__ 12#define _ASM_IA64_UV_UV_MMRS_H
13 13
14#define UV_MMR_ENABLE (1UL << 63) 14#define UV_MMR_ENABLE (1UL << 63)
15 15
@@ -243,6 +243,158 @@ union uvh_event_occurred0_u {
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0 243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244 244
245/* ========================================================================= */ 245/* ========================================================================= */
246/* UVH_GR0_TLB_INT0_CONFIG */
247/* ========================================================================= */
248#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
249
250#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
251#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
252#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
253#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
254#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
255#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
256#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
257#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
258#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
259#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
260#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
261#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
262#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
263#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
264#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
265#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
266
267union uvh_gr0_tlb_int0_config_u {
268 unsigned long v;
269 struct uvh_gr0_tlb_int0_config_s {
270 unsigned long vector_ : 8; /* RW */
271 unsigned long dm : 3; /* RW */
272 unsigned long destmode : 1; /* RW */
273 unsigned long status : 1; /* RO */
274 unsigned long p : 1; /* RO */
275 unsigned long rsvd_14 : 1; /* */
276 unsigned long t : 1; /* RO */
277 unsigned long m : 1; /* RW */
278 unsigned long rsvd_17_31: 15; /* */
279 unsigned long apic_id : 32; /* RW */
280 } s;
281};
282
283/* ========================================================================= */
284/* UVH_GR0_TLB_INT1_CONFIG */
285/* ========================================================================= */
286#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
287
288#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
289#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
290#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
291#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
292#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
293#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
294#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
295#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
296#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
297#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
298#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
299#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
300#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
301#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
302#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
303#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
304
305union uvh_gr0_tlb_int1_config_u {
306 unsigned long v;
307 struct uvh_gr0_tlb_int1_config_s {
308 unsigned long vector_ : 8; /* RW */
309 unsigned long dm : 3; /* RW */
310 unsigned long destmode : 1; /* RW */
311 unsigned long status : 1; /* RO */
312 unsigned long p : 1; /* RO */
313 unsigned long rsvd_14 : 1; /* */
314 unsigned long t : 1; /* RO */
315 unsigned long m : 1; /* RW */
316 unsigned long rsvd_17_31: 15; /* */
317 unsigned long apic_id : 32; /* RW */
318 } s;
319};
320
321/* ========================================================================= */
322/* UVH_GR1_TLB_INT0_CONFIG */
323/* ========================================================================= */
324#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
325
326#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
327#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
328#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
329#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
330#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
331#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
332#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
333#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
334#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
335#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
336#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
337#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
338#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
339#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
340#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
341#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
342
343union uvh_gr1_tlb_int0_config_u {
344 unsigned long v;
345 struct uvh_gr1_tlb_int0_config_s {
346 unsigned long vector_ : 8; /* RW */
347 unsigned long dm : 3; /* RW */
348 unsigned long destmode : 1; /* RW */
349 unsigned long status : 1; /* RO */
350 unsigned long p : 1; /* RO */
351 unsigned long rsvd_14 : 1; /* */
352 unsigned long t : 1; /* RO */
353 unsigned long m : 1; /* RW */
354 unsigned long rsvd_17_31: 15; /* */
355 unsigned long apic_id : 32; /* RW */
356 } s;
357};
358
359/* ========================================================================= */
360/* UVH_GR1_TLB_INT1_CONFIG */
361/* ========================================================================= */
362#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
363
364#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
365#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
366#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
367#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
368#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
369#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
370#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
371#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
372#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
373#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
374#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
375#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
376#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
377#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
378#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
379#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
380
381union uvh_gr1_tlb_int1_config_u {
382 unsigned long v;
383 struct uvh_gr1_tlb_int1_config_s {
384 unsigned long vector_ : 8; /* RW */
385 unsigned long dm : 3; /* RW */
386 unsigned long destmode : 1; /* RW */
387 unsigned long status : 1; /* RO */
388 unsigned long p : 1; /* RO */
389 unsigned long rsvd_14 : 1; /* */
390 unsigned long t : 1; /* RO */
391 unsigned long m : 1; /* RW */
392 unsigned long rsvd_17_31: 15; /* */
393 unsigned long apic_id : 32; /* RW */
394 } s;
395};
396
397/* ========================================================================= */
246/* UVH_INT_CMPB */ 398/* UVH_INT_CMPB */
247/* ========================================================================= */ 399/* ========================================================================= */
248#define UVH_INT_CMPB 0x22080UL 400#define UVH_INT_CMPB 0x22080UL
@@ -670,4 +822,4 @@ union uvh_si_alias2_overlay_config_u {
670}; 822};
671 823
672 824
673#endif /* __ASM_IA64_UV_MMRS__ */ 825#endif /* _ASM_IA64_UV_UV_MMRS_H */