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authorYasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>2007-07-17 08:20:29 -0400
committerTony Luck <tony.luck@intel.com>2007-07-17 12:49:36 -0400
commite3a8f7b8b65c6feadab4384fd7097f79c8c1d898 (patch)
tree0d92d2b7bd4bdaa630a7a723210244a6d9e7ea25 /arch/ia64
parenta5fcaa210626a79465321e344c91a6a7dc3881fa (diff)
[IA64] Remove block structure for locking in iosapic.c
Remove unnecessary indent between spin_lock() and spin_unlock() in iosapic.c. This has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/kernel/iosapic.c301
1 files changed, 135 insertions, 166 deletions
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 37f46527d233..522b13d0bde3 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -209,9 +209,7 @@ gsi_to_irq (unsigned int gsi)
209 * and Linux irq numbers... 209 * and Linux irq numbers...
210 */ 210 */
211 spin_lock_irqsave(&iosapic_lock, flags); 211 spin_lock_irqsave(&iosapic_lock, flags);
212 { 212 irq = _gsi_to_vector(gsi);
213 irq = _gsi_to_vector(gsi);
214 }
215 spin_unlock_irqrestore(&iosapic_lock, flags); 213 spin_unlock_irqrestore(&iosapic_lock, flags);
216 214
217 return irq; 215 return irq;
@@ -322,15 +320,12 @@ mask_irq (unsigned int irq)
322 return; /* not an IOSAPIC interrupt! */ 320 return; /* not an IOSAPIC interrupt! */
323 321
324 spin_lock_irqsave(&iosapic_lock, flags); 322 spin_lock_irqsave(&iosapic_lock, flags);
325 { 323 /* set only the mask bit */
326 /* set only the mask bit */ 324 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
327 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; 325 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
328 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, 326 addr = rte->addr;
329 rte_list) { 327 rte_index = rte->rte_index;
330 addr = rte->addr; 328 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
331 rte_index = rte->rte_index;
332 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
333 }
334 } 329 }
335 spin_unlock_irqrestore(&iosapic_lock, flags); 330 spin_unlock_irqrestore(&iosapic_lock, flags);
336} 331}
@@ -349,14 +344,11 @@ unmask_irq (unsigned int irq)
349 return; /* not an IOSAPIC interrupt! */ 344 return; /* not an IOSAPIC interrupt! */
350 345
351 spin_lock_irqsave(&iosapic_lock, flags); 346 spin_lock_irqsave(&iosapic_lock, flags);
352 { 347 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
353 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; 348 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
354 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, 349 addr = rte->addr;
355 rte_list) { 350 rte_index = rte->rte_index;
356 addr = rte->addr; 351 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
357 rte_index = rte->rte_index;
358 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
359 }
360 } 352 }
361 spin_unlock_irqrestore(&iosapic_lock, flags); 353 spin_unlock_irqrestore(&iosapic_lock, flags);
362} 354}
@@ -391,28 +383,21 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
391 high32 = dest << IOSAPIC_DEST_SHIFT; 383 high32 = dest << IOSAPIC_DEST_SHIFT;
392 384
393 spin_lock_irqsave(&iosapic_lock, flags); 385 spin_lock_irqsave(&iosapic_lock, flags);
394 { 386 low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
395 low32 = iosapic_intr_info[vec].low32 & 387 if (redir)
396 ~(7 << IOSAPIC_DELIVERY_SHIFT); 388 /* change delivery mode to lowest priority */
397 389 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
398 if (redir) 390 else
399 /* change delivery mode to lowest priority */ 391 /* change delivery mode to fixed */
400 low32 |= (IOSAPIC_LOWEST_PRIORITY << 392 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
401 IOSAPIC_DELIVERY_SHIFT); 393
402 else 394 iosapic_intr_info[vec].low32 = low32;
403 /* change delivery mode to fixed */ 395 iosapic_intr_info[vec].dest = dest;
404 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT); 396 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
405 397 addr = rte->addr;
406 iosapic_intr_info[vec].low32 = low32; 398 rte_index = rte->rte_index;
407 iosapic_intr_info[vec].dest = dest; 399 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
408 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, 400 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
409 rte_list) {
410 addr = rte->addr;
411 rte_index = rte->rte_index;
412 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index),
413 high32);
414 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
415 }
416 } 401 }
417 spin_unlock_irqrestore(&iosapic_lock, flags); 402 spin_unlock_irqrestore(&iosapic_lock, flags);
418#endif 403#endif
@@ -797,14 +782,12 @@ again:
797 * don't touch the RTE. 782 * don't touch the RTE.
798 */ 783 */
799 spin_lock_irqsave(&iosapic_lock, flags); 784 spin_lock_irqsave(&iosapic_lock, flags);
800 { 785 vector = gsi_to_vector(gsi);
801 vector = gsi_to_vector(gsi); 786 if (vector > 0) {
802 if (vector > 0) { 787 rte = gsi_vector_to_rte(gsi, vector);
803 rte = gsi_vector_to_rte(gsi, vector); 788 rte->refcnt++;
804 rte->refcnt++; 789 spin_unlock_irqrestore(&iosapic_lock, flags);
805 spin_unlock_irqrestore(&iosapic_lock, flags); 790 return vector;
806 return vector;
807 }
808 } 791 }
809 spin_unlock_irqrestore(&iosapic_lock, flags); 792 spin_unlock_irqrestore(&iosapic_lock, flags);
810 793
@@ -818,35 +801,31 @@ again:
818 801
819 spin_lock_irqsave(&irq_desc[vector].lock, flags); 802 spin_lock_irqsave(&irq_desc[vector].lock, flags);
820 spin_lock(&iosapic_lock); 803 spin_lock(&iosapic_lock);
821 { 804 if (gsi_to_vector(gsi) > 0) {
822 if (gsi_to_vector(gsi) > 0) { 805 if (list_empty(&iosapic_intr_info[vector].rtes))
823 if (list_empty(&iosapic_intr_info[vector].rtes)) 806 free_irq_vector(vector);
824 free_irq_vector(vector); 807 spin_unlock(&iosapic_lock);
825 spin_unlock(&iosapic_lock); 808 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
826 spin_unlock_irqrestore(&irq_desc[vector].lock, 809 goto again;
827 flags); 810 }
828 goto again;
829 }
830
831 dest = get_target_cpu(gsi, vector);
832 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
833 polarity, trigger);
834 if (err < 0) {
835 spin_unlock(&iosapic_lock);
836 spin_unlock_irqrestore(&irq_desc[vector].lock,
837 flags);
838 return err;
839 }
840 811
841 /* 812 dest = get_target_cpu(gsi, vector);
842 * If the vector is shared and already unmasked for 813 err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
843 * other interrupt sources, don't mask it. 814 polarity, trigger);
844 */ 815 if (err < 0) {
845 low32 = iosapic_intr_info[vector].low32; 816 spin_unlock(&iosapic_lock);
846 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK)) 817 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
847 mask = 0; 818 return err;
848 set_rte(gsi, vector, dest, mask);
849 } 819 }
820
821 /*
822 * If the vector is shared and already unmasked for other
823 * interrupt sources, don't mask it.
824 */
825 low32 = iosapic_intr_info[vector].low32;
826 if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
827 mask = 0;
828 set_rte(gsi, vector, dest, mask);
850 spin_unlock(&iosapic_lock); 829 spin_unlock(&iosapic_lock);
851 spin_unlock_irqrestore(&irq_desc[vector].lock, flags); 830 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
852 831
@@ -886,69 +865,64 @@ iosapic_unregister_intr (unsigned int gsi)
886 idesc = irq_desc + irq; 865 idesc = irq_desc + irq;
887 spin_lock_irqsave(&idesc->lock, flags); 866 spin_lock_irqsave(&idesc->lock, flags);
888 spin_lock(&iosapic_lock); 867 spin_lock(&iosapic_lock);
889 { 868 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
890 if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) { 869 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
891 printk(KERN_ERR 870 gsi);
892 "iosapic_unregister_intr(%u) unbalanced\n", 871 WARN_ON(1);
893 gsi); 872 goto out;
894 WARN_ON(1); 873 }
895 goto out;
896 }
897 874
898 if (--rte->refcnt > 0) 875 if (--rte->refcnt > 0)
899 goto out; 876 goto out;
900 877
901 /* Mask the interrupt */ 878 /* Mask the interrupt */
902 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK; 879 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
903 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), 880 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32);
904 low32);
905 881
906 /* Remove the rte entry from the list */ 882 /* Remove the rte entry from the list */
907 list_del(&rte->rte_list); 883 list_del(&rte->rte_list);
908 iosapic_intr_info[vector].count--; 884 iosapic_intr_info[vector].count--;
909 iosapic_free_rte(rte); 885 iosapic_free_rte(rte);
910 index = find_iosapic(gsi); 886 index = find_iosapic(gsi);
911 iosapic_lists[index].rtes_inuse--; 887 iosapic_lists[index].rtes_inuse--;
912 WARN_ON(iosapic_lists[index].rtes_inuse < 0); 888 WARN_ON(iosapic_lists[index].rtes_inuse < 0);
913
914 trigger = iosapic_intr_info[vector].trigger;
915 polarity = iosapic_intr_info[vector].polarity;
916 dest = iosapic_intr_info[vector].dest;
917 printk(KERN_INFO
918 "GSI %u (%s, %s) -> CPU %d (0x%04x)"
919 " vector %d unregistered\n",
920 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
921 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
922 cpu_logical_id(dest), dest, vector);
923 889
924 if (list_empty(&iosapic_intr_info[vector].rtes)) { 890 trigger = iosapic_intr_info[vector].trigger;
925 /* Sanity check */ 891 polarity = iosapic_intr_info[vector].polarity;
926 BUG_ON(iosapic_intr_info[vector].count); 892 dest = iosapic_intr_info[vector].dest;
893 printk(KERN_INFO
894 "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
895 gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
896 (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
897 cpu_logical_id(dest), dest, vector);
927 898
928 /* Clear the interrupt controller descriptor */ 899 if (list_empty(&iosapic_intr_info[vector].rtes)) {
929 idesc->chip = &no_irq_type; 900 /* Sanity check */
901 BUG_ON(iosapic_intr_info[vector].count);
902
903 /* Clear the interrupt controller descriptor */
904 idesc->chip = &no_irq_type;
930 905
931#ifdef CONFIG_SMP 906#ifdef CONFIG_SMP
932 /* Clear affinity */ 907 /* Clear affinity */
933 cpus_setall(idesc->affinity); 908 cpus_setall(idesc->affinity);
934#endif 909#endif
935 910
936 /* Clear the interrupt information */ 911 /* Clear the interrupt information */
937 memset(&iosapic_intr_info[vector], 0, 912 memset(&iosapic_intr_info[vector], 0,
938 sizeof(struct iosapic_intr_info)); 913 sizeof(struct iosapic_intr_info));
939 iosapic_intr_info[vector].low32 |= IOSAPIC_MASK; 914 iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
940 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes); 915 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
941
942 if (idesc->action) {
943 printk(KERN_ERR
944 "interrupt handlers still exist on"
945 "IRQ %u\n", irq);
946 WARN_ON(1);
947 }
948 916
949 /* Free the interrupt vector */ 917 if (idesc->action) {
950 free_irq_vector(vector); 918 printk(KERN_ERR
919 "interrupt handlers still exist on IRQ %u\n",
920 irq);
921 WARN_ON(1);
951 } 922 }
923
924 /* Free the interrupt vector */
925 free_irq_vector(vector);
952 } 926 }
953 out: 927 out:
954 spin_unlock(&iosapic_lock); 928 spin_unlock(&iosapic_lock);
@@ -1108,31 +1082,29 @@ iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1108 unsigned long flags; 1082 unsigned long flags;
1109 1083
1110 spin_lock_irqsave(&iosapic_lock, flags); 1084 spin_lock_irqsave(&iosapic_lock, flags);
1111 { 1085 addr = ioremap(phys_addr, 0);
1112 addr = ioremap(phys_addr, 0); 1086 ver = iosapic_version(addr);
1113 ver = iosapic_version(addr);
1114 1087
1115 if ((err = iosapic_check_gsi_range(gsi_base, ver))) { 1088 if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1116 iounmap(addr); 1089 iounmap(addr);
1117 spin_unlock_irqrestore(&iosapic_lock, flags); 1090 spin_unlock_irqrestore(&iosapic_lock, flags);
1118 return err; 1091 return err;
1119 } 1092 }
1120 1093
1121 /* 1094 /*
1122 * The MAX_REDIR register holds the highest input pin 1095 * The MAX_REDIR register holds the highest input pin number
1123 * number (starting from 0). 1096 * (starting from 0). We add 1 so that we can use it for
1124 * We add 1 so that we can use it for number of pins (= RTEs) 1097 * number of pins (= RTEs)
1125 */ 1098 */
1126 num_rte = ((ver >> 16) & 0xff) + 1; 1099 num_rte = ((ver >> 16) & 0xff) + 1;
1127 1100
1128 index = iosapic_alloc(); 1101 index = iosapic_alloc();
1129 iosapic_lists[index].addr = addr; 1102 iosapic_lists[index].addr = addr;
1130 iosapic_lists[index].gsi_base = gsi_base; 1103 iosapic_lists[index].gsi_base = gsi_base;
1131 iosapic_lists[index].num_rte = num_rte; 1104 iosapic_lists[index].num_rte = num_rte;
1132#ifdef CONFIG_NUMA 1105#ifdef CONFIG_NUMA
1133 iosapic_lists[index].node = MAX_NUMNODES; 1106 iosapic_lists[index].node = MAX_NUMNODES;
1134#endif 1107#endif
1135 }
1136 spin_unlock_irqrestore(&iosapic_lock, flags); 1108 spin_unlock_irqrestore(&iosapic_lock, flags);
1137 1109
1138 if ((gsi_base == 0) && pcat_compat) { 1110 if ((gsi_base == 0) && pcat_compat) {
@@ -1157,25 +1129,22 @@ iosapic_remove (unsigned int gsi_base)
1157 unsigned long flags; 1129 unsigned long flags;
1158 1130
1159 spin_lock_irqsave(&iosapic_lock, flags); 1131 spin_lock_irqsave(&iosapic_lock, flags);
1160 { 1132 index = find_iosapic(gsi_base);
1161 index = find_iosapic(gsi_base); 1133 if (index < 0) {
1162 if (index < 0) { 1134 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1163 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n", 1135 __FUNCTION__, gsi_base);
1164 __FUNCTION__, gsi_base); 1136 goto out;
1165 goto out; 1137 }
1166 }
1167
1168 if (iosapic_lists[index].rtes_inuse) {
1169 err = -EBUSY;
1170 printk(KERN_WARNING
1171 "%s: IOSAPIC for GSI base %u is busy\n",
1172 __FUNCTION__, gsi_base);
1173 goto out;
1174 }
1175 1138
1176 iounmap(iosapic_lists[index].addr); 1139 if (iosapic_lists[index].rtes_inuse) {
1177 iosapic_free(index); 1140 err = -EBUSY;
1141 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1142 __FUNCTION__, gsi_base);
1143 goto out;
1178 } 1144 }
1145
1146 iounmap(iosapic_lists[index].addr);
1147 iosapic_free(index);
1179 out: 1148 out:
1180 spin_unlock_irqrestore(&iosapic_lock, flags); 1149 spin_unlock_irqrestore(&iosapic_lock, flags);
1181 return err; 1150 return err;