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authorH. J. Lu <hjl@lucon.org>2005-10-07 14:01:19 -0400
committerTony Luck <tony.luck@intel.com>2005-10-25 18:05:45 -0400
commit9c184a073bfd650cc791956d6ca79725bb682716 (patch)
treed12206902d58d98c059a0a7b1aa8568253bc39c3 /arch/ia64
parent444d1d9bb5b724f03344c9317bc01d54a9b39073 (diff)
[IA64] Fix 2.6 kernel for the new ia64 assembler
The new ia64 assembler uses slot 1 for the offset of a long (2-slot) instruction and the old assembler uses slot 2. The 2.6 kernel assumes slot 2 and won't boot when the new assembler is used: http://sources.redhat.com/bugzilla/show_bug.cgi?id=1433 This patch will work with either slot 1 or 2. Patch provided by H.J. Lu Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/kernel/patch.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/ia64/kernel/patch.c b/arch/ia64/kernel/patch.c
index 367804a605fa..6a4ac7d70b35 100644
--- a/arch/ia64/kernel/patch.c
+++ b/arch/ia64/kernel/patch.c
@@ -64,22 +64,30 @@ ia64_patch (u64 insn_addr, u64 mask, u64 val)
64void 64void
65ia64_patch_imm64 (u64 insn_addr, u64 val) 65ia64_patch_imm64 (u64 insn_addr, u64 val)
66{ 66{
67 ia64_patch(insn_addr, 67 /* The assembler may generate offset pointing to either slot 1
68 or slot 2 for a long (2-slot) instruction, occupying slots 1
69 and 2. */
70 insn_addr &= -16UL;
71 ia64_patch(insn_addr + 2,
68 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ 72 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
69 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ 73 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
70 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ 74 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
71 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ 75 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
72 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)); 76 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */));
73 ia64_patch(insn_addr - 1, 0x1ffffffffffUL, val >> 22); 77 ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
74} 78}
75 79
76void 80void
77ia64_patch_imm60 (u64 insn_addr, u64 val) 81ia64_patch_imm60 (u64 insn_addr, u64 val)
78{ 82{
79 ia64_patch(insn_addr, 83 /* The assembler may generate offset pointing to either slot 1
84 or slot 2 for a long (2-slot) instruction, occupying slots 1
85 and 2. */
86 insn_addr &= -16UL;
87 ia64_patch(insn_addr + 2,
80 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ 88 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
81 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); 89 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
82 ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); 90 ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18);
83} 91}
84 92
85/* 93/*