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authorYasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com>2007-07-17 08:20:42 -0400
committerTony Luck <tony.luck@intel.com>2007-07-17 12:49:56 -0400
commitc5e3f9e5a2152578db7a37090303ce66d03a7c87 (patch)
treeac1dc6d241258320a88a866c03ad440e4e1ece9a /arch/ia64
parente3a8f7b8b65c6feadab4384fd7097f79c8c1d898 (diff)
[IA64] Remove duplicated members in iosapic_rte_info
Remove duplicated members in iosapic_rte_info in iosapic.c. This patch has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Yasuaki Ishimatsu <isimatu.yasuaki@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/kernel/iosapic.c60
1 files changed, 24 insertions, 36 deletions
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 522b13d0bde3..29ec86c24194 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -117,16 +117,22 @@ static DEFINE_SPINLOCK(iosapic_lock);
117 * These tables map IA-64 vectors to the IOSAPIC pin that generates this 117 * These tables map IA-64 vectors to the IOSAPIC pin that generates this
118 * vector. 118 * vector.
119 */ 119 */
120static struct iosapic {
121 char __iomem *addr; /* base address of IOSAPIC */
122 unsigned int gsi_base; /* GSI base */
123 unsigned short num_rte; /* # of RTEs on this IOSAPIC */
124 int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
125#ifdef CONFIG_NUMA
126 unsigned short node; /* numa node association via pxm */
127#endif
128} iosapic_lists[NR_IOSAPICS];
120 129
121struct iosapic_rte_info { 130struct iosapic_rte_info {
122 struct list_head rte_list; /* node in list of RTEs sharing the 131 struct list_head rte_list; /* RTEs sharing the same vector */
123 * same vector */
124 char __iomem *addr; /* base address of IOSAPIC */
125 unsigned int gsi_base; /* first GSI assigned to this
126 * IOSAPIC */
127 char rte_index; /* IOSAPIC RTE index */ 132 char rte_index; /* IOSAPIC RTE index */
128 int refcnt; /* reference counter */ 133 int refcnt; /* reference counter */
129 unsigned int flags; /* flags */ 134 unsigned int flags; /* flags */
135 struct iosapic *iosapic;
130} ____cacheline_aligned; 136} ____cacheline_aligned;
131 137
132static struct iosapic_intr_info { 138static struct iosapic_intr_info {
@@ -142,17 +148,6 @@ static struct iosapic_intr_info {
142 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */ 148 unsigned char trigger : 1; /* trigger mode (see iosapic.h) */
143} iosapic_intr_info[IA64_NUM_VECTORS]; 149} iosapic_intr_info[IA64_NUM_VECTORS];
144 150
145static struct iosapic {
146 char __iomem *addr; /* base address of IOSAPIC */
147 unsigned int gsi_base; /* first GSI assigned to this
148 * IOSAPIC */
149 unsigned short num_rte; /* # of RTEs on this IOSAPIC */
150 int rtes_inuse; /* # of RTEs in use on this IOSAPIC */
151#ifdef CONFIG_NUMA
152 unsigned short node; /* numa node association via pxm */
153#endif
154} iosapic_lists[NR_IOSAPICS];
155
156static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */ 151static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
157 152
158static int iosapic_kmalloc_ok; 153static int iosapic_kmalloc_ok;
@@ -184,7 +179,7 @@ _gsi_to_vector (unsigned int gsi)
184 for (info = iosapic_intr_info; info < 179 for (info = iosapic_intr_info; info <
185 iosapic_intr_info + IA64_NUM_VECTORS; ++info) 180 iosapic_intr_info + IA64_NUM_VECTORS; ++info)
186 list_for_each_entry(rte, &info->rtes, rte_list) 181 list_for_each_entry(rte, &info->rtes, rte_list)
187 if (rte->gsi_base + rte->rte_index == gsi) 182 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
188 return info - iosapic_intr_info; 183 return info - iosapic_intr_info;
189 return -1; 184 return -1;
190} 185}
@@ -221,7 +216,7 @@ static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
221 struct iosapic_rte_info *rte; 216 struct iosapic_rte_info *rte;
222 217
223 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) 218 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
224 if (rte->gsi_base + rte->rte_index == gsi) 219 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
225 return rte; 220 return rte;
226 return NULL; 221 return NULL;
227} 222}
@@ -243,7 +238,7 @@ set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
243 return; /* not an IOSAPIC interrupt */ 238 return; /* not an IOSAPIC interrupt */
244 239
245 rte_index = rte->rte_index; 240 rte_index = rte->rte_index;
246 addr = rte->addr; 241 addr = rte->iosapic->addr;
247 pol = iosapic_intr_info[vector].polarity; 242 pol = iosapic_intr_info[vector].polarity;
248 trigger = iosapic_intr_info[vector].trigger; 243 trigger = iosapic_intr_info[vector].trigger;
249 dmode = iosapic_intr_info[vector].dmode; 244 dmode = iosapic_intr_info[vector].dmode;
@@ -297,10 +292,10 @@ kexec_disable_iosapic(void)
297 iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) { 292 iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) {
298 list_for_each_entry(rte, &info->rtes, 293 list_for_each_entry(rte, &info->rtes,
299 rte_list) { 294 rte_list) {
300 iosapic_write(rte->addr, 295 iosapic_write(rte->iosapic->addr,
301 IOSAPIC_RTE_LOW(rte->rte_index), 296 IOSAPIC_RTE_LOW(rte->rte_index),
302 IOSAPIC_MASK|vec); 297 IOSAPIC_MASK|vec);
303 iosapic_eoi(rte->addr, vec); 298 iosapic_eoi(rte->iosapic->addr, vec);
304 } 299 }
305 } 300 }
306} 301}
@@ -323,7 +318,7 @@ mask_irq (unsigned int irq)
323 /* set only the mask bit */ 318 /* set only the mask bit */
324 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK; 319 low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
325 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { 320 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
326 addr = rte->addr; 321 addr = rte->iosapic->addr;
327 rte_index = rte->rte_index; 322 rte_index = rte->rte_index;
328 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); 323 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
329 } 324 }
@@ -346,7 +341,7 @@ unmask_irq (unsigned int irq)
346 spin_lock_irqsave(&iosapic_lock, flags); 341 spin_lock_irqsave(&iosapic_lock, flags);
347 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK; 342 low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
348 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { 343 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
349 addr = rte->addr; 344 addr = rte->iosapic->addr;
350 rte_index = rte->rte_index; 345 rte_index = rte->rte_index;
351 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); 346 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
352 } 347 }
@@ -394,7 +389,7 @@ iosapic_set_affinity (unsigned int irq, cpumask_t mask)
394 iosapic_intr_info[vec].low32 = low32; 389 iosapic_intr_info[vec].low32 = low32;
395 iosapic_intr_info[vec].dest = dest; 390 iosapic_intr_info[vec].dest = dest;
396 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) { 391 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
397 addr = rte->addr; 392 addr = rte->iosapic->addr;
398 rte_index = rte->rte_index; 393 rte_index = rte->rte_index;
399 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32); 394 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
400 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32); 395 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
@@ -422,7 +417,7 @@ iosapic_end_level_irq (unsigned int irq)
422 417
423 move_native_irq(irq); 418 move_native_irq(irq);
424 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) 419 list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
425 iosapic_eoi(rte->addr, vec); 420 iosapic_eoi(rte->iosapic->addr, vec);
426} 421}
427 422
428#define iosapic_shutdown_level_irq mask_irq 423#define iosapic_shutdown_level_irq mask_irq
@@ -614,10 +609,7 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
614{ 609{
615 irq_desc_t *idesc; 610 irq_desc_t *idesc;
616 struct hw_interrupt_type *irq_type; 611 struct hw_interrupt_type *irq_type;
617 int rte_index;
618 int index; 612 int index;
619 unsigned long gsi_base;
620 void __iomem *iosapic_address;
621 struct iosapic_rte_info *rte; 613 struct iosapic_rte_info *rte;
622 614
623 index = find_iosapic(gsi); 615 index = find_iosapic(gsi);
@@ -627,9 +619,6 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
627 return -ENODEV; 619 return -ENODEV;
628 } 620 }
629 621
630 iosapic_address = iosapic_lists[index].addr;
631 gsi_base = iosapic_lists[index].gsi_base;
632
633 rte = gsi_vector_to_rte(gsi, vector); 622 rte = gsi_vector_to_rte(gsi, vector);
634 if (!rte) { 623 if (!rte) {
635 rte = iosapic_alloc_rte(); 624 rte = iosapic_alloc_rte();
@@ -639,10 +628,8 @@ register_intr (unsigned int gsi, int vector, unsigned char delivery,
639 return -ENOMEM; 628 return -ENOMEM;
640 } 629 }
641 630
642 rte_index = gsi - gsi_base; 631 rte->iosapic = &iosapic_lists[index];
643 rte->rte_index = rte_index; 632 rte->rte_index = gsi - rte->iosapic->gsi_base;
644 rte->addr = iosapic_address;
645 rte->gsi_base = gsi_base;
646 rte->refcnt++; 633 rte->refcnt++;
647 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes); 634 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
648 iosapic_intr_info[vector].count++; 635 iosapic_intr_info[vector].count++;
@@ -877,7 +864,8 @@ iosapic_unregister_intr (unsigned int gsi)
877 864
878 /* Mask the interrupt */ 865 /* Mask the interrupt */
879 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK; 866 low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
880 iosapic_write(rte->addr, IOSAPIC_RTE_LOW(rte->rte_index), low32); 867 iosapic_write(rte->iosapic->addr,
868 IOSAPIC_RTE_LOW(rte->rte_index), low32);
881 869
882 /* Remove the rte entry from the list */ 870 /* Remove the rte entry from the list */
883 list_del(&rte->rte_list); 871 list_del(&rte->rte_list);