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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-11 15:18:16 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-11 15:18:16 -0500
commit11bd04f6f35621193311c32e0721142b073a7794 (patch)
tree00979740582bb26e8d3756bf3526c85f19f66a46 /arch/ia64
parent4e2ccdb0409146f8cf64a11b6ef82a9c928ced2a (diff)
parent9e0b5b2c447ad0caa075a5cfef86def62e1782ff (diff)
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (109 commits) PCI: fix coding style issue in pci_save_state() PCI: add pci_request_acs PCI: fix BUG_ON triggered by logical PCIe root port removal PCI: remove ifdefed pci_cleanup_aer_correct_error_status PCI: unconditionally clear AER uncorr status register during cleanup x86/PCI: claim SR-IOV BARs in pcibios_allocate_resource PCI: portdrv: remove redundant definitions PCI: portdrv: remove unnecessary struct pcie_port_data PCI: portdrv: minor cleanup for pcie_port_device_register PCI: portdrv: add missing irq cleanup PCI: portdrv: enable device before irq initialization PCI: portdrv: cleanup service irqs initialization PCI: portdrv: check capabilities first PCI: portdrv: move PME capability check PCI: portdrv: remove redundant pcie type calculation PCI: portdrv: cleanup pcie_device registration PCI: portdrv: remove redundant pcie_port_device_probe PCI: Always set prefetchable base/limit upper32 registers PCI: read-modify-write the pcie device control register when initiating pcie flr PCI: show dma_mask bits in /sys ... Fixed up conflicts in: arch/x86/kernel/amd_iommu_init.c drivers/pci/dmar.c drivers/pci/hotplug/acpiphp_glue.c
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/include/asm/xen/hypervisor.h28
-rw-r--r--arch/ia64/pci/pci.c33
2 files changed, 23 insertions, 38 deletions
diff --git a/arch/ia64/include/asm/xen/hypervisor.h b/arch/ia64/include/asm/xen/hypervisor.h
index 88afb54501e4..67455c2ed2b1 100644
--- a/arch/ia64/include/asm/xen/hypervisor.h
+++ b/arch/ia64/include/asm/xen/hypervisor.h
@@ -37,35 +37,9 @@
37#include <xen/interface/xen.h> 37#include <xen/interface/xen.h>
38#include <xen/interface/version.h> /* to compile feature.c */ 38#include <xen/interface/version.h> /* to compile feature.c */
39#include <xen/features.h> /* to comiple xen-netfront.c */ 39#include <xen/features.h> /* to comiple xen-netfront.c */
40#include <xen/xen.h>
40#include <asm/xen/hypercall.h> 41#include <asm/xen/hypercall.h>
41 42
42/* xen_domain_type is set before executing any C code by early_xen_setup */
43enum xen_domain_type {
44 XEN_NATIVE, /* running on bare hardware */
45 XEN_PV_DOMAIN, /* running in a PV domain */
46 XEN_HVM_DOMAIN, /* running in a Xen hvm domain*/
47};
48
49#ifdef CONFIG_XEN
50extern enum xen_domain_type xen_domain_type;
51#else
52#define xen_domain_type XEN_NATIVE
53#endif
54
55#define xen_domain() (xen_domain_type != XEN_NATIVE)
56#define xen_pv_domain() (xen_domain() && \
57 xen_domain_type == XEN_PV_DOMAIN)
58#define xen_hvm_domain() (xen_domain() && \
59 xen_domain_type == XEN_HVM_DOMAIN)
60
61#ifdef CONFIG_XEN_DOM0
62#define xen_initial_domain() (xen_pv_domain() && \
63 (xen_start_info->flags & SIF_INITDOMAIN))
64#else
65#define xen_initial_domain() (0)
66#endif
67
68
69#ifdef CONFIG_XEN 43#ifdef CONFIG_XEN
70extern struct shared_info *HYPERVISOR_shared_info; 44extern struct shared_info *HYPERVISOR_shared_info;
71extern struct start_info *xen_start_info; 45extern struct start_info *xen_start_info;
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index c0fca2c1c858..df639db779f9 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -131,6 +131,7 @@ alloc_pci_controller (int seg)
131} 131}
132 132
133struct pci_root_info { 133struct pci_root_info {
134 struct acpi_device *bridge;
134 struct pci_controller *controller; 135 struct pci_controller *controller;
135 char *name; 136 char *name;
136}; 137};
@@ -297,9 +298,20 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
297 window->offset = offset; 298 window->offset = offset;
298 299
299 if (insert_resource(root, &window->resource)) { 300 if (insert_resource(root, &window->resource)) {
300 printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n", 301 dev_err(&info->bridge->dev,
301 window->resource.start, window->resource.end, 302 "can't allocate host bridge window %pR\n",
302 root->name, info->name); 303 &window->resource);
304 } else {
305 if (offset)
306 dev_info(&info->bridge->dev, "host bridge window %pR "
307 "(PCI address [%#llx-%#llx])\n",
308 &window->resource,
309 window->resource.start - offset,
310 window->resource.end - offset);
311 else
312 dev_info(&info->bridge->dev,
313 "host bridge window %pR\n",
314 &window->resource);
303 } 315 }
304 316
305 return AE_OK; 317 return AE_OK;
@@ -319,8 +331,9 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
319 (res->end - res->start < 16)) 331 (res->end - res->start < 16))
320 continue; 332 continue;
321 if (j >= PCI_BUS_NUM_RESOURCES) { 333 if (j >= PCI_BUS_NUM_RESOURCES) {
322 printk("Ignoring range [%#llx-%#llx] (%lx)\n", 334 dev_warn(&bus->dev,
323 res->start, res->end, res->flags); 335 "ignoring host bridge window %pR (no space)\n",
336 res);
324 continue; 337 continue;
325 } 338 }
326 bus->resource[j++] = res; 339 bus->resource[j++] = res;
@@ -364,6 +377,7 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
364 goto out3; 377 goto out3;
365 378
366 sprintf(name, "PCI Bus %04x:%02x", domain, bus); 379 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
380 info.bridge = device;
367 info.controller = controller; 381 info.controller = controller;
368 info.name = name; 382 info.name = name;
369 acpi_walk_resources(device->handle, METHOD_NAME__CRS, 383 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
@@ -720,9 +734,6 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
720 return ret; 734 return ret;
721} 735}
722 736
723/* It's defined in drivers/pci/pci.c */
724extern u8 pci_cache_line_size;
725
726/** 737/**
727 * set_pci_cacheline_size - determine cacheline size for PCI devices 738 * set_pci_cacheline_size - determine cacheline size for PCI devices
728 * 739 *
@@ -731,7 +742,7 @@ extern u8 pci_cache_line_size;
731 * 742 *
732 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). 743 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
733 */ 744 */
734static void __init set_pci_cacheline_size(void) 745static void __init set_pci_dfl_cacheline_size(void)
735{ 746{
736 unsigned long levels, unique_caches; 747 unsigned long levels, unique_caches;
737 long status; 748 long status;
@@ -751,7 +762,7 @@ static void __init set_pci_cacheline_size(void)
751 "(status=%ld)\n", __func__, status); 762 "(status=%ld)\n", __func__, status);
752 return; 763 return;
753 } 764 }
754 pci_cache_line_size = (1 << cci.pcci_line_size) / 4; 765 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
755} 766}
756 767
757u64 ia64_dma_get_required_mask(struct device *dev) 768u64 ia64_dma_get_required_mask(struct device *dev)
@@ -782,7 +793,7 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);
782 793
783static int __init pcibios_init(void) 794static int __init pcibios_init(void)
784{ 795{
785 set_pci_cacheline_size(); 796 set_pci_dfl_cacheline_size();
786 return 0; 797 return 0;
787} 798}
788 799