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authorMark Maule <maule@sgi.com>2005-11-07 16:48:50 -0500
committerTony Luck <tony.luck@intel.com>2005-11-08 13:07:09 -0500
commit6fb93a92ec2a012fa525499c330522bbb8c18d80 (patch)
treeb64e157335242a8d257fb9d24fe6f09b8f4c99f6 /arch/ia64
parentcbb921443424fb8019e52bae83e442d01f7715ef (diff)
[IA64] altix: misc pci interrupt related fixes
Fix a couple of altix interrupt related bugs. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64')
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_provider.c4
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_reg.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index 7b03b8084ffc..1f500c81002c 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -212,13 +212,13 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
212 pdi_pcibus_info; 212 pdi_pcibus_info;
213 213
214 /* Disable the device's IRQ */ 214 /* Disable the device's IRQ */
215 pcireg_intr_enable_bit_clr(pcibus_info, bit); 215 pcireg_intr_enable_bit_clr(pcibus_info, (1 << bit));
216 216
217 /* Change the device's IRQ */ 217 /* Change the device's IRQ */
218 pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr); 218 pcireg_intr_addr_addr_set(pcibus_info, bit, xtalk_addr);
219 219
220 /* Re-enable the device's IRQ */ 220 /* Re-enable the device's IRQ */
221 pcireg_intr_enable_bit_set(pcibus_info, bit); 221 pcireg_intr_enable_bit_set(pcibus_info, (1 << bit));
222 222
223 pcibr_force_interrupt(sn_irq_info); 223 pcibr_force_interrupt(sn_irq_info);
224 } 224 }
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 4f718c3e93d3..5d534091262c 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -131,7 +131,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
131 __sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits); 131 __sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
132 break; 132 break;
133 case PCIBR_BRIDGETYPE_PIC: 133 case PCIBR_BRIDGETYPE_PIC:
134 __sn_clrq_relaxed(&ptr->pic.p_int_enable, ~bits); 134 __sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
135 break; 135 break;
136 default: 136 default:
137 panic 137 panic