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authorIsaku Yamahata <yamahata@valinux.co.jp>2008-10-16 22:18:07 -0400
committerTony Luck <tony.luck@intel.com>2008-10-17 13:07:33 -0400
commit7477de989faffd4be4adfa3d3e1bf35bdf2e0f75 (patch)
treebd4c3b51538124f36b32a2146cbe2c2dd6c608f8 /arch/ia64/xen/irq_xen.c
parent78c2ae4a0ebd1ab46160e163bf4ca1b7e9463301 (diff)
ia64/pv_ops/xen: implement xen pv_irq_ops.
implement xen pv_irq_ops to paravirtualize irq handling with xen event channel. Cc: Jeremy Fitzhardinge <jeremy@goop.org> Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com> Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/xen/irq_xen.c')
-rw-r--r--arch/ia64/xen/irq_xen.c435
1 files changed, 435 insertions, 0 deletions
diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c
new file mode 100644
index 000000000000..af93aadb68bb
--- /dev/null
+++ b/arch/ia64/xen/irq_xen.c
@@ -0,0 +1,435 @@
1/******************************************************************************
2 * arch/ia64/xen/irq_xen.c
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#include <linux/cpu.h>
24
25#include <xen/interface/xen.h>
26#include <xen/interface/callback.h>
27#include <xen/events.h>
28
29#include <asm/xen/privop.h>
30
31#include "irq_xen.h"
32
33/***************************************************************************
34 * pv_irq_ops
35 * irq operations
36 */
37
38static int
39xen_assign_irq_vector(int irq)
40{
41 struct physdev_irq irq_op;
42
43 irq_op.irq = irq;
44 if (HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op))
45 return -ENOSPC;
46
47 return irq_op.vector;
48}
49
50static void
51xen_free_irq_vector(int vector)
52{
53 struct physdev_irq irq_op;
54
55 if (vector < IA64_FIRST_DEVICE_VECTOR ||
56 vector > IA64_LAST_DEVICE_VECTOR)
57 return;
58
59 irq_op.vector = vector;
60 if (HYPERVISOR_physdev_op(PHYSDEVOP_free_irq_vector, &irq_op))
61 printk(KERN_WARNING "%s: xen_free_irq_vecotr fail vector=%d\n",
62 __func__, vector);
63}
64
65
66static DEFINE_PER_CPU(int, timer_irq) = -1;
67static DEFINE_PER_CPU(int, ipi_irq) = -1;
68static DEFINE_PER_CPU(int, resched_irq) = -1;
69static DEFINE_PER_CPU(int, cmc_irq) = -1;
70static DEFINE_PER_CPU(int, cmcp_irq) = -1;
71static DEFINE_PER_CPU(int, cpep_irq) = -1;
72#define NAME_SIZE 15
73static DEFINE_PER_CPU(char[NAME_SIZE], timer_name);
74static DEFINE_PER_CPU(char[NAME_SIZE], ipi_name);
75static DEFINE_PER_CPU(char[NAME_SIZE], resched_name);
76static DEFINE_PER_CPU(char[NAME_SIZE], cmc_name);
77static DEFINE_PER_CPU(char[NAME_SIZE], cmcp_name);
78static DEFINE_PER_CPU(char[NAME_SIZE], cpep_name);
79#undef NAME_SIZE
80
81struct saved_irq {
82 unsigned int irq;
83 struct irqaction *action;
84};
85/* 16 should be far optimistic value, since only several percpu irqs
86 * are registered early.
87 */
88#define MAX_LATE_IRQ 16
89static struct saved_irq saved_percpu_irqs[MAX_LATE_IRQ];
90static unsigned short late_irq_cnt;
91static unsigned short saved_irq_cnt;
92static int xen_slab_ready;
93
94#ifdef CONFIG_SMP
95/* Dummy stub. Though we may check XEN_RESCHEDULE_VECTOR before __do_IRQ,
96 * it ends up to issue several memory accesses upon percpu data and
97 * thus adds unnecessary traffic to other paths.
98 */
99static irqreturn_t
100xen_dummy_handler(int irq, void *dev_id)
101{
102
103 return IRQ_HANDLED;
104}
105
106static struct irqaction xen_ipi_irqaction = {
107 .handler = handle_IPI,
108 .flags = IRQF_DISABLED,
109 .name = "IPI"
110};
111
112static struct irqaction xen_resched_irqaction = {
113 .handler = xen_dummy_handler,
114 .flags = IRQF_DISABLED,
115 .name = "resched"
116};
117
118static struct irqaction xen_tlb_irqaction = {
119 .handler = xen_dummy_handler,
120 .flags = IRQF_DISABLED,
121 .name = "tlb_flush"
122};
123#endif
124
125/*
126 * This is xen version percpu irq registration, which needs bind
127 * to xen specific evtchn sub-system. One trick here is that xen
128 * evtchn binding interface depends on kmalloc because related
129 * port needs to be freed at device/cpu down. So we cache the
130 * registration on BSP before slab is ready and then deal them
131 * at later point. For rest instances happening after slab ready,
132 * we hook them to xen evtchn immediately.
133 *
134 * FIXME: MCA is not supported by far, and thus "nomca" boot param is
135 * required.
136 */
137static void
138__xen_register_percpu_irq(unsigned int cpu, unsigned int vec,
139 struct irqaction *action, int save)
140{
141 irq_desc_t *desc;
142 int irq = 0;
143
144 if (xen_slab_ready) {
145 switch (vec) {
146 case IA64_TIMER_VECTOR:
147 snprintf(per_cpu(timer_name, cpu),
148 sizeof(per_cpu(timer_name, cpu)),
149 "%s%d", action->name, cpu);
150 irq = bind_virq_to_irqhandler(VIRQ_ITC, cpu,
151 action->handler, action->flags,
152 per_cpu(timer_name, cpu), action->dev_id);
153 per_cpu(timer_irq, cpu) = irq;
154 break;
155 case IA64_IPI_RESCHEDULE:
156 snprintf(per_cpu(resched_name, cpu),
157 sizeof(per_cpu(resched_name, cpu)),
158 "%s%d", action->name, cpu);
159 irq = bind_ipi_to_irqhandler(XEN_RESCHEDULE_VECTOR, cpu,
160 action->handler, action->flags,
161 per_cpu(resched_name, cpu), action->dev_id);
162 per_cpu(resched_irq, cpu) = irq;
163 break;
164 case IA64_IPI_VECTOR:
165 snprintf(per_cpu(ipi_name, cpu),
166 sizeof(per_cpu(ipi_name, cpu)),
167 "%s%d", action->name, cpu);
168 irq = bind_ipi_to_irqhandler(XEN_IPI_VECTOR, cpu,
169 action->handler, action->flags,
170 per_cpu(ipi_name, cpu), action->dev_id);
171 per_cpu(ipi_irq, cpu) = irq;
172 break;
173 case IA64_CMC_VECTOR:
174 snprintf(per_cpu(cmc_name, cpu),
175 sizeof(per_cpu(cmc_name, cpu)),
176 "%s%d", action->name, cpu);
177 irq = bind_virq_to_irqhandler(VIRQ_MCA_CMC, cpu,
178 action->handler,
179 action->flags,
180 per_cpu(cmc_name, cpu),
181 action->dev_id);
182 per_cpu(cmc_irq, cpu) = irq;
183 break;
184 case IA64_CMCP_VECTOR:
185 snprintf(per_cpu(cmcp_name, cpu),
186 sizeof(per_cpu(cmcp_name, cpu)),
187 "%s%d", action->name, cpu);
188 irq = bind_ipi_to_irqhandler(XEN_CMCP_VECTOR, cpu,
189 action->handler,
190 action->flags,
191 per_cpu(cmcp_name, cpu),
192 action->dev_id);
193 per_cpu(cmcp_irq, cpu) = irq;
194 break;
195 case IA64_CPEP_VECTOR:
196 snprintf(per_cpu(cpep_name, cpu),
197 sizeof(per_cpu(cpep_name, cpu)),
198 "%s%d", action->name, cpu);
199 irq = bind_ipi_to_irqhandler(XEN_CPEP_VECTOR, cpu,
200 action->handler,
201 action->flags,
202 per_cpu(cpep_name, cpu),
203 action->dev_id);
204 per_cpu(cpep_irq, cpu) = irq;
205 break;
206 case IA64_CPE_VECTOR:
207 case IA64_MCA_RENDEZ_VECTOR:
208 case IA64_PERFMON_VECTOR:
209 case IA64_MCA_WAKEUP_VECTOR:
210 case IA64_SPURIOUS_INT_VECTOR:
211 /* No need to complain, these aren't supported. */
212 break;
213 default:
214 printk(KERN_WARNING "Percpu irq %d is unsupported "
215 "by xen!\n", vec);
216 break;
217 }
218 BUG_ON(irq < 0);
219
220 if (irq > 0) {
221 /*
222 * Mark percpu. Without this, migrate_irqs() will
223 * mark the interrupt for migrations and trigger it
224 * on cpu hotplug.
225 */
226 desc = irq_desc + irq;
227 desc->status |= IRQ_PER_CPU;
228 }
229 }
230
231 /* For BSP, we cache registered percpu irqs, and then re-walk
232 * them when initializing APs
233 */
234 if (!cpu && save) {
235 BUG_ON(saved_irq_cnt == MAX_LATE_IRQ);
236 saved_percpu_irqs[saved_irq_cnt].irq = vec;
237 saved_percpu_irqs[saved_irq_cnt].action = action;
238 saved_irq_cnt++;
239 if (!xen_slab_ready)
240 late_irq_cnt++;
241 }
242}
243
244static void
245xen_register_percpu_irq(ia64_vector vec, struct irqaction *action)
246{
247 __xen_register_percpu_irq(smp_processor_id(), vec, action, 1);
248}
249
250static void
251xen_bind_early_percpu_irq(void)
252{
253 int i;
254
255 xen_slab_ready = 1;
256 /* There's no race when accessing this cached array, since only
257 * BSP will face with such step shortly
258 */
259 for (i = 0; i < late_irq_cnt; i++)
260 __xen_register_percpu_irq(smp_processor_id(),
261 saved_percpu_irqs[i].irq,
262 saved_percpu_irqs[i].action, 0);
263}
264
265/* FIXME: There's no obvious point to check whether slab is ready. So
266 * a hack is used here by utilizing a late time hook.
267 */
268
269#ifdef CONFIG_HOTPLUG_CPU
270static int __devinit
271unbind_evtchn_callback(struct notifier_block *nfb,
272 unsigned long action, void *hcpu)
273{
274 unsigned int cpu = (unsigned long)hcpu;
275
276 if (action == CPU_DEAD) {
277 /* Unregister evtchn. */
278 if (per_cpu(cpep_irq, cpu) >= 0) {
279 unbind_from_irqhandler(per_cpu(cpep_irq, cpu), NULL);
280 per_cpu(cpep_irq, cpu) = -1;
281 }
282 if (per_cpu(cmcp_irq, cpu) >= 0) {
283 unbind_from_irqhandler(per_cpu(cmcp_irq, cpu), NULL);
284 per_cpu(cmcp_irq, cpu) = -1;
285 }
286 if (per_cpu(cmc_irq, cpu) >= 0) {
287 unbind_from_irqhandler(per_cpu(cmc_irq, cpu), NULL);
288 per_cpu(cmc_irq, cpu) = -1;
289 }
290 if (per_cpu(ipi_irq, cpu) >= 0) {
291 unbind_from_irqhandler(per_cpu(ipi_irq, cpu), NULL);
292 per_cpu(ipi_irq, cpu) = -1;
293 }
294 if (per_cpu(resched_irq, cpu) >= 0) {
295 unbind_from_irqhandler(per_cpu(resched_irq, cpu),
296 NULL);
297 per_cpu(resched_irq, cpu) = -1;
298 }
299 if (per_cpu(timer_irq, cpu) >= 0) {
300 unbind_from_irqhandler(per_cpu(timer_irq, cpu), NULL);
301 per_cpu(timer_irq, cpu) = -1;
302 }
303 }
304 return NOTIFY_OK;
305}
306
307static struct notifier_block unbind_evtchn_notifier = {
308 .notifier_call = unbind_evtchn_callback,
309 .priority = 0
310};
311#endif
312
313void xen_smp_intr_init_early(unsigned int cpu)
314{
315#ifdef CONFIG_SMP
316 unsigned int i;
317
318 for (i = 0; i < saved_irq_cnt; i++)
319 __xen_register_percpu_irq(cpu, saved_percpu_irqs[i].irq,
320 saved_percpu_irqs[i].action, 0);
321#endif
322}
323
324void xen_smp_intr_init(void)
325{
326#ifdef CONFIG_SMP
327 unsigned int cpu = smp_processor_id();
328 struct callback_register event = {
329 .type = CALLBACKTYPE_event,
330 .address = { .ip = (unsigned long)&xen_event_callback },
331 };
332
333 if (cpu == 0) {
334 /* Initialization was already done for boot cpu. */
335#ifdef CONFIG_HOTPLUG_CPU
336 /* Register the notifier only once. */
337 register_cpu_notifier(&unbind_evtchn_notifier);
338#endif
339 return;
340 }
341
342 /* This should be piggyback when setup vcpu guest context */
343 BUG_ON(HYPERVISOR_callback_op(CALLBACKOP_register, &event));
344#endif /* CONFIG_SMP */
345}
346
347void __init
348xen_irq_init(void)
349{
350 struct callback_register event = {
351 .type = CALLBACKTYPE_event,
352 .address = { .ip = (unsigned long)&xen_event_callback },
353 };
354
355 xen_init_IRQ();
356 BUG_ON(HYPERVISOR_callback_op(CALLBACKOP_register, &event));
357 late_time_init = xen_bind_early_percpu_irq;
358}
359
360void
361xen_platform_send_ipi(int cpu, int vector, int delivery_mode, int redirect)
362{
363#ifdef CONFIG_SMP
364 /* TODO: we need to call vcpu_up here */
365 if (unlikely(vector == ap_wakeup_vector)) {
366 /* XXX
367 * This should be in __cpu_up(cpu) in ia64 smpboot.c
368 * like x86. But don't want to modify it,
369 * keep it untouched.
370 */
371 xen_smp_intr_init_early(cpu);
372
373 xen_send_ipi(cpu, vector);
374 /* vcpu_prepare_and_up(cpu); */
375 return;
376 }
377#endif
378
379 switch (vector) {
380 case IA64_IPI_VECTOR:
381 xen_send_IPI_one(cpu, XEN_IPI_VECTOR);
382 break;
383 case IA64_IPI_RESCHEDULE:
384 xen_send_IPI_one(cpu, XEN_RESCHEDULE_VECTOR);
385 break;
386 case IA64_CMCP_VECTOR:
387 xen_send_IPI_one(cpu, XEN_CMCP_VECTOR);
388 break;
389 case IA64_CPEP_VECTOR:
390 xen_send_IPI_one(cpu, XEN_CPEP_VECTOR);
391 break;
392 case IA64_TIMER_VECTOR: {
393 /* this is used only once by check_sal_cache_flush()
394 at boot time */
395 static int used = 0;
396 if (!used) {
397 xen_send_ipi(cpu, IA64_TIMER_VECTOR);
398 used = 1;
399 break;
400 }
401 /* fallthrough */
402 }
403 default:
404 printk(KERN_WARNING "Unsupported IPI type 0x%x\n",
405 vector);
406 notify_remote_via_irq(0); /* defaults to 0 irq */
407 break;
408 }
409}
410
411static void __init
412xen_register_ipi(void)
413{
414#ifdef CONFIG_SMP
415 register_percpu_irq(IA64_IPI_VECTOR, &xen_ipi_irqaction);
416 register_percpu_irq(IA64_IPI_RESCHEDULE, &xen_resched_irqaction);
417 register_percpu_irq(IA64_IPI_LOCAL_TLB_FLUSH, &xen_tlb_irqaction);
418#endif
419}
420
421static void
422xen_resend_irq(unsigned int vector)
423{
424 (void)resend_irq_on_evtchn(vector);
425}
426
427const struct pv_irq_ops xen_irq_ops __initdata = {
428 .register_ipi = xen_register_ipi,
429
430 .assign_irq_vector = xen_assign_irq_vector,
431 .free_irq_vector = xen_free_irq_vector,
432 .register_percpu_irq = xen_register_percpu_irq,
433
434 .resend_irq = xen_resend_irq,
435};