[IA64] Cleanup of arch/ia64/sn and include/asm-ia64/sn

Replace uintX_t declarations with uX declarations.
Replace intX_t declarations with sX declarations.

Signed-off-by: Prarit Bhargava <prarit@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

4 files changed, 50 insertions, 50 deletions

diff --git a/arch/ia64/sn/pci/pcibr/pcibr_ate.c b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
index d1647b863e61..aa3fa5152a32 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_ate.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_ate.c
@@ -18,10 +18,10 @@ int pcibr_invalidate_ate = 0;	/* by default don't invalidate ATE on free */
  * mark_ate: Mark the ate as either free or inuse.
  */
 static void mark_ate(struct ate_resource *ate_resource, int start, int number,
-                     uint64_t value)
+                     u64 value)
 {
 
-        uint64_t *ate = ate_resource->ate;
+        u64 *ate = ate_resource->ate;
         int index;
         int length = 0;
 
@@ -38,7 +38,7 @@ static int find_free_ate(struct ate_resource *ate_resource, int start,
                          int count)
 {
 
-        uint64_t *ate = ate_resource->ate;
+        u64 *ate = ate_resource->ate;
         int index;
         int start_free;
 
@@ -119,7 +119,7 @@ static inline int alloc_ate_resource(struct ate_resource *ate_resource,
 int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
 {
         int status = 0;
-        uint64_t flag;
+        u64 flag;
 
         flag = pcibr_lock(pcibus_info);
         status = alloc_ate_resource(&pcibus_info->pbi_int_ate_resource, count);
@@ -139,7 +139,7 @@ int pcibr_ate_alloc(struct pcibus_info *pcibus_info, int count)
  * Setup an Address Translation Entry as specified.  Use either the Bridge
  * internal maps or the external map RAM, as appropriate.
  */
-static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info,
+static inline u64 *pcibr_ate_addr(struct pcibus_info *pcibus_info,
                                        int ate_index)
 {
         if (ate_index < pcibus_info->pbi_int_ate_size) {
@@ -153,7 +153,7 @@ static inline uint64_t *pcibr_ate_addr(struct pcibus_info *pcibus_info,
  */
 void inline
 ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
-          volatile uint64_t ate)
+          volatile u64 ate)
 {
         while (count-- > 0) {
                 if (ate_index < pcibus_info->pbi_int_ate_size) {
@@ -171,9 +171,9 @@ ate_write(struct pcibus_info *pcibus_info, int ate_index, int count,
 void pcibr_ate_free(struct pcibus_info *pcibus_info, int index)
 {
 
-        volatile uint64_t ate;
+        volatile u64 ate;
         int count;
-        uint64_t flags;
+        u64 flags;
 
         if (pcibr_invalidate_ate) {
                 /* For debugging purposes, clear the valid bit in the ATE */
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index e68332d93171..54ce5b7ceed2 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -41,21 +41,21 @@ extern int sn_ioif_inited;
 
 static dma_addr_t
 pcibr_dmamap_ate32(struct pcidev_info *info,
-                   uint64_t paddr, size_t req_size, uint64_t flags)
+                   u64 paddr, size_t req_size, u64 flags)
 {
 
         struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
         struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
             pdi_pcibus_info;
-        uint8_t internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
+        u8 internal_device = (PCI_SLOT(pcidev_info->pdi_host_pcidev_info->
                                             pdi_linux_pcidev->devfn)) - 1;
         int ate_count;
         int ate_index;
-        uint64_t ate_flags = flags | PCI32_ATE_V;
-        uint64_t ate;
-        uint64_t pci_addr;
-        uint64_t xio_addr;
-        uint64_t offset;
+        u64 ate_flags = flags | PCI32_ATE_V;
+        u64 ate;
+        u64 pci_addr;
+        u64 xio_addr;
+        u64 offset;
 
         /* PIC in PCI-X mode does not supports 32bit PageMap mode */
         if (IS_PIC_SOFT(pcibus_info) && IS_PCIX(pcibus_info)) {
@@ -109,12 +109,12 @@ pcibr_dmamap_ate32(struct pcidev_info *info,
 }
 
 static dma_addr_t
-pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
-                        uint64_t dma_attributes)
+pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
+                        u64 dma_attributes)
 {
         struct pcibus_info *pcibus_info = (struct pcibus_info *)
             ((info->pdi_host_pcidev_info)->pdi_pcibus_info);
-        uint64_t pci_addr;
+        u64 pci_addr;
 
         /* Translate to Crosstalk View of Physical Address */
         pci_addr = (IS_PIC_SOFT(pcibus_info) ? PHYS_TO_DMA(paddr) :
@@ -127,7 +127,7 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
         /* Handle Bridge Chipset differences */
         if (IS_PIC_SOFT(pcibus_info)) {
                 pci_addr |=
-                    ((uint64_t) pcibus_info->
+                    ((u64) pcibus_info->
                      pbi_hub_xid << PIC_PCI64_ATTR_TARG_SHFT);
         } else
                 pci_addr |= TIOCP_PCI64_CMDTYPE_MEM;
@@ -142,17 +142,17 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, uint64_t paddr,
 
 static dma_addr_t
 pcibr_dmatrans_direct32(struct pcidev_info * info,
-                        uint64_t paddr, size_t req_size, uint64_t flags)
+                        u64 paddr, size_t req_size, u64 flags)
 {
 
         struct pcidev_info *pcidev_info = info->pdi_host_pcidev_info;
         struct pcibus_info *pcibus_info = (struct pcibus_info *)pcidev_info->
             pdi_pcibus_info;
-        uint64_t xio_addr;
+        u64 xio_addr;
 
-        uint64_t xio_base;
-        uint64_t offset;
-        uint64_t endoff;
+        u64 xio_base;
+        u64 offset;
+        u64 endoff;
 
         if (IS_PCIX(pcibus_info)) {
                 return 0;
@@ -209,14 +209,14 @@ pcibr_dma_unmap(struct pci_dev *hwdev, dma_addr_t dma_handle, int direction)
  * unlike the PIC Device(x) Write Request Buffer Flush register.
  */
 
-void sn_dma_flush(uint64_t addr)
+void sn_dma_flush(u64 addr)
 {
         nasid_t nasid;
         int is_tio;
         int wid_num;
         int i, j;
-        uint64_t flags;
-        uint64_t itte;
+        u64 flags;
+        u64 itte;
         struct hubdev_info *hubinfo;
         volatile struct sn_flush_device_kernel *p;
         volatile struct sn_flush_device_common *common;
@@ -299,8 +299,8 @@ void sn_dma_flush(uint64_t addr)
                  * If CE ever needs the sn_dma_flush mechanism, we will have
                  * to account for that here and in tioce_bus_fixup().
                  */
-                uint32_t tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
-                uint32_t revnum = XWIDGET_PART_REV_NUM(tio_id);
+                u32 tio_id = HUB_L(TIO_IOSPACE_ADDR(nasid, TIO_NODE_ID));
+                u32 revnum = XWIDGET_PART_REV_NUM(tio_id);
 
                 /* TIOCP BRINGUP WAR (PV907516): Don't write buffer flush reg */
                 if ((1 << XWIDGET_PART_REV_NUM_REV(revnum)) & PV907516) {
@@ -315,7 +315,7 @@ void sn_dma_flush(uint64_t addr)
                 *common->sfdl_flush_addr = 0;
 
                 /* force an interrupt. */
-                *(volatile uint32_t *)(common->sfdl_force_int_addr) = 1;
+                *(volatile u32 *)(common->sfdl_force_int_addr) = 1;
 
                 /* wait for the interrupt to come back. */
                 while (*(common->sfdl_flush_addr) != 0x10f)
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_provider.c b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
index e328e948175d..77a1262751d3 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_provider.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_provider.c
@@ -23,7 +23,7 @@ int
 sal_pcibr_slot_enable(struct pcibus_info *soft, int device, void *resp)
 {
         struct ia64_sal_retval ret_stuff;
-        uint64_t busnum;
+        u64 busnum;
 
         ret_stuff.status = 0;
         ret_stuff.v0 = 0;
@@ -40,7 +40,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
                        void *resp)
 {
         struct ia64_sal_retval ret_stuff;
-        uint64_t busnum;
+        u64 busnum;
 
         ret_stuff.status = 0;
         ret_stuff.v0 = 0;
@@ -56,7 +56,7 @@ sal_pcibr_slot_disable(struct pcibus_info *soft, int device, int action,
 static int sal_pcibr_error_interrupt(struct pcibus_info *soft)
 {
         struct ia64_sal_retval ret_stuff;
-        uint64_t busnum;
+        u64 busnum;
         int segment;
         ret_stuff.status = 0;
         ret_stuff.v0 = 0;
@@ -159,9 +159,9 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *cont
         /* Setup the PMU ATE map */
         soft->pbi_int_ate_resource.lowest_free_index = 0;
         soft->pbi_int_ate_resource.ate =
-            kmalloc(soft->pbi_int_ate_size * sizeof(uint64_t), GFP_KERNEL);
+            kmalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL);
         memset(soft->pbi_int_ate_resource.ate, 0,
-               (soft->pbi_int_ate_size * sizeof(uint64_t)));
+               (soft->pbi_int_ate_size * sizeof(u64)));
 
         if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP) {
                 /* TIO PCI Bridge: find nearest node with CPUs */
@@ -203,7 +203,7 @@ void pcibr_target_interrupt(struct sn_irq_info *sn_irq_info)
         struct pcidev_info *pcidev_info;
         struct pcibus_info *pcibus_info;
         int bit = sn_irq_info->irq_int_bit;
-        uint64_t xtalk_addr = sn_irq_info->irq_xtalkaddr;
+        u64 xtalk_addr = sn_irq_info->irq_xtalkaddr;
 
         pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
         if (pcidev_info) {
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 79fdb91d7259..8b8bbd51d433 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -23,7 +23,7 @@ union br_ptr {
 /*
  * Control Register Access -- Read/Write                            0000_0020
  */
-void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
+void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -43,7 +43,7 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
         }
 }
 
-void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
+void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -66,10 +66,10 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
 /*
  * PCI/PCIX Target Flush Register Access -- Read Only               0000_0050
  */
-uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
+u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-        uint64_t ret = 0;
+        u64 ret = 0;
 
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
@@ -96,10 +96,10 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
 /*
  * Interrupt Status Register Access -- Read Only                    0000_0100
  */
-uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
+u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-        uint64_t ret = 0;
+        u64 ret = 0;
 
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
@@ -121,7 +121,7 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
 /*
  * Interrupt Enable Register Access -- Read/Write                   0000_0108
  */
-void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
+void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -141,7 +141,7 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
         }
 }
 
-void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
+void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -165,7 +165,7 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
  * Intr Host Address Register (int_addr) -- Read/Write  0000_0130 - 0000_0168
  */
 void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
-                               uint64_t addr)
+                               u64 addr)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -217,10 +217,10 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
 /*
  * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
  */
-uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
+u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-        uint64_t ret = 0;
+        u64 ret = 0;
 
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
@@ -242,7 +242,7 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
 }
 
 void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
-                        uint64_t val)
+                        u64 val)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
 
@@ -262,10 +262,10 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
         }
 }
 
-uint64_t __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
+u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
 {
         union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
-        uint64_t __iomem *ret = NULL;
+        u64 __iomem *ret = NULL;
 
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {