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authorDean Nelson <dcn@sgi.com>2005-10-25 15:09:51 -0400
committerTony Luck <tony.luck@intel.com>2005-10-25 19:32:39 -0400
commit4b38fcd4858204cb3667eb7b3aca48ffb1002f05 (patch)
tree2125f5d9689e5bdc64ce2e4f35d8a8220c2e0054 /arch/ia64/sn/kernel/xpc.h
parente54af724c1ae3530c95135157776c9be65cdb747 (diff)
[IA64-SGI] XPC changes to support more than 2k nasids
XPC needs to be changed to support up to 16k nasids on an SGI Altix system. Signed-off-by: Dean Nelson <dcn@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/sn/kernel/xpc.h')
-rw-r--r--arch/ia64/sn/kernel/xpc.h77
1 files changed, 57 insertions, 20 deletions
diff --git a/arch/ia64/sn/kernel/xpc.h b/arch/ia64/sn/kernel/xpc.h
index ae51d7b4c42e..33df1b3758b6 100644
--- a/arch/ia64/sn/kernel/xpc.h
+++ b/arch/ia64/sn/kernel/xpc.h
@@ -68,29 +68,58 @@
68 68
69 69
70/* 70/*
71 * Reserved Page provided by SAL. 71 * the reserved page
72 * 72 *
73 * SAL provides one page per partition of reserved memory. When SAL 73 * SAL reserves one page of memory per partition for XPC. Though a full page
74 * initialization is complete, SAL_signature, SAL_version, partid, 74 * in length (16384 bytes), its starting address is not page aligned, but it
75 * part_nasids, and mach_nasids are set. 75 * is cacheline aligned. The reserved page consists of the following:
76 *
77 * reserved page header
78 *
79 * The first cacheline of the reserved page contains the header
80 * (struct xpc_rsvd_page). Before SAL initialization has completed,
81 * SAL has set up the following fields of the reserved page header:
82 * SAL_signature, SAL_version, partid, and nasids_size. The other
83 * fields are set up by XPC. (xpc_rsvd_page points to the local
84 * partition's reserved page.)
85 *
86 * part_nasids mask
87 * mach_nasids mask
88 *
89 * SAL also sets up two bitmaps (or masks), one that reflects the actual
90 * nasids in this partition (part_nasids), and the other that reflects
91 * the actual nasids in the entire machine (mach_nasids). We're only
92 * interested in the even numbered nasids (which contain the processors
93 * and/or memory), so we only need half as many bits to represent the
94 * nasids. The part_nasids mask is located starting at the first cacheline
95 * following the reserved page header. The mach_nasids mask follows right
96 * after the part_nasids mask. The size in bytes of each mask is reflected
97 * by the reserved page header field 'nasids_size'. (Local partition's
98 * mask pointers are xpc_part_nasids and xpc_mach_nasids.)
99 *
100 * vars
101 * vars part
102 *
103 * Immediately following the mach_nasids mask are the XPC variables
104 * required by other partitions. First are those that are generic to all
105 * partitions (vars), followed on the next available cacheline by those
106 * which are partition specific (vars part). These are setup by XPC.
107 * (Local partition's vars pointers are xpc_vars and xpc_vars_part.)
76 * 108 *
77 * Note: Until vars_pa is set, the partition XPC code has not been initialized. 109 * Note: Until vars_pa is set, the partition XPC code has not been initialized.
78 */ 110 */
79struct xpc_rsvd_page { 111struct xpc_rsvd_page {
80 u64 SAL_signature; /* SAL unique signature */ 112 u64 SAL_signature; /* SAL: unique signature */
81 u64 SAL_version; /* SAL specified version */ 113 u64 SAL_version; /* SAL: version */
82 u8 partid; /* partition ID from SAL */ 114 u8 partid; /* SAL: partition ID */
83 u8 version; 115 u8 version;
84 u8 pad[6]; /* pad to u64 align */ 116 u8 pad1[6]; /* align to next u64 in cacheline */
85 volatile u64 vars_pa; 117 volatile u64 vars_pa;
86 struct timespec stamp; /* time when reserved page was initialized */ 118 struct timespec stamp; /* time when reserved page was setup by XPC */
87 u64 part_nasids[XP_NASID_MASK_WORDS] ____cacheline_aligned; 119 u64 pad2[9]; /* align to last u64 in cacheline */
88 u64 mach_nasids[XP_NASID_MASK_WORDS] ____cacheline_aligned; 120 u64 nasids_size; /* SAL: size of each nasid mask in bytes */
89}; 121};
90 122
91#define XPC_RSVD_PAGE_ALIGNED_SIZE \
92 (L1_CACHE_ALIGN(sizeof(struct xpc_rsvd_page)))
93
94#define XPC_RP_VERSION _XPC_VERSION(1,1) /* version 1.1 of the reserved page */ 123#define XPC_RP_VERSION _XPC_VERSION(1,1) /* version 1.1 of the reserved page */
95 124
96#define XPC_SUPPORTS_RP_STAMP(_version) \ 125#define XPC_SUPPORTS_RP_STAMP(_version) \
@@ -142,8 +171,6 @@ struct xpc_vars {
142 AMO_t *amos_page; /* vaddr of page of AMOs from MSPEC driver */ 171 AMO_t *amos_page; /* vaddr of page of AMOs from MSPEC driver */
143}; 172};
144 173
145#define XPC_VARS_ALIGNED_SIZE (L1_CACHE_ALIGN(sizeof(struct xpc_vars)))
146
147#define XPC_V_VERSION _XPC_VERSION(3,1) /* version 3.1 of the cross vars */ 174#define XPC_V_VERSION _XPC_VERSION(3,1) /* version 3.1 of the cross vars */
148 175
149#define XPC_SUPPORTS_DISENGAGE_REQUEST(_version) \ 176#define XPC_SUPPORTS_DISENGAGE_REQUEST(_version) \
@@ -184,7 +211,7 @@ xpc_disallow_hb(partid_t partid, struct xpc_vars *vars)
184/* 211/*
185 * The AMOs page consists of a number of AMO variables which are divided into 212 * The AMOs page consists of a number of AMO variables which are divided into
186 * four groups, The first two groups are used to identify an IRQ's sender. 213 * four groups, The first two groups are used to identify an IRQ's sender.
187 * These two groups consist of 64 and 16 AMO variables respectively. The last 214 * These two groups consist of 64 and 128 AMO variables respectively. The last
188 * two groups, consisting of just one AMO variable each, are used to identify 215 * two groups, consisting of just one AMO variable each, are used to identify
189 * the remote partitions that are currently engaged (from the viewpoint of 216 * the remote partitions that are currently engaged (from the viewpoint of
190 * the XPC running on the remote partition). 217 * the XPC running on the remote partition).
@@ -233,6 +260,16 @@ struct xpc_vars_part {
233#define XPC_VP_MAGIC2 0x0073726176435058L /* 'XPCvars\0'L (little endian) */ 260#define XPC_VP_MAGIC2 0x0073726176435058L /* 'XPCvars\0'L (little endian) */
234 261
235 262
263/* the reserved page sizes and offsets */
264
265#define XPC_RP_HEADER_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_rsvd_page))
266#define XPC_RP_VARS_SIZE L1_CACHE_ALIGN(sizeof(struct xpc_vars))
267
268#define XPC_RP_PART_NASIDS(_rp) (u64 *) ((u8 *) _rp + XPC_RP_HEADER_SIZE)
269#define XPC_RP_MACH_NASIDS(_rp) (XPC_RP_PART_NASIDS(_rp) + xp_nasid_mask_words)
270#define XPC_RP_VARS(_rp) ((struct xpc_vars *) XPC_RP_MACH_NASIDS(_rp) + xp_nasid_mask_words)
271#define XPC_RP_VARS_PART(_rp) (struct xpc_vars_part *) ((u8 *) XPC_RP_VARS(rp) + XPC_RP_VARS_SIZE)
272
236 273
237/* 274/*
238 * Functions registered by add_timer() or called by kernel_thread() only 275 * Functions registered by add_timer() or called by kernel_thread() only
@@ -1147,9 +1184,9 @@ xpc_IPI_send_local_msgrequest(struct xpc_channel *ch)
1147 * cacheable mapping for the entire region. This will prevent speculative 1184 * cacheable mapping for the entire region. This will prevent speculative
1148 * reading of cached copies of our lines from being issued which will cause 1185 * reading of cached copies of our lines from being issued which will cause
1149 * a PI FSB Protocol error to be generated by the SHUB. For XPC, we need 64 1186 * a PI FSB Protocol error to be generated by the SHUB. For XPC, we need 64
1150 * (XP_MAX_PARTITIONS) AMO variables for message notification and an 1187 * AMO variables (based on XP_MAX_PARTITIONS) for message notification and an
1151 * additional 16 (XP_NASID_MASK_WORDS) AMO variables for partition activation 1188 * additional 128 AMO variables (based on XP_NASID_MASK_WORDS) for partition
1152 * and 2 AMO variables for partition deactivation. 1189 * activation and 2 AMO variables for partition deactivation.
1153 */ 1190 */
1154static inline AMO_t * 1191static inline AMO_t *
1155xpc_IPI_init(int index) 1192xpc_IPI_init(int index)