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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/ia64/sn/include
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/ia64/sn/include')
-rw-r--r--arch/ia64/sn/include/ioerror.h81
-rw-r--r--arch/ia64/sn/include/pci/pcibr_provider.h149
-rw-r--r--arch/ia64/sn/include/pci/pcibus_provider_defs.h43
-rw-r--r--arch/ia64/sn/include/pci/pcidev.h54
-rw-r--r--arch/ia64/sn/include/pci/pic.h261
-rw-r--r--arch/ia64/sn/include/pci/tiocp.h256
-rw-r--r--arch/ia64/sn/include/tio.h37
-rw-r--r--arch/ia64/sn/include/xtalk/hubdev.h67
-rw-r--r--arch/ia64/sn/include/xtalk/xbow.h291
-rw-r--r--arch/ia64/sn/include/xtalk/xwidgetdev.h70
10 files changed, 1309 insertions, 0 deletions
diff --git a/arch/ia64/sn/include/ioerror.h b/arch/ia64/sn/include/ioerror.h
new file mode 100644
index 000000000000..e68f2b0789a7
--- /dev/null
+++ b/arch/ia64/sn/include/ioerror.h
@@ -0,0 +1,81 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_IOERROR_H
9#define _ASM_IA64_SN_IOERROR_H
10
11/*
12 * IO error structure.
13 *
14 * This structure would expand to hold the information retrieved from
15 * all IO related error registers.
16 *
17 * This structure is defined to hold all system specific
18 * information related to a single error.
19 *
20 * This serves a couple of purpose.
21 * - Error handling often involves translating one form of address to other
22 * form. So, instead of having different data structures at each level,
23 * we have a single structure, and the appropriate fields get filled in
24 * at each layer.
25 * - This provides a way to dump all error related information in any layer
26 * of erorr handling (debugging aid).
27 *
28 * A second possibility is to allow each layer to define its own error
29 * data structure, and fill in the proper fields. This has the advantage
30 * of isolating the layers.
31 * A big concern is the potential stack usage (and overflow), if each layer
32 * defines these structures on stack (assuming we don't want to do kmalloc.
33 *
34 * Any layer wishing to pass extra information to a layer next to it in
35 * error handling hierarchy, can do so as a separate parameter.
36 */
37
38typedef struct io_error_s {
39 /* Bit fields indicating which structure fields are valid */
40 union {
41 struct {
42 unsigned ievb_errortype:1;
43 unsigned ievb_widgetnum:1;
44 unsigned ievb_widgetdev:1;
45 unsigned ievb_srccpu:1;
46 unsigned ievb_srcnode:1;
47 unsigned ievb_errnode:1;
48 unsigned ievb_sysioaddr:1;
49 unsigned ievb_xtalkaddr:1;
50 unsigned ievb_busspace:1;
51 unsigned ievb_busaddr:1;
52 unsigned ievb_vaddr:1;
53 unsigned ievb_memaddr:1;
54 unsigned ievb_epc:1;
55 unsigned ievb_ef:1;
56 unsigned ievb_tnum:1;
57 } iev_b;
58 unsigned iev_a;
59 } ie_v;
60
61 short ie_errortype; /* error type: extra info about error */
62 short ie_widgetnum; /* Widget number that's in error */
63 short ie_widgetdev; /* Device within widget in error */
64 cpuid_t ie_srccpu; /* CPU on srcnode generating error */
65 cnodeid_t ie_srcnode; /* Node which caused the error */
66 cnodeid_t ie_errnode; /* Node where error was noticed */
67 iopaddr_t ie_sysioaddr; /* Sys specific IO address */
68 iopaddr_t ie_xtalkaddr; /* Xtalk (48bit) addr of Error */
69 iopaddr_t ie_busspace; /* Bus specific address space */
70 iopaddr_t ie_busaddr; /* Bus specific address */
71 caddr_t ie_vaddr; /* Virtual address of error */
72 iopaddr_t ie_memaddr; /* Physical memory address */
73 caddr_t ie_epc; /* pc when error reported */
74 caddr_t ie_ef; /* eframe when error reported */
75 short ie_tnum; /* Xtalk TNUM field */
76} ioerror_t;
77
78#define IOERROR_INIT(e) do { (e)->ie_v.iev_a = 0; } while (0)
79#define IOERROR_SETVALUE(e,f,v) do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0)
80
81#endif /* _ASM_IA64_SN_IOERROR_H */
diff --git a/arch/ia64/sn/include/pci/pcibr_provider.h b/arch/ia64/sn/include/pci/pcibr_provider.h
new file mode 100644
index 000000000000..b1f05ffec70b
--- /dev/null
+++ b/arch/ia64/sn/include/pci/pcibr_provider.h
@@ -0,0 +1,149 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10
11/* Workarounds */
12#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
13
14#define BUSTYPE_MASK 0x1
15
16/* Macros given a pcibus structure */
17#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
18#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
19 asic == PCIIO_ASIC_TYPE_TIOCP)
20#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
21
22
23/*
24 * The different PCI Bridge types supported on the SGI Altix platforms
25 */
26#define PCIBR_BRIDGETYPE_UNKNOWN -1
27#define PCIBR_BRIDGETYPE_PIC 2
28#define PCIBR_BRIDGETYPE_TIOCP 3
29
30/*
31 * Bridge 64bit Direct Map Attributes
32 */
33#define PCI64_ATTR_PREF (1ull << 59)
34#define PCI64_ATTR_PREC (1ull << 58)
35#define PCI64_ATTR_VIRTUAL (1ull << 57)
36#define PCI64_ATTR_BAR (1ull << 56)
37#define PCI64_ATTR_SWAP (1ull << 55)
38#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
39
40#define PCI32_LOCAL_BASE 0
41#define PCI32_MAPPED_BASE 0x40000000
42#define PCI32_DIRECT_BASE 0x80000000
43
44#define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \
45 (uint64_t)(x) >= PCI32_MAPPED_BASE)
46#define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE)
47
48
49/*
50 * Bridge PMU Address Transaltion Entry Attibutes
51 */
52#define PCI32_ATE_V (0x1 << 0)
53#define PCI32_ATE_CO (0x1 << 1)
54#define PCI32_ATE_PREC (0x1 << 2)
55#define PCI32_ATE_PREF (0x1 << 3)
56#define PCI32_ATE_BAR (0x1 << 4)
57#define PCI32_ATE_ADDR_SHFT 12
58
59#define MINIMAL_ATES_REQUIRED(addr, size) \
60 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
61
62#define MINIMAL_ATE_FLAG(addr, size) \
63 (MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
64
65/* bit 29 of the pci address is the SWAP bit */
66#define ATE_SWAPSHIFT 29
67#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
68#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
69
70/*
71 * I/O page size
72 */
73#if PAGE_SIZE < 16384
74#define IOPFNSHIFT 12 /* 4K per mapped page */
75#else
76#define IOPFNSHIFT 14 /* 16K per mapped page */
77#endif
78
79#define IOPGSIZE (1 << IOPFNSHIFT)
80#define IOPG(x) ((x) >> IOPFNSHIFT)
81#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
82
83#define PCIBR_DEV_SWAP_DIR (1ull << 19)
84#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
85
86/*
87 * PMU resources.
88 */
89struct ate_resource{
90 uint64_t *ate;
91 uint64_t num_ate;
92 uint64_t lowest_free_index;
93};
94
95struct pcibus_info {
96 struct pcibus_bussoft pbi_buscommon; /* common header */
97 uint32_t pbi_moduleid;
98 short pbi_bridge_type;
99 short pbi_bridge_mode;
100
101 struct ate_resource pbi_int_ate_resource;
102 uint64_t pbi_int_ate_size;
103
104 uint64_t pbi_dir_xbase;
105 char pbi_hub_xid;
106
107 uint64_t pbi_devreg[8];
108 spinlock_t pbi_lock;
109
110 uint32_t pbi_valid_devices;
111 uint32_t pbi_enabled_devices;
112};
113
114/*
115 * pcibus_info structure locking macros
116 */
117inline static unsigned long
118pcibr_lock(struct pcibus_info *pcibus_info)
119{
120 unsigned long flag;
121 spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
122 return(flag);
123}
124#define pcibr_unlock(pcibus_info, flag) spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
125
126extern void *pcibr_bus_fixup(struct pcibus_bussoft *);
127extern uint64_t pcibr_dma_map(struct pcidev_info *, unsigned long, size_t, unsigned int);
128extern void pcibr_dma_unmap(struct pcidev_info *, dma_addr_t, int);
129
130/*
131 * prototypes for the bridge asic register access routines in pcibr_reg.c
132 */
133extern void pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
134extern void pcireg_control_bit_set(struct pcibus_info *, uint64_t);
135extern uint64_t pcireg_tflush_get(struct pcibus_info *);
136extern uint64_t pcireg_intr_status_get(struct pcibus_info *);
137extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
138extern void pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
139extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
140extern void pcireg_force_intr_set(struct pcibus_info *, int);
141extern uint64_t pcireg_wrb_flush_get(struct pcibus_info *, int);
142extern void pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
143extern uint64_t * pcireg_int_ate_addr(struct pcibus_info *, int);
144extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
145extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
146extern int pcibr_ate_alloc(struct pcibus_info *, int);
147extern void pcibr_ate_free(struct pcibus_info *, int);
148extern void ate_write(struct pcibus_info *, int, int, uint64_t);
149#endif
diff --git a/arch/ia64/sn/include/pci/pcibus_provider_defs.h b/arch/ia64/sn/include/pci/pcibus_provider_defs.h
new file mode 100644
index 000000000000..07065615bbea
--- /dev/null
+++ b/arch/ia64/sn/include/pci/pcibus_provider_defs.h
@@ -0,0 +1,43 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
10
11/*
12 * SN pci asic types. Do not ever renumber these or reuse values. The
13 * values must agree with what prom thinks they are.
14 */
15
16#define PCIIO_ASIC_TYPE_UNKNOWN 0
17#define PCIIO_ASIC_TYPE_PPB 1
18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3
20
21/*
22 * Common pciio bus provider data. There should be one of these as the
23 * first field in any pciio based provider soft structure (e.g. pcibr_soft
24 * tioca_soft, etc).
25 */
26
27struct pcibus_bussoft {
28 uint32_t bs_asic_type; /* chipset type */
29 uint32_t bs_xid; /* xwidget id */
30 uint64_t bs_persist_busnum; /* Persistent Bus Number */
31 uint64_t bs_legacy_io; /* legacy io pio addr */
32 uint64_t bs_legacy_mem; /* legacy mem pio addr */
33 uint64_t bs_base; /* widget base */
34 struct xwidget_info *bs_xwidget_info;
35};
36
37/*
38 * DMA mapping flags
39 */
40
41#define SN_PCIDMA_CONSISTENT 0x0001
42
43#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/arch/ia64/sn/include/pci/pcidev.h b/arch/ia64/sn/include/pci/pcidev.h
new file mode 100644
index 000000000000..81eb95d3bf47
--- /dev/null
+++ b/arch/ia64/sn/include/pci/pcidev.h
@@ -0,0 +1,54 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
9#define _ASM_IA64_SN_PCI_PCIDEV_H
10
11#include <linux/pci.h>
12
13extern struct sn_irq_info **sn_irq;
14
15#define SN_PCIDEV_INFO(pci_dev) \
16 ((struct pcidev_info *)(pci_dev)->sysdata)
17
18/*
19 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
20 * this only works for root busses, not for busses represented by PPB's.
21 */
22
23#define SN_PCIBUS_BUSSOFT(pci_bus) \
24 ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
25
26/*
27 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
28 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
29 * due to possible PPB's in the path.
30 */
31
32#define SN_PCIDEV_BUSSOFT(pci_dev) \
33 (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
34
35#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
36#define PCIIO_SLOT_NONE 255
37#define PCIIO_FUNC_NONE 255
38#define PCIIO_VENDOR_ID_NONE (-1)
39
40struct pcidev_info {
41 uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
42 uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
43
44 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
45 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
46 struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
47
48 struct sn_irq_info *pdi_sn_irq_info;
49};
50
51extern void sn_irq_fixup(struct pci_dev *pci_dev,
52 struct sn_irq_info *sn_irq_info);
53
54#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/arch/ia64/sn/include/pci/pic.h b/arch/ia64/sn/include/pci/pic.h
new file mode 100644
index 000000000000..fd18acecb1e6
--- /dev/null
+++ b/arch/ia64/sn/include/pci/pic.h
@@ -0,0 +1,261 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PIC_H
9#define _ASM_IA64_SN_PCI_PIC_H
10
11/*
12 * PIC AS DEVICE ZERO
13 * ------------------
14 *
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says:
20 *
21 * The current PCI-X bus specification now defines that the parent
22 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
23 * reduced the total number of devices from 8 to 4 and removed the
24 * device registers and windows, now only supporting devices 0,1,2, and
25 * 3. PIC did leave all 8 configuration space windows. The reason was
26 * there was nothing to gain by removing them. Here in lies the problem.
27 * The device numbering we do using 0 through 3 is unrelated to the device
28 * numbering which PCI-X requires in configuration space. In the past we
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our:
32 *
33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4.
37 *
38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that:
41 *
42 * Internal Slot#
43 * |
44 * | 0 1 2 3
45 * ----------|---------------------------------------
46 * config | 0x21000 0x22000 0x23000 0x24000
47 * |
48 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
49 * |
50 * odd rrb | n/a 0[1] n/a 1[1]
51 * |
52 * int dev | 00 01 10 11
53 * |
54 * ext slot# | 1 2 3 4
55 * ----------|---------------------------------------
56 */
57
58#define PIC_ATE_TARGETID_SHFT 8
59#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
60#define PIC_PCI64_ATTR_TARG_SHFT 60
61
62
63/*****************************************************************************
64 *********************** PIC MMR structure mapping ***************************
65 *****************************************************************************/
66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits.
70 */
71
72struct pic {
73
74 /* 0x000000-0x00FFFF -- Local Registers */
75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 uint64_t p_wid_id; /* 0x000000 */
78 uint64_t p_wid_stat; /* 0x000008 */
79 uint64_t p_wid_err_upper; /* 0x000010 */
80 uint64_t p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower
82 uint64_t p_wid_control; /* 0x000020 */
83 uint64_t p_wid_req_timeout; /* 0x000028 */
84 uint64_t p_wid_int_upper; /* 0x000030 */
85 uint64_t p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower
87 uint64_t p_wid_err_cmdword; /* 0x000040 */
88 uint64_t p_wid_llp; /* 0x000048 */
89 uint64_t p_wid_tflush; /* 0x000050 */
90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 uint64_t p_wid_aux_err; /* 0x000058 */
93 uint64_t p_wid_resp_upper; /* 0x000060 */
94 uint64_t p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower
96 uint64_t p_wid_tst_pin_ctrl; /* 0x000070 */
97 uint64_t p_wid_addr_lkerr; /* 0x000078 */
98
99 /* 0x000080-0x00008F -- PMU & MAP */
100 uint64_t p_dir_map; /* 0x000080 */
101 uint64_t _pad_000088; /* 0x000088 */
102
103 /* 0x000090-0x00009F -- SSRAM */
104 uint64_t p_map_fault; /* 0x000090 */
105 uint64_t _pad_000098; /* 0x000098 */
106
107 /* 0x0000A0-0x0000AF -- Arbitration */
108 uint64_t p_arb; /* 0x0000A0 */
109 uint64_t _pad_0000A8; /* 0x0000A8 */
110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 uint64_t p_ate_parity_err; /* 0x0000B0 */
113 uint64_t _pad_0000B8; /* 0x0000B8 */
114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 uint64_t p_bus_timeout; /* 0x0000C0 */
117 uint64_t p_pci_cfg; /* 0x0000C8 */
118 uint64_t p_pci_err_upper; /* 0x0000D0 */
119 uint64_t p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower
121 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
122
123 /* 0x000100-0x0001FF -- Interrupt */
124 uint64_t p_int_status; /* 0x000100 */
125 uint64_t p_int_enable; /* 0x000108 */
126 uint64_t p_int_rst_stat; /* 0x000110 */
127 uint64_t p_int_mode; /* 0x000118 */
128 uint64_t p_int_device; /* 0x000120 */
129 uint64_t p_int_host_err; /* 0x000128 */
130 uint64_t p_int_addr[8]; /* 0x0001{30,,,68} */
131 uint64_t p_err_int_view; /* 0x000170 */
132 uint64_t p_mult_int; /* 0x000178 */
133 uint64_t p_force_always[8]; /* 0x0001{80,,,B8} */
134 uint64_t p_force_pin[8]; /* 0x0001{C0,,,F8} */
135
136 /* 0x000200-0x000298 -- Device */
137 uint64_t p_device[4]; /* 0x0002{00,,,18} */
138 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
139 uint64_t p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
141 uint64_t p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 uint64_t p_resp_status; /* 0x000290 */
145 uint64_t p_resp_clear; /* 0x000298 */
146
147 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct {
151 uint64_t upper; /* 0x0003{00,,,F0} */
152 uint64_t lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16];
154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct {
157 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
158 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
159 uint64_t inflight; /* 0x000{410,,,5D0} */
160 uint64_t prefetch; /* 0x000{418,,,5D8} */
161 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
162 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
163 uint64_t max_latency; /* 0x000{430,,,5F0} */
164 uint64_t clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8];
166
167
168 /* 0x000600-0x0009FF -- PCI/X registers */
169 uint64_t p_pcix_bus_err_addr; /* 0x000600 */
170 uint64_t p_pcix_bus_err_attr; /* 0x000608 */
171 uint64_t p_pcix_bus_err_data; /* 0x000610 */
172 uint64_t p_pcix_pio_split_addr; /* 0x000618 */
173 uint64_t p_pcix_pio_split_attr; /* 0x000620 */
174 uint64_t p_pcix_dma_req_err_attr; /* 0x000628 */
175 uint64_t p_pcix_dma_req_err_addr; /* 0x000630 */
176 uint64_t p_pcix_timeout; /* 0x000638 */
177
178 uint64_t _pad_000640[120]; /* 0x000{640,,,9F8} */
179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct {
182 uint64_t p_buf_addr; /* 0x000{A00,,,AF0} */
183 uint64_t p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16];
185
186 struct {
187 uint64_t p_buf_addr; /* 0x000{B00,,,BE0} */
188 uint64_t p_buf_attr; /* 0x000{B08,,,BE8} */
189 uint64_t p_buf_valid; /* 0x000{B10,,,BF0} */
190 uint64_t __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8];
192
193 /* End of Local Registers -- Start of Address Map space */
194
195 char _pad_000c00[0x010000 - 0x000c00];
196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 uint64_t p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 uint64_t p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202
203 char _pad_014000[0x18000 - 0x014000];
204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 uint64_t p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 uint64_t p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 uint64_t p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209
210 char _pad_019800[0x20000 - 0x019800];
211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union {
214 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union {
219 uint8_t c[0x100 / 1];
220 uint16_t s[0x100 / 2];
221 uint32_t l[0x100 / 4];
222 uint64_t d[0x100 / 8];
223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union {
228 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
229 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
230 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
231 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union {
233 uint8_t c[0x100 / 1];
234 uint16_t s[0x100 / 2];
235 uint32_t l[0x100 / 4];
236 uint64_t d[0x100 / 8];
237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */
239
240 char _pad_029000[0x030000-0x029000];
241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union {
244 uint8_t c[8 / 1];
245 uint16_t s[8 / 2];
246 uint32_t l[8 / 4];
247 uint64_t d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */
249
250 char _pad_030007[0x040000-0x030008];
251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union {
254 uint8_t c[8 / 1];
255 uint16_t s[8 / 2];
256 uint32_t l[8 / 4];
257 uint64_t d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */
259};
260
261#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/arch/ia64/sn/include/pci/tiocp.h b/arch/ia64/sn/include/pci/tiocp.h
new file mode 100644
index 000000000000..f07c83b2bf6e
--- /dev/null
+++ b/arch/ia64/sn/include/pci/tiocp.h
@@ -0,0 +1,256 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_TIOCP_H
9#define _ASM_IA64_SN_PCI_TIOCP_H
10
11#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
12#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
13
14
15/*****************************************************************************
16 *********************** TIOCP MMR structure mapping ***************************
17 *****************************************************************************/
18
19struct tiocp{
20
21 /* 0x000000-0x00FFFF -- Local Registers */
22
23 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
24 uint64_t cp_id; /* 0x000000 */
25 uint64_t cp_stat; /* 0x000008 */
26 uint64_t cp_err_upper; /* 0x000010 */
27 uint64_t cp_err_lower; /* 0x000018 */
28 #define cp_err cp_err_lower
29 uint64_t cp_control; /* 0x000020 */
30 uint64_t cp_req_timeout; /* 0x000028 */
31 uint64_t cp_intr_upper; /* 0x000030 */
32 uint64_t cp_intr_lower; /* 0x000038 */
33 #define cp_intr cp_intr_lower
34 uint64_t cp_err_cmdword; /* 0x000040 */
35 uint64_t _pad_000048; /* 0x000048 */
36 uint64_t cp_tflush; /* 0x000050 */
37
38 /* 0x000058-0x00007F -- Bridge-specific Configuration */
39 uint64_t cp_aux_err; /* 0x000058 */
40 uint64_t cp_resp_upper; /* 0x000060 */
41 uint64_t cp_resp_lower; /* 0x000068 */
42 #define cp_resp cp_resp_lower
43 uint64_t cp_tst_pin_ctrl; /* 0x000070 */
44 uint64_t cp_addr_lkerr; /* 0x000078 */
45
46 /* 0x000080-0x00008F -- PMU & MAP */
47 uint64_t cp_dir_map; /* 0x000080 */
48 uint64_t _pad_000088; /* 0x000088 */
49
50 /* 0x000090-0x00009F -- SSRAM */
51 uint64_t cp_map_fault; /* 0x000090 */
52 uint64_t _pad_000098; /* 0x000098 */
53
54 /* 0x0000A0-0x0000AF -- Arbitration */
55 uint64_t cp_arb; /* 0x0000A0 */
56 uint64_t _pad_0000A8; /* 0x0000A8 */
57
58 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
59 uint64_t cp_ate_parity_err; /* 0x0000B0 */
60 uint64_t _pad_0000B8; /* 0x0000B8 */
61
62 /* 0x0000C0-0x0000FF -- PCI/GIO */
63 uint64_t cp_bus_timeout; /* 0x0000C0 */
64 uint64_t cp_pci_cfg; /* 0x0000C8 */
65 uint64_t cp_pci_err_upper; /* 0x0000D0 */
66 uint64_t cp_pci_err_lower; /* 0x0000D8 */
67 #define cp_pci_err cp_pci_err_lower
68 uint64_t _pad_0000E0[4]; /* 0x0000{E0..F8} */
69
70 /* 0x000100-0x0001FF -- Interrupt */
71 uint64_t cp_int_status; /* 0x000100 */
72 uint64_t cp_int_enable; /* 0x000108 */
73 uint64_t cp_int_rst_stat; /* 0x000110 */
74 uint64_t cp_int_mode; /* 0x000118 */
75 uint64_t cp_int_device; /* 0x000120 */
76 uint64_t cp_int_host_err; /* 0x000128 */
77 uint64_t cp_int_addr[8]; /* 0x0001{30,,,68} */
78 uint64_t cp_err_int_view; /* 0x000170 */
79 uint64_t cp_mult_int; /* 0x000178 */
80 uint64_t cp_force_always[8]; /* 0x0001{80,,,B8} */
81 uint64_t cp_force_pin[8]; /* 0x0001{C0,,,F8} */
82
83 /* 0x000200-0x000298 -- Device */
84 uint64_t cp_device[4]; /* 0x0002{00,,,18} */
85 uint64_t _pad_000220[4]; /* 0x0002{20,,,38} */
86 uint64_t cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
87 uint64_t _pad_000260[4]; /* 0x0002{60,,,78} */
88 uint64_t cp_rrb_map[2]; /* 0x0002{80,,,88} */
89 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
90 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
91 uint64_t cp_resp_status; /* 0x000290 */
92 uint64_t cp_resp_clear; /* 0x000298 */
93
94 uint64_t _pad_0002A0[12]; /* 0x0002{A0..F8} */
95
96 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
97 struct {
98 uint64_t upper; /* 0x0003{00,,,F0} */
99 uint64_t lower; /* 0x0003{08,,,F8} */
100 } cp_buf_addr_match[16];
101
102 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
103 struct {
104 uint64_t flush_w_touch; /* 0x000{400,,,5C0} */
105 uint64_t flush_wo_touch; /* 0x000{408,,,5C8} */
106 uint64_t inflight; /* 0x000{410,,,5D0} */
107 uint64_t prefetch; /* 0x000{418,,,5D8} */
108 uint64_t total_pci_retry; /* 0x000{420,,,5E0} */
109 uint64_t max_pci_retry; /* 0x000{428,,,5E8} */
110 uint64_t max_latency; /* 0x000{430,,,5F0} */
111 uint64_t clear_all; /* 0x000{438,,,5F8} */
112 } cp_buf_count[8];
113
114
115 /* 0x000600-0x0009FF -- PCI/X registers */
116 uint64_t cp_pcix_bus_err_addr; /* 0x000600 */
117 uint64_t cp_pcix_bus_err_attr; /* 0x000608 */
118 uint64_t cp_pcix_bus_err_data; /* 0x000610 */
119 uint64_t cp_pcix_pio_split_addr; /* 0x000618 */
120 uint64_t cp_pcix_pio_split_attr; /* 0x000620 */
121 uint64_t cp_pcix_dma_req_err_attr; /* 0x000628 */
122 uint64_t cp_pcix_dma_req_err_addr; /* 0x000630 */
123 uint64_t cp_pcix_timeout; /* 0x000638 */
124
125 uint64_t _pad_000640[24]; /* 0x000{640,,,6F8} */
126
127 /* 0x000700-0x000737 -- Debug Registers */
128 uint64_t cp_ct_debug_ctl; /* 0x000700 */
129 uint64_t cp_br_debug_ctl; /* 0x000708 */
130 uint64_t cp_mux3_debug_ctl; /* 0x000710 */
131 uint64_t cp_mux4_debug_ctl; /* 0x000718 */
132 uint64_t cp_mux5_debug_ctl; /* 0x000720 */
133 uint64_t cp_mux6_debug_ctl; /* 0x000728 */
134 uint64_t cp_mux7_debug_ctl; /* 0x000730 */
135
136 uint64_t _pad_000738[89]; /* 0x000{738,,,9F8} */
137
138 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
139 struct {
140 uint64_t cp_buf_addr; /* 0x000{A00,,,AF0} */
141 uint64_t cp_buf_attr; /* 0X000{A08,,,AF8} */
142 } cp_pcix_read_buf_64[16];
143
144 struct {
145 uint64_t cp_buf_addr; /* 0x000{B00,,,BE0} */
146 uint64_t cp_buf_attr; /* 0x000{B08,,,BE8} */
147 uint64_t cp_buf_valid; /* 0x000{B10,,,BF0} */
148 uint64_t __pad1; /* 0x000{B18,,,BF8} */
149 } cp_pcix_write_buf_64[8];
150
151 /* End of Local Registers -- Start of Address Map space */
152
153 char _pad_000c00[0x010000 - 0x000c00];
154
155 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
156 uint64_t cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
157
158 char _pad_012000[0x14000 - 0x012000];
159
160 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
161 uint64_t cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
162
163 char _pad_016000[0x18000 - 0x016000];
164
165 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
166 uint64_t cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
167 uint64_t cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
168 uint64_t cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
169
170 char _pad_019800[0x1C000 - 0x019800];
171
172 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
173 uint64_t cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
174 uint64_t cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
175 uint64_t cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
176
177 char _pad_01F000[0x20000 - 0x01F000];
178
179 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
180 char _pad_020000[0x021000 - 0x20000];
181
182 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
183 union {
184 uint8_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
185 uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
186 uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
187 uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
188 union {
189 uint8_t c[0x100 / 1];
190 uint16_t s[0x100 / 2];
191 uint32_t l[0x100 / 4];
192 uint64_t d[0x100 / 8];
193 } f[8];
194 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
195
196 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
197 union {
198 uint8_t c[0x1000 / 1]; /* 0x028000-0x029000 */
199 uint16_t s[0x1000 / 2]; /* 0x028000-0x029000 */
200 uint32_t l[0x1000 / 4]; /* 0x028000-0x029000 */
201 uint64_t d[0x1000 / 8]; /* 0x028000-0x029000 */
202 union {
203 uint8_t c[0x100 / 1];
204 uint16_t s[0x100 / 2];
205 uint32_t l[0x100 / 4];
206 uint64_t d[0x100 / 8];
207 } f[8];
208 } cp_type1_cfg; /* 0x028000-0x029000 */
209
210 char _pad_029000[0x030000-0x029000];
211
212 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
213 union {
214 uint8_t c[8 / 1];
215 uint16_t s[8 / 2];
216 uint32_t l[8 / 4];
217 uint64_t d[8 / 8];
218 } cp_pci_iack; /* 0x030000-0x030007 */
219
220 char _pad_030007[0x040000-0x030008];
221
222 /* 0x040000-0x040007 -- PCIX Special Cycle */
223 union {
224 uint8_t c[8 / 1];
225 uint16_t s[8 / 2];
226 uint32_t l[8 / 4];
227 uint64_t d[8 / 8];
228 } cp_pcix_cycle; /* 0x040000-0x040007 */
229
230 char _pad_040007[0x200000-0x040008];
231
232 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
233 union {
234 uint8_t c[0x100000 / 1];
235 uint16_t s[0x100000 / 2];
236 uint32_t l[0x100000 / 4];
237 uint64_t d[0x100000 / 8];
238 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
239
240 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
241
242 char _pad_800000[0xA00000-0x800000];
243
244 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
245 union {
246 uint8_t c[0x100000 / 1];
247 uint16_t s[0x100000 / 2];
248 uint32_t l[0x100000 / 4];
249 uint64_t d[0x100000 / 8];
250 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
251
252 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
253
254};
255
256#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/arch/ia64/sn/include/tio.h b/arch/ia64/sn/include/tio.h
new file mode 100644
index 000000000000..0139124dd54a
--- /dev/null
+++ b/arch/ia64/sn/include/tio.h
@@ -0,0 +1,37 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_H
10#define _ASM_IA64_SN_TIO_H
11
12#define TIO_MMR_ADDR_MOD
13
14#define TIO_NODE_ID TIO_MMR_ADDR_MOD(0x0000000090060e80)
15
16#define TIO_ITTE_BASE 0xb0008800 /* base of translation table entries */
17#define TIO_ITTE(bigwin) (TIO_ITTE_BASE + 8*(bigwin))
18
19#define TIO_ITTE_OFFSET_BITS 8 /* size of offset field */
20#define TIO_ITTE_OFFSET_MASK ((1<<TIO_ITTE_OFFSET_BITS)-1)
21#define TIO_ITTE_OFFSET_SHIFT 0
22
23#define TIO_ITTE_WIDGET_BITS 2 /* size of widget field */
24#define TIO_ITTE_WIDGET_MASK ((1<<TIO_ITTE_WIDGET_BITS)-1)
25#define TIO_ITTE_WIDGET_SHIFT 12
26#define TIO_ITTE_VALID_MASK 0x1
27#define TIO_ITTE_VALID_SHIFT 16
28
29
30#define TIO_ITTE_PUT(nasid, bigwin, widget, addr, valid) \
31 REMOTE_HUB_S((nasid), TIO_ITTE(bigwin), \
32 (((((addr) >> TIO_BWIN_SIZE_BITS) & \
33 TIO_ITTE_OFFSET_MASK) << TIO_ITTE_OFFSET_SHIFT) | \
34 (((widget) & TIO_ITTE_WIDGET_MASK) << TIO_ITTE_WIDGET_SHIFT)) | \
35 (( (valid) & TIO_ITTE_VALID_MASK) << TIO_ITTE_VALID_SHIFT))
36
37#endif /* _ASM_IA64_SN_TIO_H */
diff --git a/arch/ia64/sn/include/xtalk/hubdev.h b/arch/ia64/sn/include/xtalk/hubdev.h
new file mode 100644
index 000000000000..868e7ecae84b
--- /dev/null
+++ b/arch/ia64/sn/include/xtalk/hubdev.h
@@ -0,0 +1,67 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_XTALK_HUBDEV_H
9#define _ASM_IA64_SN_XTALK_HUBDEV_H
10
11#define HUB_WIDGET_ID_MAX 0xf
12#define DEV_PER_WIDGET (2*2*8)
13#define IIO_ITTE_WIDGET_BITS 4 /* size of widget field */
14#define IIO_ITTE_WIDGET_MASK ((1<<IIO_ITTE_WIDGET_BITS)-1)
15#define IIO_ITTE_WIDGET_SHIFT 8
16
17/*
18 * Use the top big window as a surrogate for the first small window
19 */
20#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
21#define IIO_NUM_ITTES 7
22#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
23
24struct sn_flush_device_list {
25 int sfdl_bus;
26 int sfdl_slot;
27 int sfdl_pin;
28 struct bar_list {
29 unsigned long start;
30 unsigned long end;
31 } sfdl_bar_list[6];
32 unsigned long sfdl_force_int_addr;
33 unsigned long sfdl_flush_value;
34 volatile unsigned long *sfdl_flush_addr;
35 uint64_t sfdl_persistent_busnum;
36 struct pcibus_info *sfdl_pcibus_info;
37 spinlock_t sfdl_flush_lock;
38};
39
40/*
41 * **widget_p - Used as an array[wid_num][device] of sn_flush_device_list.
42 */
43struct sn_flush_nasid_entry {
44 struct sn_flush_device_list **widget_p; /* Used as a array of wid_num */
45 uint64_t iio_itte[8];
46};
47
48struct hubdev_info {
49 geoid_t hdi_geoid;
50 short hdi_nasid;
51 short hdi_peer_nasid; /* Dual Porting Peer */
52
53 struct sn_flush_nasid_entry hdi_flush_nasid_list;
54 struct xwidget_info hdi_xwidget_info[HUB_WIDGET_ID_MAX + 1];
55
56
57 void *hdi_nodepda;
58 void *hdi_node_vertex;
59 void *hdi_xtalk_vertex;
60};
61
62extern void hubdev_init_node(nodepda_t *, cnodeid_t);
63extern void hub_error_init(struct hubdev_info *);
64extern void ice_error_init(struct hubdev_info *);
65
66
67#endif /* _ASM_IA64_SN_XTALK_HUBDEV_H */
diff --git a/arch/ia64/sn/include/xtalk/xbow.h b/arch/ia64/sn/include/xtalk/xbow.h
new file mode 100644
index 000000000000..ec56b3432f17
--- /dev/null
+++ b/arch/ia64/sn/include/xtalk/xbow.h
@@ -0,0 +1,291 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_XTALK_XBOW_H
9#define _ASM_IA64_SN_XTALK_XBOW_H
10
11#define XBOW_PORT_8 0x8
12#define XBOW_PORT_C 0xc
13#define XBOW_PORT_F 0xf
14
15#define MAX_XBOW_PORTS 8 /* number of ports on xbow chip */
16#define BASE_XBOW_PORT XBOW_PORT_8 /* Lowest external port */
17
18#define XBOW_CREDIT 4
19
20#define MAX_XBOW_NAME 16
21
22/* Register set for each xbow link */
23typedef volatile struct xb_linkregs_s {
24/*
25 * we access these through synergy unswizzled space, so the address
26 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
27 * That's why we put the register first and filler second.
28 */
29 uint32_t link_ibf;
30 uint32_t filler0; /* filler for proper alignment */
31 uint32_t link_control;
32 uint32_t filler1;
33 uint32_t link_status;
34 uint32_t filler2;
35 uint32_t link_arb_upper;
36 uint32_t filler3;
37 uint32_t link_arb_lower;
38 uint32_t filler4;
39 uint32_t link_status_clr;
40 uint32_t filler5;
41 uint32_t link_reset;
42 uint32_t filler6;
43 uint32_t link_aux_status;
44 uint32_t filler7;
45} xb_linkregs_t;
46
47typedef volatile struct xbow_s {
48 /* standard widget configuration 0x000000-0x000057 */
49 struct widget_cfg xb_widget; /* 0x000000 */
50
51 /* helper fieldnames for accessing bridge widget */
52
53#define xb_wid_id xb_widget.w_id
54#define xb_wid_stat xb_widget.w_status
55#define xb_wid_err_upper xb_widget.w_err_upper_addr
56#define xb_wid_err_lower xb_widget.w_err_lower_addr
57#define xb_wid_control xb_widget.w_control
58#define xb_wid_req_timeout xb_widget.w_req_timeout
59#define xb_wid_int_upper xb_widget.w_intdest_upper_addr
60#define xb_wid_int_lower xb_widget.w_intdest_lower_addr
61#define xb_wid_err_cmdword xb_widget.w_err_cmd_word
62#define xb_wid_llp xb_widget.w_llp_cfg
63#define xb_wid_stat_clr xb_widget.w_tflush
64
65/*
66 * we access these through synergy unswizzled space, so the address
67 * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
68 * That's why we put the register first and filler second.
69 */
70 /* xbow-specific widget configuration 0x000058-0x0000FF */
71 uint32_t xb_wid_arb_reload; /* 0x00005C */
72 uint32_t _pad_000058;
73 uint32_t xb_perf_ctr_a; /* 0x000064 */
74 uint32_t _pad_000060;
75 uint32_t xb_perf_ctr_b; /* 0x00006c */
76 uint32_t _pad_000068;
77 uint32_t xb_nic; /* 0x000074 */
78 uint32_t _pad_000070;
79
80 /* Xbridge only */
81 uint32_t xb_w0_rst_fnc; /* 0x00007C */
82 uint32_t _pad_000078;
83 uint32_t xb_l8_rst_fnc; /* 0x000084 */
84 uint32_t _pad_000080;
85 uint32_t xb_l9_rst_fnc; /* 0x00008c */
86 uint32_t _pad_000088;
87 uint32_t xb_la_rst_fnc; /* 0x000094 */
88 uint32_t _pad_000090;
89 uint32_t xb_lb_rst_fnc; /* 0x00009c */
90 uint32_t _pad_000098;
91 uint32_t xb_lc_rst_fnc; /* 0x0000a4 */
92 uint32_t _pad_0000a0;
93 uint32_t xb_ld_rst_fnc; /* 0x0000ac */
94 uint32_t _pad_0000a8;
95 uint32_t xb_le_rst_fnc; /* 0x0000b4 */
96 uint32_t _pad_0000b0;
97 uint32_t xb_lf_rst_fnc; /* 0x0000bc */
98 uint32_t _pad_0000b8;
99 uint32_t xb_lock; /* 0x0000c4 */
100 uint32_t _pad_0000c0;
101 uint32_t xb_lock_clr; /* 0x0000cc */
102 uint32_t _pad_0000c8;
103 /* end of Xbridge only */
104 uint32_t _pad_0000d0[12];
105
106 /* Link Specific Registers, port 8..15 0x000100-0x000300 */
107 xb_linkregs_t xb_link_raw[MAX_XBOW_PORTS];
108#define xb_link(p) xb_link_raw[(p) & (MAX_XBOW_PORTS - 1)]
109
110} xbow_t;
111
112#define XB_FLAGS_EXISTS 0x1 /* device exists */
113#define XB_FLAGS_MASTER 0x2
114#define XB_FLAGS_SLAVE 0x0
115#define XB_FLAGS_GBR 0x4
116#define XB_FLAGS_16BIT 0x8
117#define XB_FLAGS_8BIT 0x0
118
119/* is widget port number valid? (based on version 7.0 of xbow spec) */
120#define XBOW_WIDGET_IS_VALID(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_F)
121
122/* whether to use upper or lower arbitration register, given source widget id */
123#define XBOW_ARB_IS_UPPER(wid) ((wid) >= XBOW_PORT_8 && (wid) <= XBOW_PORT_B)
124#define XBOW_ARB_IS_LOWER(wid) ((wid) >= XBOW_PORT_C && (wid) <= XBOW_PORT_F)
125
126/* offset of arbitration register, given source widget id */
127#define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
128
129#define XBOW_WID_ID WIDGET_ID
130#define XBOW_WID_STAT WIDGET_STATUS
131#define XBOW_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
132#define XBOW_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
133#define XBOW_WID_CONTROL WIDGET_CONTROL
134#define XBOW_WID_REQ_TO WIDGET_REQ_TIMEOUT
135#define XBOW_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
136#define XBOW_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
137#define XBOW_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
138#define XBOW_WID_LLP WIDGET_LLP_CFG
139#define XBOW_WID_STAT_CLR WIDGET_TFLUSH
140#define XBOW_WID_ARB_RELOAD 0x5c
141#define XBOW_WID_PERF_CTR_A 0x64
142#define XBOW_WID_PERF_CTR_B 0x6c
143#define XBOW_WID_NIC 0x74
144
145/* Xbridge only */
146#define XBOW_W0_RST_FNC 0x00007C
147#define XBOW_L8_RST_FNC 0x000084
148#define XBOW_L9_RST_FNC 0x00008c
149#define XBOW_LA_RST_FNC 0x000094
150#define XBOW_LB_RST_FNC 0x00009c
151#define XBOW_LC_RST_FNC 0x0000a4
152#define XBOW_LD_RST_FNC 0x0000ac
153#define XBOW_LE_RST_FNC 0x0000b4
154#define XBOW_LF_RST_FNC 0x0000bc
155#define XBOW_RESET_FENCE(x) ((x) > 7 && (x) < 16) ? \
156 (XBOW_W0_RST_FNC + ((x) - 7) * 8) : \
157 ((x) == 0) ? XBOW_W0_RST_FNC : 0
158#define XBOW_LOCK 0x0000c4
159#define XBOW_LOCK_CLR 0x0000cc
160/* End of Xbridge only */
161
162/* used only in ide, but defined here within the reserved portion */
163/* of the widget0 address space (before 0xf4) */
164#define XBOW_WID_UNDEF 0xe4
165
166/* xbow link register set base, legal value for x is 0x8..0xf */
167#define XB_LINK_BASE 0x100
168#define XB_LINK_OFFSET 0x40
169#define XB_LINK_REG_BASE(x) (XB_LINK_BASE + ((x) & (MAX_XBOW_PORTS - 1)) * XB_LINK_OFFSET)
170
171#define XB_LINK_IBUF_FLUSH(x) (XB_LINK_REG_BASE(x) + 0x4)
172#define XB_LINK_CTRL(x) (XB_LINK_REG_BASE(x) + 0xc)
173#define XB_LINK_STATUS(x) (XB_LINK_REG_BASE(x) + 0x14)
174#define XB_LINK_ARB_UPPER(x) (XB_LINK_REG_BASE(x) + 0x1c)
175#define XB_LINK_ARB_LOWER(x) (XB_LINK_REG_BASE(x) + 0x24)
176#define XB_LINK_STATUS_CLR(x) (XB_LINK_REG_BASE(x) + 0x2c)
177#define XB_LINK_RESET(x) (XB_LINK_REG_BASE(x) + 0x34)
178#define XB_LINK_AUX_STATUS(x) (XB_LINK_REG_BASE(x) + 0x3c)
179
180/* link_control(x) */
181#define XB_CTRL_LINKALIVE_IE 0x80000000 /* link comes alive */
182 /* reserved: 0x40000000 */
183#define XB_CTRL_PERF_CTR_MODE_MSK 0x30000000 /* perf counter mode */
184#define XB_CTRL_IBUF_LEVEL_MSK 0x0e000000 /* input packet buffer level */
185#define XB_CTRL_8BIT_MODE 0x01000000 /* force link into 8 bit mode */
186#define XB_CTRL_BAD_LLP_PKT 0x00800000 /* force bad LLP packet */
187#define XB_CTRL_WIDGET_CR_MSK 0x007c0000 /* LLP widget credit mask */
188#define XB_CTRL_WIDGET_CR_SHFT 18 /* LLP widget credit shift */
189#define XB_CTRL_ILLEGAL_DST_IE 0x00020000 /* illegal destination */
190#define XB_CTRL_OALLOC_IBUF_IE 0x00010000 /* overallocated input buffer */
191 /* reserved: 0x0000fe00 */
192#define XB_CTRL_BNDWDTH_ALLOC_IE 0x00000100 /* bandwidth alloc */
193#define XB_CTRL_RCV_CNT_OFLOW_IE 0x00000080 /* rcv retry overflow */
194#define XB_CTRL_XMT_CNT_OFLOW_IE 0x00000040 /* xmt retry overflow */
195#define XB_CTRL_XMT_MAX_RTRY_IE 0x00000020 /* max transmit retry */
196#define XB_CTRL_RCV_IE 0x00000010 /* receive */
197#define XB_CTRL_XMT_RTRY_IE 0x00000008 /* transmit retry */
198 /* reserved: 0x00000004 */
199#define XB_CTRL_MAXREQ_TOUT_IE 0x00000002 /* maximum request timeout */
200#define XB_CTRL_SRC_TOUT_IE 0x00000001 /* source timeout */
201
202/* link_status(x) */
203#define XB_STAT_LINKALIVE XB_CTRL_LINKALIVE_IE
204 /* reserved: 0x7ff80000 */
205#define XB_STAT_MULTI_ERR 0x00040000 /* multi error */
206#define XB_STAT_ILLEGAL_DST_ERR XB_CTRL_ILLEGAL_DST_IE
207#define XB_STAT_OALLOC_IBUF_ERR XB_CTRL_OALLOC_IBUF_IE
208#define XB_STAT_BNDWDTH_ALLOC_ID_MSK 0x0000ff00 /* port bitmask */
209#define XB_STAT_RCV_CNT_OFLOW_ERR XB_CTRL_RCV_CNT_OFLOW_IE
210#define XB_STAT_XMT_CNT_OFLOW_ERR XB_CTRL_XMT_CNT_OFLOW_IE
211#define XB_STAT_XMT_MAX_RTRY_ERR XB_CTRL_XMT_MAX_RTRY_IE
212#define XB_STAT_RCV_ERR XB_CTRL_RCV_IE
213#define XB_STAT_XMT_RTRY_ERR XB_CTRL_XMT_RTRY_IE
214 /* reserved: 0x00000004 */
215#define XB_STAT_MAXREQ_TOUT_ERR XB_CTRL_MAXREQ_TOUT_IE
216#define XB_STAT_SRC_TOUT_ERR XB_CTRL_SRC_TOUT_IE
217
218/* link_aux_status(x) */
219#define XB_AUX_STAT_RCV_CNT 0xff000000
220#define XB_AUX_STAT_XMT_CNT 0x00ff0000
221#define XB_AUX_STAT_TOUT_DST 0x0000ff00
222#define XB_AUX_LINKFAIL_RST_BAD 0x00000040
223#define XB_AUX_STAT_PRESENT 0x00000020
224#define XB_AUX_STAT_PORT_WIDTH 0x00000010
225 /* reserved: 0x0000000f */
226
227/*
228 * link_arb_upper/link_arb_lower(x), (reg) should be the link_arb_upper
229 * register if (x) is 0x8..0xb, link_arb_lower if (x) is 0xc..0xf
230 */
231#define XB_ARB_GBR_MSK 0x1f
232#define XB_ARB_RR_MSK 0x7
233#define XB_ARB_GBR_SHFT(x) (((x) & 0x3) * 8)
234#define XB_ARB_RR_SHFT(x) (((x) & 0x3) * 8 + 5)
235#define XB_ARB_GBR_CNT(reg,x) ((reg) >> XB_ARB_GBR_SHFT(x) & XB_ARB_GBR_MSK)
236#define XB_ARB_RR_CNT(reg,x) ((reg) >> XB_ARB_RR_SHFT(x) & XB_ARB_RR_MSK)
237
238/* XBOW_WID_STAT */
239#define XB_WID_STAT_LINK_INTR_SHFT (24)
240#define XB_WID_STAT_LINK_INTR_MASK (0xFF << XB_WID_STAT_LINK_INTR_SHFT)
241#define XB_WID_STAT_LINK_INTR(x) (0x1 << (((x)&7) + XB_WID_STAT_LINK_INTR_SHFT))
242#define XB_WID_STAT_WIDGET0_INTR 0x00800000
243#define XB_WID_STAT_SRCID_MASK 0x000003c0 /* Xbridge only */
244#define XB_WID_STAT_REG_ACC_ERR 0x00000020
245#define XB_WID_STAT_RECV_TOUT 0x00000010 /* Xbridge only */
246#define XB_WID_STAT_ARB_TOUT 0x00000008 /* Xbridge only */
247#define XB_WID_STAT_XTALK_ERR 0x00000004
248#define XB_WID_STAT_DST_TOUT 0x00000002 /* Xbridge only */
249#define XB_WID_STAT_MULTI_ERR 0x00000001
250
251#define XB_WID_STAT_SRCID_SHFT 6
252
253/* XBOW_WID_CONTROL */
254#define XB_WID_CTRL_REG_ACC_IE XB_WID_STAT_REG_ACC_ERR
255#define XB_WID_CTRL_RECV_TOUT XB_WID_STAT_RECV_TOUT
256#define XB_WID_CTRL_ARB_TOUT XB_WID_STAT_ARB_TOUT
257#define XB_WID_CTRL_XTALK_IE XB_WID_STAT_XTALK_ERR
258
259/* XBOW_WID_INT_UPPER */
260/* defined in xwidget.h for WIDGET_INTDEST_UPPER_ADDR */
261
262/* XBOW WIDGET part number, in the ID register */
263#define XBOW_WIDGET_PART_NUM 0x0 /* crossbow */
264#define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
265#define XBOW_WIDGET_MFGR_NUM 0x0
266#define XXBOW_WIDGET_MFGR_NUM 0x0
267#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */
268
269#define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */
270#define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */
271#define XBOW_REV_1_2 0x3 /* xbow rev 1.2 is "3" */
272#define XBOW_REV_1_3 0x4 /* xbow rev 1.3 is "4" */
273#define XBOW_REV_2_0 0x5 /* xbow rev 2.0 is "5" */
274
275#define XXBOW_PART_REV_1_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x1 )
276#define XXBOW_PART_REV_2_0 (XXBOW_WIDGET_PART_NUM << 4 | 0x2 )
277
278/* XBOW_WID_ARB_RELOAD */
279#define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */
280
281#define IS_XBRIDGE_XBOW(wid) \
282 (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \
283 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
284
285#define IS_PIC_XBOW(wid) \
286 (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \
287 XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM)
288
289#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv)
290
291#endif /* _ASM_IA64_SN_XTALK_XBOW_H */
diff --git a/arch/ia64/sn/include/xtalk/xwidgetdev.h b/arch/ia64/sn/include/xtalk/xwidgetdev.h
new file mode 100644
index 000000000000..c5f4bc5cc033
--- /dev/null
+++ b/arch/ia64/sn/include/xtalk/xwidgetdev.h
@@ -0,0 +1,70 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_XTALK_XWIDGET_H
9#define _ASM_IA64_SN_XTALK_XWIDGET_H
10
11/* WIDGET_ID */
12#define WIDGET_REV_NUM 0xf0000000
13#define WIDGET_PART_NUM 0x0ffff000
14#define WIDGET_MFG_NUM 0x00000ffe
15#define WIDGET_REV_NUM_SHFT 28
16#define WIDGET_PART_NUM_SHFT 12
17#define WIDGET_MFG_NUM_SHFT 1
18
19#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
20#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
21#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
22#define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \
23 XWIDGET_REV_NUM(widgetid))
24#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf)
25
26/* widget configuration registers */
27struct widget_cfg{
28 uint32_t w_id; /* 0x04 */
29 uint32_t w_pad_0; /* 0x00 */
30 uint32_t w_status; /* 0x0c */
31 uint32_t w_pad_1; /* 0x08 */
32 uint32_t w_err_upper_addr; /* 0x14 */
33 uint32_t w_pad_2; /* 0x10 */
34 uint32_t w_err_lower_addr; /* 0x1c */
35 uint32_t w_pad_3; /* 0x18 */
36 uint32_t w_control; /* 0x24 */
37 uint32_t w_pad_4; /* 0x20 */
38 uint32_t w_req_timeout; /* 0x2c */
39 uint32_t w_pad_5; /* 0x28 */
40 uint32_t w_intdest_upper_addr; /* 0x34 */
41 uint32_t w_pad_6; /* 0x30 */
42 uint32_t w_intdest_lower_addr; /* 0x3c */
43 uint32_t w_pad_7; /* 0x38 */
44 uint32_t w_err_cmd_word; /* 0x44 */
45 uint32_t w_pad_8; /* 0x40 */
46 uint32_t w_llp_cfg; /* 0x4c */
47 uint32_t w_pad_9; /* 0x48 */
48 uint32_t w_tflush; /* 0x54 */
49 uint32_t w_pad_10; /* 0x50 */
50};
51
52/*
53 * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
54 */
55struct xwidget_hwid{
56 int mfg_num;
57 int rev_num;
58 int part_num;
59};
60
61struct xwidget_info{
62
63 struct xwidget_hwid xwi_hwid; /* Widget Identification */
64 char xwi_masterxid; /* Hub's Widget Port Number */
65 void *xwi_hubinfo; /* Hub's provider private info */
66 uint64_t *xwi_hub_provider; /* prom provider functions */
67 void *xwi_vertex;
68};
69
70#endif /* _ASM_IA64_SN_XTALK_XWIDGET_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 16:21:04 -0500