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authorMatthew Wilcox <matthew@wil.cx>2009-10-12 10:24:30 -0400
committerTony Luck <tony.luck@intel.com>2009-10-13 13:44:42 -0400
commitadcd740341dbd58eb94a8c2885c171ce9eb8677c (patch)
tree99cbbea95dc9864b3d39e12180ad8dcdeeabc04c /arch/ia64/pci
parentdec1798f81f7e8a299734bdc29197ae77bf08018 (diff)
[IA64] Require SAL 3.2 in order to do extended config space ops
We had assumed that SAL firmware would return an error if it didn't understand extended config space. Unfortunately, the SAL on the SGI 750 doesn't do that, it panics the machine. So, condition the extended PCI config space accesses on SAL revision 3.2. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Tested-by: Brad Spengler <spender@grsecurity.net> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/pci')
-rw-r--r--arch/ia64/pci/pci.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 7de76dd352fe..c0fca2c1c858 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -56,10 +56,13 @@ int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
56 if ((seg | reg) <= 255) { 56 if ((seg | reg) <= 255) {
57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 57 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
58 mode = 0; 58 mode = 0;
59 } else { 59 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 60 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
61 mode = 1; 61 mode = 1;
62 } else {
63 return -EINVAL;
62 } 64 }
65
63 result = ia64_sal_pci_config_read(addr, mode, len, &data); 66 result = ia64_sal_pci_config_read(addr, mode, len, &data);
64 if (result != 0) 67 if (result != 0)
65 return -EINVAL; 68 return -EINVAL;
@@ -80,9 +83,11 @@ int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
80 if ((seg | reg) <= 255) { 83 if ((seg | reg) <= 255) {
81 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); 84 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
82 mode = 0; 85 mode = 0;
83 } else { 86 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
84 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); 87 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
85 mode = 1; 88 mode = 1;
89 } else {
90 return -EINVAL;
86 } 91 }
87 result = ia64_sal_pci_config_write(addr, mode, len, value); 92 result = ia64_sal_pci_config_write(addr, mode, len, value);
88 if (result != 0) 93 if (result != 0)