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authorJames Bottomley <jejb@titanic.(none)>2005-05-20 16:27:44 -0400
committerJames Bottomley <jejb@titanic.(none)>2005-05-20 16:27:44 -0400
commitad34ea2cc3845ef4dcd7d12fb0fa8484734bd672 (patch)
treead434400f5ecaa33b433c8f830e40792d8d6c05c /arch/ia64/mm/fault.c
parent90356ac3194bf91a441a5f9c3067af386ef62462 (diff)
parent88d7bd8cb9eb8d64bf7997600b0d64f7834047c5 (diff)
merge by hand - fix up rejections in Documentation/DocBook/Makefile
Diffstat (limited to 'arch/ia64/mm/fault.c')
-rw-r--r--arch/ia64/mm/fault.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c
index da859125aaef..4174ec999dde 100644
--- a/arch/ia64/mm/fault.c
+++ b/arch/ia64/mm/fault.c
@@ -209,10 +209,13 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
209 } 209 }
210 210
211 no_context: 211 no_context:
212 if (isr & IA64_ISR_SP) { 212 if ((isr & IA64_ISR_SP)
213 || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH))
214 {
213 /* 215 /*
214 * This fault was due to a speculative load set the "ed" bit in the psr to 216 * This fault was due to a speculative load or lfetch.fault, set the "ed"
215 * ensure forward progress (target register will get a NaT). 217 * bit in the psr to ensure forward progress. (Target register will get a
218 * NaT for ld.s, lfetch will be canceled.)
216 */ 219 */
217 ia64_psr(regs)->ed = 1; 220 ia64_psr(regs)->ed = 1;
218 return; 221 return;