[IA64] improve flush_icache_range()

Check with PAL to see what the i-cache line size is for
each level of the cache, and so use the correct stride
when flushing the cache.

Acked-by: David Mosberger
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 34 insertions, 12 deletions

diff --git a/arch/ia64/lib/flush.S b/arch/ia64/lib/flush.S
index a1af9146cfdb..3e2cfa2c6d39 100644
--- a/arch/ia64/lib/flush.S
+++ b/arch/ia64/lib/flush.S
@@ -3,37 +3,59 @@
  *
  * Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
  *      David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * 05/28/05 Zoltan Menyhart     Dynamic stride size
  */
+
 #include <asm/asmmacro.h>
-#include <asm/page.h>
+
 
         /*
          * flush_icache_range(start,end)
-         *      Must flush range from start to end-1 but nothing else (need to
+         *
+         *      Make i-cache(s) coherent with d-caches.
+         *
+         *      Must deal with range from start to end-1 but nothing else (need to
          *      be careful not to touch addresses that may be unmapped).
+         *
+         *      Note: "in0" and "in1" are preserved for debugging purposes.
          */
 GLOBAL_ENTRY(flush_icache_range)
+
         .prologue
-        alloc r2=ar.pfs,2,0,0,0
-        sub r8=in1,in0,1
+        alloc   r2=ar.pfs,2,0,0,0
+        movl    r3=ia64_i_cache_stride_shift
+        mov     r21=1
+        ;;
+        ld8     r20=[r3]                // r20: stride shift
+        sub     r22=in1,r0,1            // last byte address
         ;;
-        shr.u r8=r8,5                   // we flush 32 bytes per iteration
-        .save ar.lc, r3
-        mov r3=ar.lc                    // save ar.lc
+        shr.u   r23=in0,r20             // start / (stride size)
+        shr.u   r22=r22,r20             // (last byte address) / (stride size)
+        shl     r21=r21,r20             // r21: stride size of the i-cache(s)
+        ;;
+        sub     r8=r22,r23              // number of strides - 1
+        shl     r24=r23,r20             // r24: addresses for "fc.i" =
+                                        //      "start" rounded down to stride boundary
+        .save   ar.lc,r3
+        mov     r3=ar.lc                // save ar.lc
         ;;
 
         .body
-
-        mov ar.lc=r8
+        mov     ar.lc=r8
         ;;
-.Loop:  fc.i in0                        // issuable on M2 only
-        add in0=32,in0
+        /*
+         * 32 byte aligned loop, even number of (actually 2) bundles
+         */
+.Loop:  fc.i    r24                     // issuable on M0 only
+        add     r24=r21,r24             // we flush "stride size" bytes per iteration
+        nop.i   0
         br.cloop.sptk.few .Loop
         ;;
         sync.i
         ;;
         srlz.i
         ;;
-        mov ar.lc=r3                    // restore ar.lc
+        mov     ar.lc=r3                // restore ar.lc
         br.ret.sptk.many rp
 END(flush_icache_range)