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authorTony Luck <tony.luck@intel.com>2005-10-28 17:33:50 -0400
committerTony Luck <tony.luck@intel.com>2005-10-28 17:33:50 -0400
commit9acd3fa2e10f4e5b093ddf93af8f23cc9bdbd621 (patch)
treefefb8d52a8ef074d59f2b342d18b4372dde8952c /arch/ia64/kernel
parent5a2b1722e1051b84485a77006abe9b929aedef32 (diff)
parent9c184a073bfd650cc791956d6ca79725bb682716 (diff)
Pull asm-slot-fix into release branch
Diffstat (limited to 'arch/ia64/kernel')
-rw-r--r--arch/ia64/kernel/patch.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/ia64/kernel/patch.c b/arch/ia64/kernel/patch.c
index 367804a605fa..6a4ac7d70b35 100644
--- a/arch/ia64/kernel/patch.c
+++ b/arch/ia64/kernel/patch.c
@@ -64,22 +64,30 @@ ia64_patch (u64 insn_addr, u64 mask, u64 val)
64void 64void
65ia64_patch_imm64 (u64 insn_addr, u64 val) 65ia64_patch_imm64 (u64 insn_addr, u64 val)
66{ 66{
67 ia64_patch(insn_addr, 67 /* The assembler may generate offset pointing to either slot 1
68 or slot 2 for a long (2-slot) instruction, occupying slots 1
69 and 2. */
70 insn_addr &= -16UL;
71 ia64_patch(insn_addr + 2,
68 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ 72 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
69 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ 73 | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
70 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ 74 | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
71 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ 75 | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
72 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)); 76 | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */));
73 ia64_patch(insn_addr - 1, 0x1ffffffffffUL, val >> 22); 77 ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
74} 78}
75 79
76void 80void
77ia64_patch_imm60 (u64 insn_addr, u64 val) 81ia64_patch_imm60 (u64 insn_addr, u64 val)
78{ 82{
79 ia64_patch(insn_addr, 83 /* The assembler may generate offset pointing to either slot 1
84 or slot 2 for a long (2-slot) instruction, occupying slots 1
85 and 2. */
86 insn_addr &= -16UL;
87 ia64_patch(insn_addr + 2,
80 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ 88 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
81 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); 89 | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
82 ia64_patch(insn_addr - 1, 0x1fffffffffcUL, val >> 18); 90 ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18);
83} 91}
84 92
85/* 93/*