diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-17 14:31:57 -0400 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-07-17 14:31:57 -0400 |
commit | 492559af235eb56884d62553f191c0b5c4def990 (patch) | |
tree | a5dfa19243b3b8b976e9f5b9c788cafcd3ad80c7 /arch/ia64/kernel | |
parent | d3676756968eef4a31da11be5addc4eec1b6db2c (diff) | |
parent | 4f8de2745629330d78776282ea490fece22ee5e4 (diff) |
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
[IA64] Clean away some code inside some non-existent CONFIG ifdefs
[IA64] ar.itc access must really be after xtime_lock.sequence has been read
[IA64] correctly count CPU objects in the ia64/sn hwperf interface
[IA64] arbitary speed tty ioctl support
[IA64] use machvec=dig on hpzx1 platforms
Diffstat (limited to 'arch/ia64/kernel')
-rw-r--r-- | arch/ia64/kernel/fsys.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S index 8589e84a27c6..3f926c2dc708 100644 --- a/arch/ia64/kernel/fsys.S +++ b/arch/ia64/kernel/fsys.S | |||
@@ -247,6 +247,9 @@ ENTRY(fsys_gettimeofday) | |||
247 | .time_redo: | 247 | .time_redo: |
248 | .pred.rel.mutex p8,p9,p10 | 248 | .pred.rel.mutex p8,p9,p10 |
249 | ld4.acq r28 = [r29] // xtime_lock.sequence. Must come first for locking purposes | 249 | ld4.acq r28 = [r29] // xtime_lock.sequence. Must come first for locking purposes |
250 | ;; | ||
251 | and r28 = ~1,r28 // Make sequence even to force retry if odd | ||
252 | ;; | ||
250 | (p8) mov r2 = ar.itc // CPU_TIMER. 36 clocks latency!!! | 253 | (p8) mov r2 = ar.itc // CPU_TIMER. 36 clocks latency!!! |
251 | add r22 = IA64_TIME_INTERPOLATOR_LAST_COUNTER_OFFSET,r20 | 254 | add r22 = IA64_TIME_INTERPOLATOR_LAST_COUNTER_OFFSET,r20 |
252 | (p9) ld8 r2 = [r30] // readq(ti->address). Could also have latency issues.. | 255 | (p9) ld8 r2 = [r30] // readq(ti->address). Could also have latency issues.. |
@@ -284,7 +287,6 @@ EX(.fail_efault, probe.w.fault r31, 3) // This takes 5 cycles and we have spare | |||
284 | (p15) ld8 r17 = [r19],-IA64_TIMESPEC_TV_NSEC_OFFSET | 287 | (p15) ld8 r17 = [r19],-IA64_TIMESPEC_TV_NSEC_OFFSET |
285 | (p7) cmp.ne p7,p0 = r25,r3 // if cmpxchg not successful redo | 288 | (p7) cmp.ne p7,p0 = r25,r3 // if cmpxchg not successful redo |
286 | // simulate tbit.nz.or p7,p0 = r28,0 | 289 | // simulate tbit.nz.or p7,p0 = r28,0 |
287 | and r28 = ~1,r28 // Make sequence even to force retry if odd | ||
288 | getf.sig r2 = f8 | 290 | getf.sig r2 = f8 |
289 | mf | 291 | mf |
290 | add r8 = r8,r18 // Add time interpolator offset | 292 | add r8 = r8,r18 // Add time interpolator offset |