[IA64] improve flush_icache_range()

Check with PAL to see what the i-cache line size is for
each level of the cache, and so use the correct stride
when flushing the cache.

Acked-by: David Mosberger
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 35 insertions, 2 deletions

diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 2693e1522d7c..7fc891aca446 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -20,6 +20,7 @@
  * 02/01/00 R.Seth      fixed get_cpuinfo for SMP
  * 01/07/99 S.Eranian   added the support for command line argument
  * 06/24/99 W.Drummond  added boot_cpu_data.
+ * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
  */
 #include <linux/config.h>
 #include <linux/module.h>
@@ -83,6 +84,13 @@ EXPORT_SYMBOL(io_space);
 unsigned int num_io_spaces;
 
 /*
+ * "flush_icache_range()" needs to know what processor dependent stride size to use
+ * when it makes i-cache(s) coherent with d-caches.
+ */
+#define I_CACHE_STRIDE_SHIFT    5       /* Safest way to go: 32 bytes by 32 bytes */
+unsigned long ia64_i_cache_stride_shift = ~0;
+
+/*
  * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1).  This
  * mask specifies a mask of address bits that must be 0 in order for two buffers to be
  * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
@@ -626,6 +634,12 @@ setup_per_cpu_areas (void)
         /* start_kernel() requires this... */
 }
 
+/*
+ * Calculate the max. cache line size.
+ *
+ * In addition, the minimum of the i-cache stride sizes is calculated for
+ * "flush_icache_range()".
+ */
 static void
 get_max_cacheline_size (void)
 {
@@ -639,6 +653,8 @@ get_max_cacheline_size (void)
                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
                        __FUNCTION__, status);
                 max = SMP_CACHE_BYTES;
+                /* Safest setup for "flush_icache_range()" */
+                ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
                 goto out;
         }
 
@@ -647,14 +663,31 @@ get_max_cacheline_size (void)
                                                     &cci);
                 if (status != 0) {
                         printk(KERN_ERR
-                               "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
+                               "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
                                __FUNCTION__, l, status);
                         max = SMP_CACHE_BYTES;
+                        /* The safest setup for "flush_icache_range()" */
+                        cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
+                        cci.pcci_unified = 1;
                 }
                 line_size = 1 << cci.pcci_line_size;
                 if (line_size > max)
                         max = line_size;
-        }
+                if (!cci.pcci_unified) {
+                        status = ia64_pal_cache_config_info(l,
+                                                    /* cache_type (instruction)= */ 1,
+                                                    &cci);
+                        if (status != 0) {
+                                printk(KERN_ERR
+                                "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
+                                        __FUNCTION__, l, status);
+                                /* The safest setup for "flush_icache_range()" */
+                                cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
+                        }
+                }
+                if (cci.pcci_stride < ia64_i_cache_stride_shift)
+                        ia64_i_cache_stride_shift = cci.pcci_stride;
+        }
   out:
         if (max > ia64_max_cacheline_size)
                 ia64_max_cacheline_size = max;