[IA64] Multiple outstanding ptc.g instruction support

According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions.
But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize
ptc.g instructions issued by multiple processors. This serialization might have
scalability issue on a big SMP machine where many processors could purge TLB
in parallel.

The patch fixes this problem by issuing multiple ptc.g instructions in
ia64_global_tlb_purge(). It also adds support for the "PALO" table to get
a platform view of the max number of outstanding ptc.g instructions (which
may be different from the processor view found from PAL_VM_SUMMARY).

PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf

spinaphore implementation by Matthew Wilcox.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 4aa9eaea76c3..1cbd26340d87 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -59,6 +59,7 @@
 #include <asm/setup.h>
 #include <asm/smp.h>
 #include <asm/system.h>
+#include <asm/tlbflush.h>
 #include <asm/unistd.h>
 #include <asm/hpsim.h>
 
@@ -946,9 +947,10 @@ cpu_init (void)
 #endif
 
         /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
-        if (ia64_pal_vm_summary(NULL, &vmi) == 0)
+        if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
                 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
-        else {
+                setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, 0);
+        } else {
                 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
                 max_ctx = (1U << 15) - 1;       /* use architected minimum */
         }