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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-23 11:07:35 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-23 11:07:35 -0400
commit72441bdc76f7f71d7b75cdaa48f26dbb1f3d932e (patch)
treedf818d5e210c0c31c6634d43401d02a99ee87d1b /arch/ia64/kernel/setup.c
parent2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4 (diff)
parentfe393164c529f72def1952fb66c11732d0984d78 (diff)
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: (41 commits) [IA64] Fix annoying IA64_TR_ALLOC_MAX message. [IA64] kill sys32_pipe [IA64] remove sys32_pause [IA64] Add Variable Page Size and IA64 Support in Intel IOMMU ia64/pv_ops: paravirtualized instruction checker. ia64/xen: a recipe for using xen/ia64 with pv_ops. ia64/pv_ops: update Kconfig for paravirtualized guest and xen. ia64/xen: preliminary support for save/restore. ia64/xen: define xen machine vector for domU. ia64/pv_ops/xen: implement xen pv_time_ops. ia64/pv_ops/xen: implement xen pv_irq_ops. ia64/pv_ops/xen: define the nubmer of irqs which xen needs. ia64/pv_ops/xen: implement xen pv_iosapic_ops. ia64/pv_ops/xen: paravirtualize entry.S for ia64/xen. ia64/pv_ops/xen: paravirtualize ivt.S for xen. ia64/pv_ops/xen: paravirtualize DO_SAVE_MIN for xen. ia64/pv_ops/xen: define xen paravirtualized instructions for hand written assembly code ia64/pv_ops/xen: define xen pv_cpu_ops. ia64/pv_ops/xen: define xen pv_init_ops for various xen initialization. ia64/pv_ops/xen: elf note based xen startup. ...
Diffstat (limited to 'arch/ia64/kernel/setup.c')
-rw-r--r--arch/ia64/kernel/setup.c42
1 files changed, 29 insertions, 13 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 916ba898237f..ae7911702bf8 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -116,6 +116,13 @@ unsigned int num_io_spaces;
116 */ 116 */
117#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */ 117#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
118unsigned long ia64_i_cache_stride_shift = ~0; 118unsigned long ia64_i_cache_stride_shift = ~0;
119/*
120 * "clflush_cache_range()" needs to know what processor dependent stride size to
121 * use when it flushes cache lines including both d-cache and i-cache.
122 */
123/* Safest way to go: 32 bytes by 32 bytes */
124#define CACHE_STRIDE_SHIFT 5
125unsigned long ia64_cache_stride_shift = ~0;
119 126
120/* 127/*
121 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This 128 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
@@ -852,13 +859,14 @@ setup_per_cpu_areas (void)
852} 859}
853 860
854/* 861/*
855 * Calculate the max. cache line size. 862 * Do the following calculations:
856 * 863 *
857 * In addition, the minimum of the i-cache stride sizes is calculated for 864 * 1. the max. cache line size.
858 * "flush_icache_range()". 865 * 2. the minimum of the i-cache stride sizes for "flush_icache_range()".
866 * 3. the minimum of the cache stride sizes for "clflush_cache_range()".
859 */ 867 */
860static void __cpuinit 868static void __cpuinit
861get_max_cacheline_size (void) 869get_cache_info(void)
862{ 870{
863 unsigned long line_size, max = 1; 871 unsigned long line_size, max = 1;
864 u64 l, levels, unique_caches; 872 u64 l, levels, unique_caches;
@@ -872,12 +880,14 @@ get_max_cacheline_size (void)
872 max = SMP_CACHE_BYTES; 880 max = SMP_CACHE_BYTES;
873 /* Safest setup for "flush_icache_range()" */ 881 /* Safest setup for "flush_icache_range()" */
874 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT; 882 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
883 /* Safest setup for "clflush_cache_range()" */
884 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
875 goto out; 885 goto out;
876 } 886 }
877 887
878 for (l = 0; l < levels; ++l) { 888 for (l = 0; l < levels; ++l) {
879 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2, 889 /* cache_type (data_or_unified)=2 */
880 &cci); 890 status = ia64_pal_cache_config_info(l, 2, &cci);
881 if (status != 0) { 891 if (status != 0) {
882 printk(KERN_ERR 892 printk(KERN_ERR
883 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n", 893 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
@@ -885,15 +895,21 @@ get_max_cacheline_size (void)
885 max = SMP_CACHE_BYTES; 895 max = SMP_CACHE_BYTES;
886 /* The safest setup for "flush_icache_range()" */ 896 /* The safest setup for "flush_icache_range()" */
887 cci.pcci_stride = I_CACHE_STRIDE_SHIFT; 897 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
898 /* The safest setup for "clflush_cache_range()" */
899 ia64_cache_stride_shift = CACHE_STRIDE_SHIFT;
888 cci.pcci_unified = 1; 900 cci.pcci_unified = 1;
901 } else {
902 if (cci.pcci_stride < ia64_cache_stride_shift)
903 ia64_cache_stride_shift = cci.pcci_stride;
904
905 line_size = 1 << cci.pcci_line_size;
906 if (line_size > max)
907 max = line_size;
889 } 908 }
890 line_size = 1 << cci.pcci_line_size; 909
891 if (line_size > max)
892 max = line_size;
893 if (!cci.pcci_unified) { 910 if (!cci.pcci_unified) {
894 status = ia64_pal_cache_config_info(l, 911 /* cache_type (instruction)=1*/
895 /* cache_type (instruction)= */ 1, 912 status = ia64_pal_cache_config_info(l, 1, &cci);
896 &cci);
897 if (status != 0) { 913 if (status != 0) {
898 printk(KERN_ERR 914 printk(KERN_ERR
899 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n", 915 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
@@ -947,7 +963,7 @@ cpu_init (void)
947 } 963 }
948#endif 964#endif
949 965
950 get_max_cacheline_size(); 966 get_cache_info();
951 967
952 /* 968 /*
953 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called 969 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called