aboutsummaryrefslogtreecommitdiffstats
path: root/arch/ia64/kernel/setup.c
diff options
context:
space:
mode:
authorTony Luck <tony.luck@intel.com>2008-05-27 16:23:16 -0400
committerTony Luck <tony.luck@intel.com>2008-05-27 16:24:39 -0400
commit4dcc29e1574d88f4465ba865ed82800032f76418 (patch)
tree5579a225a6782f0f5014cbbe6938847b7f3cd53f /arch/ia64/kernel/setup.c
parente490517a039a99d692cb3a5561941b0a5f576172 (diff)
[IA64] Workaround for RSE issue
Problem: An application violating the architectural rules regarding operation dependencies and having specific Register Stack Engine (RSE) state at the time of the violation, may result in an illegal operation fault and invalid RSE state. Such faults may initiate a cascade of repeated illegal operation faults within OS interruption handlers. The specific behavior is OS dependent. Implication: An application causing an illegal operation fault with specific RSE state may result in a series of illegal operation faults and an eventual OS stack overflow condition. Workaround: OS interruption handlers that switch to kernel backing store implement a check for invalid RSE state to avoid the series of illegal operation faults. The core of the workaround is the RSE_WORKAROUND code sequence inserted into each invocation of the SAVE_MIN_WITH_COVER and SAVE_MIN_WITH_COVER_R19 macros. This sequence includes hard-coded constants that depend on the number of stacked physical registers being 96. The rest of this patch consists of code to disable this workaround should this not be the case (with the presumption that if a future Itanium processor increases the number of registers, it would also remove the need for this patch). Move the start of the RBS up to a mod32 boundary to avoid some corner cases. The dispatch_illegal_op_fault code outgrew the spot it was squatting in when built with this patch and CONFIG_VIRT_CPU_ACCOUNTING=y Move it out to the end of the ivt. Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/setup.c')
-rw-r--r--arch/ia64/kernel/setup.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index e9596cd0cdab..f48a809c686d 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -560,6 +560,17 @@ setup_arch (char **cmdline_p)
560 /* process SAL system table: */ 560 /* process SAL system table: */
561 ia64_sal_init(__va(efi.sal_systab)); 561 ia64_sal_init(__va(efi.sal_systab));
562 562
563#ifdef CONFIG_ITANIUM
564 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
565#else
566 {
567 u64 num_phys_stacked;
568
569 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96)
570 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
571 }
572#endif
573
563#ifdef CONFIG_SMP 574#ifdef CONFIG_SMP
564 cpu_physical_id(0) = hard_smp_processor_id(); 575 cpu_physical_id(0) = hard_smp_processor_id();
565#endif 576#endif