diff options
author | Peter Chubb <peterc@gelato.unsw.edu.au> | 2005-08-25 20:39:00 -0400 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2005-08-31 11:34:51 -0400 |
commit | 714d2dc14914f0f7bb008effe830c99eb47c75df (patch) | |
tree | f8282f3353680ff79696f832be72e096311ae556 /arch/ia64/kernel/palinfo.c | |
parent | dc90e95f310f4f821c905b2aec8e9449bb3270fa (diff) |
[IA64] Allow /proc/pal/cpu0/vm_info under the simulator
Not all of the PAL VM calls are implemented for the SKI simulator.
Don't just give up if one fails, print information from the calls
that succeed.
Signed-off-by: Peter Chubb <peterc@gelato.unsw.edu.au>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/kernel/palinfo.c')
-rw-r--r-- | arch/ia64/kernel/palinfo.c | 115 |
1 files changed, 60 insertions, 55 deletions
diff --git a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c index 25e7c8344564..89faa603c6be 100644 --- a/arch/ia64/kernel/palinfo.c +++ b/arch/ia64/kernel/palinfo.c | |||
@@ -307,11 +307,9 @@ vm_info(char *page) | |||
307 | 307 | ||
308 | if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) { | 308 | if ((status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2)) !=0) { |
309 | printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status); | 309 | printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status); |
310 | return 0; | 310 | } else { |
311 | } | ||
312 | 311 | ||
313 | 312 | p += sprintf(p, | |
314 | p += sprintf(p, | ||
315 | "Physical Address Space : %d bits\n" | 313 | "Physical Address Space : %d bits\n" |
316 | "Virtual Address Space : %d bits\n" | 314 | "Virtual Address Space : %d bits\n" |
317 | "Protection Key Registers(PKR) : %d\n" | 315 | "Protection Key Registers(PKR) : %d\n" |
@@ -319,92 +317,99 @@ vm_info(char *page) | |||
319 | "Hash Tag ID : 0x%x\n" | 317 | "Hash Tag ID : 0x%x\n" |
320 | "Size of RR.rid : %d\n", | 318 | "Size of RR.rid : %d\n", |
321 | vm_info_1.pal_vm_info_1_s.phys_add_size, | 319 | vm_info_1.pal_vm_info_1_s.phys_add_size, |
322 | vm_info_2.pal_vm_info_2_s.impl_va_msb+1, vm_info_1.pal_vm_info_1_s.max_pkr+1, | 320 | vm_info_2.pal_vm_info_2_s.impl_va_msb+1, |
323 | vm_info_1.pal_vm_info_1_s.key_size, vm_info_1.pal_vm_info_1_s.hash_tag_id, | 321 | vm_info_1.pal_vm_info_1_s.max_pkr+1, |
322 | vm_info_1.pal_vm_info_1_s.key_size, | ||
323 | vm_info_1.pal_vm_info_1_s.hash_tag_id, | ||
324 | vm_info_2.pal_vm_info_2_s.rid_size); | 324 | vm_info_2.pal_vm_info_2_s.rid_size); |
325 | } | ||
325 | 326 | ||
326 | if (ia64_pal_mem_attrib(&attrib) != 0) | 327 | if (ia64_pal_mem_attrib(&attrib) == 0) { |
327 | return 0; | 328 | p += sprintf(p, "Supported memory attributes : "); |
328 | 329 | sep = ""; | |
329 | p += sprintf(p, "Supported memory attributes : "); | 330 | for (i = 0; i < 8; i++) { |
330 | sep = ""; | 331 | if (attrib & (1 << i)) { |
331 | for (i = 0; i < 8; i++) { | 332 | p += sprintf(p, "%s%s", sep, mem_attrib[i]); |
332 | if (attrib & (1 << i)) { | 333 | sep = ", "; |
333 | p += sprintf(p, "%s%s", sep, mem_attrib[i]); | 334 | } |
334 | sep = ", "; | ||
335 | } | 335 | } |
336 | p += sprintf(p, "\n"); | ||
336 | } | 337 | } |
337 | p += sprintf(p, "\n"); | ||
338 | 338 | ||
339 | if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) { | 339 | if ((status = ia64_pal_vm_page_size(&tr_pages, &vw_pages)) !=0) { |
340 | printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status); | 340 | printk(KERN_ERR "ia64_pal_vm_page_size=%ld\n", status); |
341 | return 0; | 341 | } else { |
342 | } | ||
343 | |||
344 | p += sprintf(p, | ||
345 | "\nTLB walker : %simplemented\n" | ||
346 | "Number of DTR : %d\n" | ||
347 | "Number of ITR : %d\n" | ||
348 | "TLB insertable page sizes : ", | ||
349 | vm_info_1.pal_vm_info_1_s.vw ? "" : "not ", | ||
350 | vm_info_1.pal_vm_info_1_s.max_dtr_entry+1, | ||
351 | vm_info_1.pal_vm_info_1_s.max_itr_entry+1); | ||
352 | 342 | ||
343 | p += sprintf(p, | ||
344 | "\nTLB walker : %simplemented\n" | ||
345 | "Number of DTR : %d\n" | ||
346 | "Number of ITR : %d\n" | ||
347 | "TLB insertable page sizes : ", | ||
348 | vm_info_1.pal_vm_info_1_s.vw ? "" : "not ", | ||
349 | vm_info_1.pal_vm_info_1_s.max_dtr_entry+1, | ||
350 | vm_info_1.pal_vm_info_1_s.max_itr_entry+1); | ||
353 | 351 | ||
354 | p = bitvector_process(p, tr_pages); | ||
355 | 352 | ||
356 | p += sprintf(p, "\nTLB purgeable page sizes : "); | 353 | p = bitvector_process(p, tr_pages); |
357 | 354 | ||
358 | p = bitvector_process(p, vw_pages); | 355 | p += sprintf(p, "\nTLB purgeable page sizes : "); |
359 | 356 | ||
357 | p = bitvector_process(p, vw_pages); | ||
358 | } | ||
360 | if ((status=ia64_get_ptce(&ptce)) != 0) { | 359 | if ((status=ia64_get_ptce(&ptce)) != 0) { |
361 | printk(KERN_ERR "ia64_get_ptce=%ld\n", status); | 360 | printk(KERN_ERR "ia64_get_ptce=%ld\n", status); |
362 | return 0; | 361 | } else { |
363 | } | 362 | p += sprintf(p, |
364 | |||
365 | p += sprintf(p, | ||
366 | "\nPurge base address : 0x%016lx\n" | 363 | "\nPurge base address : 0x%016lx\n" |
367 | "Purge outer loop count : %d\n" | 364 | "Purge outer loop count : %d\n" |
368 | "Purge inner loop count : %d\n" | 365 | "Purge inner loop count : %d\n" |
369 | "Purge outer loop stride : %d\n" | 366 | "Purge outer loop stride : %d\n" |
370 | "Purge inner loop stride : %d\n", | 367 | "Purge inner loop stride : %d\n", |
371 | ptce.base, ptce.count[0], ptce.count[1], ptce.stride[0], ptce.stride[1]); | 368 | ptce.base, ptce.count[0], ptce.count[1], |
369 | ptce.stride[0], ptce.stride[1]); | ||
372 | 370 | ||
373 | p += sprintf(p, | 371 | p += sprintf(p, |
374 | "TC Levels : %d\n" | 372 | "TC Levels : %d\n" |
375 | "Unique TC(s) : %d\n", | 373 | "Unique TC(s) : %d\n", |
376 | vm_info_1.pal_vm_info_1_s.num_tc_levels, | 374 | vm_info_1.pal_vm_info_1_s.num_tc_levels, |
377 | vm_info_1.pal_vm_info_1_s.max_unique_tcs); | 375 | vm_info_1.pal_vm_info_1_s.max_unique_tcs); |
378 | 376 | ||
379 | for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) { | 377 | for(i=0; i < vm_info_1.pal_vm_info_1_s.num_tc_levels; i++) { |
380 | for (j=2; j>0 ; j--) { | 378 | for (j=2; j>0 ; j--) { |
381 | tc_pages = 0; /* just in case */ | 379 | tc_pages = 0; /* just in case */ |
382 | 380 | ||
383 | 381 | ||
384 | /* even without unification, some levels may not be present */ | 382 | /* even without unification, some levels may not be present */ |
385 | if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) { | 383 | if ((status=ia64_pal_vm_info(i,j, &tc_info, &tc_pages)) != 0) { |
386 | continue; | 384 | continue; |
387 | } | 385 | } |
388 | 386 | ||
389 | p += sprintf(p, | 387 | p += sprintf(p, |
390 | "\n%s Translation Cache Level %d:\n" | 388 | "\n%s Translation Cache Level %d:\n" |
391 | "\tHash sets : %d\n" | 389 | "\tHash sets : %d\n" |
392 | "\tAssociativity : %d\n" | 390 | "\tAssociativity : %d\n" |
393 | "\tNumber of entries : %d\n" | 391 | "\tNumber of entries : %d\n" |
394 | "\tFlags : ", | 392 | "\tFlags : ", |
395 | cache_types[j+tc_info.tc_unified], i+1, tc_info.tc_num_sets, | 393 | cache_types[j+tc_info.tc_unified], i+1, |
396 | tc_info.tc_associativity, tc_info.tc_num_entries); | 394 | tc_info.tc_num_sets, |
395 | tc_info.tc_associativity, | ||
396 | tc_info.tc_num_entries); | ||
397 | 397 | ||
398 | if (tc_info.tc_pf) p += sprintf(p, "PreferredPageSizeOptimized "); | 398 | if (tc_info.tc_pf) |
399 | if (tc_info.tc_unified) p += sprintf(p, "Unified "); | 399 | p += sprintf(p, "PreferredPageSizeOptimized "); |
400 | if (tc_info.tc_reduce_tr) p += sprintf(p, "TCReduction"); | 400 | if (tc_info.tc_unified) |
401 | p += sprintf(p, "Unified "); | ||
402 | if (tc_info.tc_reduce_tr) | ||
403 | p += sprintf(p, "TCReduction"); | ||
401 | 404 | ||
402 | p += sprintf(p, "\n\tSupported page sizes: "); | 405 | p += sprintf(p, "\n\tSupported page sizes: "); |
403 | 406 | ||
404 | p = bitvector_process(p, tc_pages); | 407 | p = bitvector_process(p, tc_pages); |
405 | 408 | ||
406 | /* when unified date (j=2) is enough */ | 409 | /* when unified date (j=2) is enough */ |
407 | if (tc_info.tc_unified) break; | 410 | if (tc_info.tc_unified) |
411 | break; | ||
412 | } | ||
408 | } | 413 | } |
409 | } | 414 | } |
410 | p += sprintf(p, "\n"); | 415 | p += sprintf(p, "\n"); |
@@ -440,14 +445,14 @@ register_info(char *page) | |||
440 | p += sprintf(p, "\n"); | 445 | p += sprintf(p, "\n"); |
441 | } | 446 | } |
442 | 447 | ||
443 | if (ia64_pal_rse_info(&phys_stacked, &hints) != 0) return 0; | 448 | if (ia64_pal_rse_info(&phys_stacked, &hints) == 0) { |
444 | 449 | ||
445 | p += sprintf(p, | 450 | p += sprintf(p, |
446 | "RSE stacked physical registers : %ld\n" | 451 | "RSE stacked physical registers : %ld\n" |
447 | "RSE load/store hints : %ld (%s)\n", | 452 | "RSE load/store hints : %ld (%s)\n", |
448 | phys_stacked, hints.ph_data, | 453 | phys_stacked, hints.ph_data, |
449 | hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)"); | 454 | hints.ph_data < RSE_HINTS_COUNT ? rse_hints[hints.ph_data]: "(??)"); |
450 | 455 | } | |
451 | if (ia64_pal_debug_info(&iregs, &dregs)) | 456 | if (ia64_pal_debug_info(&iregs, &dregs)) |
452 | return 0; | 457 | return 0; |
453 | 458 | ||