[IA64] Disable/re-enable CPE interrupts on Altix

When the CPE handler encounters too many CPEs (such as a solid single
bit memory error), it sets up a polling timer and disables the CPE
interrupt (to avoid excessive overhead logging the stream of single
bit errors).  disable_irq_nosync() calls chip->disable() to provide
a chipset specifiec interface for disabling the interrupt.  This patch
adds the Altix specific support to disable and re-enable the CPE interrupt.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index cc87025e8f54..10b48cd15a87 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -571,7 +571,7 @@ out:
  *  Outputs
  *      None
  */
-static void __init
+void
 ia64_mca_register_cpev (int cpev)
 {
         /* Register the CPE interrupt vector with SAL */