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authorTony Luck <tony.luck@intel.com>2008-08-01 13:13:32 -0400
committerTony Luck <tony.luck@intel.com>2008-08-01 13:21:21 -0400
commit7f30491ccd28627742e37899453ae20e3da8e18f (patch)
tree7291c0a26ed3a31acf9542857af3981d278f5de8 /arch/ia64/include
parent94ad374a0751f40d25e22e036c37f7263569d24c (diff)
[IA64] Move include/asm-ia64 to arch/ia64/include/asm
After moving the the include files there were a few clean-ups: 1) Some files used #include <asm-ia64/xyz.h>, changed to <asm/xyz.h> 2) Some comments alerted maintainers to look at various header files to make matching updates if certain code were to be changed. Updated these comments to use the new include paths. 3) Some header files mentioned their own names in initial comments. Just deleted these self references. Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch/ia64/include')
-rw-r--r--arch/ia64/include/asm/Kbuild16
-rw-r--r--arch/ia64/include/asm/a.out.h32
-rw-r--r--arch/ia64/include/asm/acpi-ext.h21
-rw-r--r--arch/ia64/include/asm/acpi.h165
-rw-r--r--arch/ia64/include/asm/agp.h30
-rw-r--r--arch/ia64/include/asm/asmmacro.h135
-rw-r--r--arch/ia64/include/asm/atomic.h226
-rw-r--r--arch/ia64/include/asm/auxvec.h11
-rw-r--r--arch/ia64/include/asm/bitops.h468
-rw-r--r--arch/ia64/include/asm/break.h23
-rw-r--r--arch/ia64/include/asm/bug.h14
-rw-r--r--arch/ia64/include/asm/bugs.h19
-rw-r--r--arch/ia64/include/asm/byteorder.h42
-rw-r--r--arch/ia64/include/asm/cache.h29
-rw-r--r--arch/ia64/include/asm/cacheflush.h51
-rw-r--r--arch/ia64/include/asm/checksum.h79
-rw-r--r--arch/ia64/include/asm/compat.h207
-rw-r--r--arch/ia64/include/asm/cpu.h22
-rw-r--r--arch/ia64/include/asm/cputime.h109
-rw-r--r--arch/ia64/include/asm/current.h17
-rw-r--r--arch/ia64/include/asm/cyclone.h15
-rw-r--r--arch/ia64/include/asm/delay.h88
-rw-r--r--arch/ia64/include/asm/device.h15
-rw-r--r--arch/ia64/include/asm/div64.h1
-rw-r--r--arch/ia64/include/asm/dma-mapping.h97
-rw-r--r--arch/ia64/include/asm/dma.h24
-rw-r--r--arch/ia64/include/asm/dmi.h11
-rw-r--r--arch/ia64/include/asm/elf.h269
-rw-r--r--arch/ia64/include/asm/emergency-restart.h6
-rw-r--r--arch/ia64/include/asm/errno.h1
-rw-r--r--arch/ia64/include/asm/esi.h29
-rw-r--r--arch/ia64/include/asm/fb.h23
-rw-r--r--arch/ia64/include/asm/fcntl.h13
-rw-r--r--arch/ia64/include/asm/fpswa.h73
-rw-r--r--arch/ia64/include/asm/fpu.h66
-rw-r--r--arch/ia64/include/asm/futex.h124
-rw-r--r--arch/ia64/include/asm/gcc_intrin.h620
-rw-r--r--arch/ia64/include/asm/hardirq.h37
-rw-r--r--arch/ia64/include/asm/hpsim.h16
-rw-r--r--arch/ia64/include/asm/hugetlb.h80
-rw-r--r--arch/ia64/include/asm/hw_irq.h192
-rw-r--r--arch/ia64/include/asm/ia32.h40
-rw-r--r--arch/ia64/include/asm/ia64regs.h100
-rw-r--r--arch/ia64/include/asm/intel_intrin.h161
-rw-r--r--arch/ia64/include/asm/intrinsics.h241
-rw-r--r--arch/ia64/include/asm/io.h459
-rw-r--r--arch/ia64/include/asm/ioctl.h1
-rw-r--r--arch/ia64/include/asm/ioctls.h93
-rw-r--r--arch/ia64/include/asm/iosapic.h126
-rw-r--r--arch/ia64/include/asm/ipcbuf.h28
-rw-r--r--arch/ia64/include/asm/irq.h34
-rw-r--r--arch/ia64/include/asm/irq_regs.h1
-rw-r--r--arch/ia64/include/asm/kdebug.h57
-rw-r--r--arch/ia64/include/asm/kexec.h44
-rw-r--r--arch/ia64/include/asm/kmap_types.h30
-rw-r--r--arch/ia64/include/asm/kprobes.h132
-rw-r--r--arch/ia64/include/asm/kregs.h165
-rw-r--r--arch/ia64/include/asm/kvm.h211
-rw-r--r--arch/ia64/include/asm/kvm_host.h527
-rw-r--r--arch/ia64/include/asm/kvm_para.h27
-rw-r--r--arch/ia64/include/asm/libata-portmap.h12
-rw-r--r--arch/ia64/include/asm/linkage.h14
-rw-r--r--arch/ia64/include/asm/local.h1
-rw-r--r--arch/ia64/include/asm/machvec.h460
-rw-r--r--arch/ia64/include/asm/machvec_dig.h16
-rw-r--r--arch/ia64/include/asm/machvec_hpsim.h18
-rw-r--r--arch/ia64/include/asm/machvec_hpzx1.h37
-rw-r--r--arch/ia64/include/asm/machvec_hpzx1_swiotlb.h42
-rw-r--r--arch/ia64/include/asm/machvec_init.h33
-rw-r--r--arch/ia64/include/asm/machvec_sn2.h139
-rw-r--r--arch/ia64/include/asm/machvec_uv.h26
-rw-r--r--arch/ia64/include/asm/mc146818rtc.h10
-rw-r--r--arch/ia64/include/asm/mca.h179
-rw-r--r--arch/ia64/include/asm/mca_asm.h242
-rw-r--r--arch/ia64/include/asm/meminit.h75
-rw-r--r--arch/ia64/include/asm/mman.h33
-rw-r--r--arch/ia64/include/asm/mmu.h13
-rw-r--r--arch/ia64/include/asm/mmu_context.h198
-rw-r--r--arch/ia64/include/asm/mmzone.h50
-rw-r--r--arch/ia64/include/asm/module.h36
-rw-r--r--arch/ia64/include/asm/msgbuf.h27
-rw-r--r--arch/ia64/include/asm/mutex.h92
-rw-r--r--arch/ia64/include/asm/native/inst.h175
-rw-r--r--arch/ia64/include/asm/native/irq.h33
-rw-r--r--arch/ia64/include/asm/nodedata.h63
-rw-r--r--arch/ia64/include/asm/numa.h82
-rw-r--r--arch/ia64/include/asm/page.h223
-rw-r--r--arch/ia64/include/asm/pal.h1827
-rw-r--r--arch/ia64/include/asm/param.h33
-rw-r--r--arch/ia64/include/asm/paravirt.h253
-rw-r--r--arch/ia64/include/asm/paravirt_privop.h112
-rw-r--r--arch/ia64/include/asm/parport.h20
-rw-r--r--arch/ia64/include/asm/patch.h27
-rw-r--r--arch/ia64/include/asm/pci.h167
-rw-r--r--arch/ia64/include/asm/percpu.h51
-rw-r--r--arch/ia64/include/asm/perfmon.h279
-rw-r--r--arch/ia64/include/asm/perfmon_default_smpl.h83
-rw-r--r--arch/ia64/include/asm/pgalloc.h122
-rw-r--r--arch/ia64/include/asm/pgtable.h615
-rw-r--r--arch/ia64/include/asm/poll.h1
-rw-r--r--arch/ia64/include/asm/posix_types.h126
-rw-r--r--arch/ia64/include/asm/processor.h771
-rw-r--r--arch/ia64/include/asm/ptrace.h364
-rw-r--r--arch/ia64/include/asm/ptrace_offsets.h268
-rw-r--r--arch/ia64/include/asm/resource.h7
-rw-r--r--arch/ia64/include/asm/rse.h66
-rw-r--r--arch/ia64/include/asm/rwsem.h182
-rw-r--r--arch/ia64/include/asm/sal.h905
-rw-r--r--arch/ia64/include/asm/scatterlist.h38
-rw-r--r--arch/ia64/include/asm/sections.h25
-rw-r--r--arch/ia64/include/asm/segment.h6
-rw-r--r--arch/ia64/include/asm/sembuf.h22
-rw-r--r--arch/ia64/include/asm/serial.h17
-rw-r--r--arch/ia64/include/asm/setup.h6
-rw-r--r--arch/ia64/include/asm/shmbuf.h38
-rw-r--r--arch/ia64/include/asm/shmparam.h12
-rw-r--r--arch/ia64/include/asm/sigcontext.h70
-rw-r--r--arch/ia64/include/asm/siginfo.h139
-rw-r--r--arch/ia64/include/asm/signal.h160
-rw-r--r--arch/ia64/include/asm/smp.h138
-rw-r--r--arch/ia64/include/asm/sn/acpi.h17
-rw-r--r--arch/ia64/include/asm/sn/addrs.h299
-rw-r--r--arch/ia64/include/asm/sn/arch.h86
-rw-r--r--arch/ia64/include/asm/sn/bte.h233
-rw-r--r--arch/ia64/include/asm/sn/clksupport.h28
-rw-r--r--arch/ia64/include/asm/sn/geo.h132
-rw-r--r--arch/ia64/include/asm/sn/intr.h68
-rw-r--r--arch/ia64/include/asm/sn/io.h274
-rw-r--r--arch/ia64/include/asm/sn/ioc3.h241
-rw-r--r--arch/ia64/include/asm/sn/klconfig.h246
-rw-r--r--arch/ia64/include/asm/sn/l1.h51
-rw-r--r--arch/ia64/include/asm/sn/leds.h33
-rw-r--r--arch/ia64/include/asm/sn/module.h127
-rw-r--r--arch/ia64/include/asm/sn/mspec.h59
-rw-r--r--arch/ia64/include/asm/sn/nodepda.h82
-rw-r--r--arch/ia64/include/asm/sn/pcibr_provider.h150
-rw-r--r--arch/ia64/include/asm/sn/pcibus_provider_defs.h68
-rw-r--r--arch/ia64/include/asm/sn/pcidev.h85
-rw-r--r--arch/ia64/include/asm/sn/pda.h69
-rw-r--r--arch/ia64/include/asm/sn/pic.h261
-rw-r--r--arch/ia64/include/asm/sn/rw_mmr.h28
-rw-r--r--arch/ia64/include/asm/sn/shub_mmr.h502
-rw-r--r--arch/ia64/include/asm/sn/shubio.h3358
-rw-r--r--arch/ia64/include/asm/sn/simulator.h25
-rw-r--r--arch/ia64/include/asm/sn/sn2/sn_hwperf.h242
-rw-r--r--arch/ia64/include/asm/sn/sn_cpuid.h132
-rw-r--r--arch/ia64/include/asm/sn/sn_feature_sets.h58
-rw-r--r--arch/ia64/include/asm/sn/sn_sal.h1188
-rw-r--r--arch/ia64/include/asm/sn/tioca.h596
-rw-r--r--arch/ia64/include/asm/sn/tioca_provider.h207
-rw-r--r--arch/ia64/include/asm/sn/tioce.h760
-rw-r--r--arch/ia64/include/asm/sn/tioce_provider.h63
-rw-r--r--arch/ia64/include/asm/sn/tiocp.h257
-rw-r--r--arch/ia64/include/asm/sn/tiocx.h72
-rw-r--r--arch/ia64/include/asm/sn/types.h26
-rw-r--r--arch/ia64/include/asm/socket.h66
-rw-r--r--arch/ia64/include/asm/sockios.h20
-rw-r--r--arch/ia64/include/asm/sparsemem.h20
-rw-r--r--arch/ia64/include/asm/spinlock.h220
-rw-r--r--arch/ia64/include/asm/spinlock_types.h21
-rw-r--r--arch/ia64/include/asm/stat.h51
-rw-r--r--arch/ia64/include/asm/statfs.h62
-rw-r--r--arch/ia64/include/asm/string.h21
-rw-r--r--arch/ia64/include/asm/suspend.h1
-rw-r--r--arch/ia64/include/asm/system.h292
-rw-r--r--arch/ia64/include/asm/termbits.h207
-rw-r--r--arch/ia64/include/asm/termios.h97
-rw-r--r--arch/ia64/include/asm/thread_info.h148
-rw-r--r--arch/ia64/include/asm/timex.h42
-rw-r--r--arch/ia64/include/asm/tlb.h257
-rw-r--r--arch/ia64/include/asm/tlbflush.h102
-rw-r--r--arch/ia64/include/asm/topology.h126
-rw-r--r--arch/ia64/include/asm/types.h46
-rw-r--r--arch/ia64/include/asm/uaccess.h401
-rw-r--r--arch/ia64/include/asm/ucontext.h12
-rw-r--r--arch/ia64/include/asm/unaligned.h11
-rw-r--r--arch/ia64/include/asm/uncached.h12
-rw-r--r--arch/ia64/include/asm/unistd.h384
-rw-r--r--arch/ia64/include/asm/unwind.h233
-rw-r--r--arch/ia64/include/asm/user.h58
-rw-r--r--arch/ia64/include/asm/ustack.h20
-rw-r--r--arch/ia64/include/asm/uv/uv_hub.h309
-rw-r--r--arch/ia64/include/asm/uv/uv_mmrs.h673
-rw-r--r--arch/ia64/include/asm/vga.h25
-rw-r--r--arch/ia64/include/asm/xor.h31
185 files changed, 29363 insertions, 0 deletions
diff --git a/arch/ia64/include/asm/Kbuild b/arch/ia64/include/asm/Kbuild
new file mode 100644
index 000000000000..ccbe8ae47a61
--- /dev/null
+++ b/arch/ia64/include/asm/Kbuild
@@ -0,0 +1,16 @@
1include include/asm-generic/Kbuild.asm
2
3header-y += break.h
4header-y += fpu.h
5header-y += fpswa.h
6header-y += ia64regs.h
7header-y += intel_intrin.h
8header-y += perfmon_default_smpl.h
9header-y += ptrace_offsets.h
10header-y += rse.h
11header-y += ucontext.h
12
13unifdef-y += gcc_intrin.h
14unifdef-y += intrinsics.h
15unifdef-y += perfmon.h
16unifdef-y += ustack.h
diff --git a/arch/ia64/include/asm/a.out.h b/arch/ia64/include/asm/a.out.h
new file mode 100644
index 000000000000..193dcfb67596
--- /dev/null
+++ b/arch/ia64/include/asm/a.out.h
@@ -0,0 +1,32 @@
1#ifndef _ASM_IA64_A_OUT_H
2#define _ASM_IA64_A_OUT_H
3
4/*
5 * No a.out format has been (or should be) defined so this file is
6 * just a dummy that allows us to get binfmt_elf compiled. It
7 * probably would be better to clean up binfmt_elf.c so it does not
8 * necessarily depend on there being a.out support.
9 *
10 * Modified 1998-2002
11 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
12 */
13
14#include <linux/types.h>
15
16struct exec {
17 unsigned long a_info;
18 unsigned long a_text;
19 unsigned long a_data;
20 unsigned long a_bss;
21 unsigned long a_entry;
22};
23
24#define N_TXTADDR(x) 0
25#define N_DATADDR(x) 0
26#define N_BSSADDR(x) 0
27#define N_DRSIZE(x) 0
28#define N_TRSIZE(x) 0
29#define N_SYMSIZE(x) 0
30#define N_TXTOFF(x) 0
31
32#endif /* _ASM_IA64_A_OUT_H */
diff --git a/arch/ia64/include/asm/acpi-ext.h b/arch/ia64/include/asm/acpi-ext.h
new file mode 100644
index 000000000000..734d137dda6e
--- /dev/null
+++ b/arch/ia64/include/asm/acpi-ext.h
@@ -0,0 +1,21 @@
1/*
2 * (c) Copyright 2003, 2006 Hewlett-Packard Development Company, L.P.
3 * Alex Williamson <alex.williamson@hp.com>
4 * Bjorn Helgaas <bjorn.helgaas@hp.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Vendor specific extensions to ACPI.
11 */
12
13#ifndef _ASM_IA64_ACPI_EXT_H
14#define _ASM_IA64_ACPI_EXT_H
15
16#include <linux/types.h>
17#include <acpi/actypes.h>
18
19extern acpi_status hp_acpi_csr_space (acpi_handle, u64 *base, u64 *length);
20
21#endif /* _ASM_IA64_ACPI_EXT_H */
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
new file mode 100644
index 000000000000..0f82cc2934e1
--- /dev/null
+++ b/arch/ia64/include/asm/acpi.h
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 1999 VA Linux Systems
3 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
4 * Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com>
5 * Copyright (C) 2001,2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 */
25
26#ifndef _ASM_ACPI_H
27#define _ASM_ACPI_H
28
29#ifdef __KERNEL__
30
31#include <acpi/pdc_intel.h>
32
33#include <linux/init.h>
34#include <linux/numa.h>
35#include <asm/system.h>
36#include <asm/numa.h>
37
38#define COMPILER_DEPENDENT_INT64 long
39#define COMPILER_DEPENDENT_UINT64 unsigned long
40
41/*
42 * Calling conventions:
43 *
44 * ACPI_SYSTEM_XFACE - Interfaces to host OS (handlers, threads)
45 * ACPI_EXTERNAL_XFACE - External ACPI interfaces
46 * ACPI_INTERNAL_XFACE - Internal ACPI interfaces
47 * ACPI_INTERNAL_VAR_XFACE - Internal variable-parameter list interfaces
48 */
49#define ACPI_SYSTEM_XFACE
50#define ACPI_EXTERNAL_XFACE
51#define ACPI_INTERNAL_XFACE
52#define ACPI_INTERNAL_VAR_XFACE
53
54/* Asm macros */
55
56#define ACPI_ASM_MACROS
57#define BREAKPOINT3
58#define ACPI_DISABLE_IRQS() local_irq_disable()
59#define ACPI_ENABLE_IRQS() local_irq_enable()
60#define ACPI_FLUSH_CPU_CACHE()
61
62static inline int
63ia64_acpi_acquire_global_lock (unsigned int *lock)
64{
65 unsigned int old, new, val;
66 do {
67 old = *lock;
68 new = (((old & ~0x3) + 2) + ((old >> 1) & 0x1));
69 val = ia64_cmpxchg4_acq(lock, new, old);
70 } while (unlikely (val != old));
71 return (new < 3) ? -1 : 0;
72}
73
74static inline int
75ia64_acpi_release_global_lock (unsigned int *lock)
76{
77 unsigned int old, new, val;
78 do {
79 old = *lock;
80 new = old & ~0x3;
81 val = ia64_cmpxchg4_acq(lock, new, old);
82 } while (unlikely (val != old));
83 return old & 0x1;
84}
85
86#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
87 ((Acq) = ia64_acpi_acquire_global_lock(&facs->global_lock))
88
89#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
90 ((Acq) = ia64_acpi_release_global_lock(&facs->global_lock))
91
92#define acpi_disabled 0 /* ACPI always enabled on IA64 */
93#define acpi_noirq 0 /* ACPI always enabled on IA64 */
94#define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
95#define acpi_strict 1 /* no ACPI spec workarounds on IA64 */
96#define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
97static inline void disable_acpi(void) { }
98
99const char *acpi_get_sysname (void);
100int acpi_request_vector (u32 int_type);
101int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
102
103/* routines for saving/restoring kernel state */
104extern int acpi_save_state_mem(void);
105extern void acpi_restore_state_mem(void);
106extern unsigned long acpi_wakeup_address;
107
108/*
109 * Record the cpei override flag and current logical cpu. This is
110 * useful for CPU removal.
111 */
112extern unsigned int can_cpei_retarget(void);
113extern unsigned int is_cpu_cpei_target(unsigned int cpu);
114extern void set_cpei_target_cpu(unsigned int cpu);
115extern unsigned int get_cpei_target_cpu(void);
116extern void prefill_possible_map(void);
117#ifdef CONFIG_ACPI_HOTPLUG_CPU
118extern int additional_cpus;
119#else
120#define additional_cpus 0
121#endif
122
123#ifdef CONFIG_ACPI_NUMA
124#if MAX_NUMNODES > 256
125#define MAX_PXM_DOMAINS MAX_NUMNODES
126#else
127#define MAX_PXM_DOMAINS (256)
128#endif
129extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
130extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
131#endif
132
133#define acpi_unlazy_tlb(x)
134
135#ifdef CONFIG_ACPI_NUMA
136extern cpumask_t early_cpu_possible_map;
137#define for_each_possible_early_cpu(cpu) \
138 for_each_cpu_mask((cpu), early_cpu_possible_map)
139
140static inline void per_cpu_scan_finalize(int min_cpus, int reserve_cpus)
141{
142 int low_cpu, high_cpu;
143 int cpu;
144 int next_nid = 0;
145
146 low_cpu = cpus_weight(early_cpu_possible_map);
147
148 high_cpu = max(low_cpu, min_cpus);
149 high_cpu = min(high_cpu + reserve_cpus, NR_CPUS);
150
151 for (cpu = low_cpu; cpu < high_cpu; cpu++) {
152 cpu_set(cpu, early_cpu_possible_map);
153 if (node_cpuid[cpu].nid == NUMA_NO_NODE) {
154 node_cpuid[cpu].nid = next_nid;
155 next_nid++;
156 if (next_nid >= num_online_nodes())
157 next_nid = 0;
158 }
159 }
160}
161#endif /* CONFIG_ACPI_NUMA */
162
163#endif /*__KERNEL__*/
164
165#endif /*_ASM_ACPI_H*/
diff --git a/arch/ia64/include/asm/agp.h b/arch/ia64/include/asm/agp.h
new file mode 100644
index 000000000000..c11fdd8ab4d7
--- /dev/null
+++ b/arch/ia64/include/asm/agp.h
@@ -0,0 +1,30 @@
1#ifndef _ASM_IA64_AGP_H
2#define _ASM_IA64_AGP_H
3
4/*
5 * IA-64 specific AGP definitions.
6 *
7 * Copyright (C) 2002-2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11/*
12 * To avoid memory-attribute aliasing issues, we require that the AGPGART engine operate
13 * in coherent mode, which lets us map the AGP memory as normal (write-back) memory
14 * (unlike x86, where it gets mapped "write-coalescing").
15 */
16#define map_page_into_agp(page) /* nothing */
17#define unmap_page_from_agp(page) /* nothing */
18#define flush_agp_cache() mb()
19
20/* Convert a physical address to an address suitable for the GART. */
21#define phys_to_gart(x) (x)
22#define gart_to_phys(x) (x)
23
24/* GATT allocation. Returns/accepts GATT kernel virtual address. */
25#define alloc_gatt_pages(order) \
26 ((char *)__get_free_pages(GFP_KERNEL, (order)))
27#define free_gatt_pages(table, order) \
28 free_pages((unsigned long)(table), (order))
29
30#endif /* _ASM_IA64_AGP_H */
diff --git a/arch/ia64/include/asm/asmmacro.h b/arch/ia64/include/asm/asmmacro.h
new file mode 100644
index 000000000000..c1642fd64029
--- /dev/null
+++ b/arch/ia64/include/asm/asmmacro.h
@@ -0,0 +1,135 @@
1#ifndef _ASM_IA64_ASMMACRO_H
2#define _ASM_IA64_ASMMACRO_H
3
4/*
5 * Copyright (C) 2000-2001, 2003-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#define ENTRY(name) \
11 .align 32; \
12 .proc name; \
13name:
14
15#define ENTRY_MIN_ALIGN(name) \
16 .align 16; \
17 .proc name; \
18name:
19
20#define GLOBAL_ENTRY(name) \
21 .global name; \
22 ENTRY(name)
23
24#define END(name) \
25 .endp name
26
27/*
28 * Helper macros to make unwind directives more readable:
29 */
30
31/* prologue_gr: */
32#define ASM_UNW_PRLG_RP 0x8
33#define ASM_UNW_PRLG_PFS 0x4
34#define ASM_UNW_PRLG_PSP 0x2
35#define ASM_UNW_PRLG_PR 0x1
36#define ASM_UNW_PRLG_GRSAVE(ninputs) (32+(ninputs))
37
38/*
39 * Helper macros for accessing user memory.
40 *
41 * When adding any new .section/.previous entries here, make sure to
42 * also add it to the DISCARD section in arch/ia64/kernel/gate.lds.S or
43 * unpleasant things will happen.
44 */
45
46 .section "__ex_table", "a" // declare section & section attributes
47 .previous
48
49# define EX(y,x...) \
50 .xdata4 "__ex_table", 99f-., y-.; \
51 [99:] x
52# define EXCLR(y,x...) \
53 .xdata4 "__ex_table", 99f-., y-.+4; \
54 [99:] x
55
56/*
57 * Tag MCA recoverable instruction ranges.
58 */
59
60 .section "__mca_table", "a" // declare section & section attributes
61 .previous
62
63# define MCA_RECOVER_RANGE(y) \
64 .xdata4 "__mca_table", y-., 99f-.; \
65 [99:]
66
67/*
68 * Mark instructions that need a load of a virtual address patched to be
69 * a load of a physical address. We use this either in critical performance
70 * path (ivt.S - TLB miss processing) or in places where it might not be
71 * safe to use a "tpa" instruction (mca_asm.S - error recovery).
72 */
73 .section ".data.patch.vtop", "a" // declare section & section attributes
74 .previous
75
76#define LOAD_PHYSICAL(pr, reg, obj) \
77[1:](pr)movl reg = obj; \
78 .xdata4 ".data.patch.vtop", 1b-.
79
80/*
81 * For now, we always put in the McKinley E9 workaround. On CPUs that don't need it,
82 * we'll patch out the work-around bundles with NOPs, so their impact is minimal.
83 */
84#define DO_MCKINLEY_E9_WORKAROUND
85
86#ifdef DO_MCKINLEY_E9_WORKAROUND
87 .section ".data.patch.mckinley_e9", "a"
88 .previous
89/* workaround for Itanium 2 Errata 9: */
90# define FSYS_RETURN \
91 .xdata4 ".data.patch.mckinley_e9", 1f-.; \
921:{ .mib; \
93 nop.m 0; \
94 mov r16=ar.pfs; \
95 br.call.sptk.many b7=2f;; \
96 }; \
972:{ .mib; \
98 nop.m 0; \
99 mov ar.pfs=r16; \
100 br.ret.sptk.many b6;; \
101 }
102#else
103# define FSYS_RETURN br.ret.sptk.many b6
104#endif
105
106/*
107 * If physical stack register size is different from DEF_NUM_STACK_REG,
108 * dynamically patch the kernel for correct size.
109 */
110 .section ".data.patch.phys_stack_reg", "a"
111 .previous
112#define LOAD_PHYS_STACK_REG_SIZE(reg) \
113[1:] adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0; \
114 .xdata4 ".data.patch.phys_stack_reg", 1b-.
115
116/*
117 * Up until early 2004, use of .align within a function caused bad unwind info.
118 * TEXT_ALIGN(n) expands into ".align n" if a fixed GAS is available or into nothing
119 * otherwise.
120 */
121#ifdef HAVE_WORKING_TEXT_ALIGN
122# define TEXT_ALIGN(n) .align n
123#else
124# define TEXT_ALIGN(n)
125#endif
126
127#ifdef HAVE_SERIALIZE_DIRECTIVE
128# define dv_serialize_data .serialize.data
129# define dv_serialize_instruction .serialize.instruction
130#else
131# define dv_serialize_data
132# define dv_serialize_instruction
133#endif
134
135#endif /* _ASM_IA64_ASMMACRO_H */
diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h
new file mode 100644
index 000000000000..50c2b83fd5a0
--- /dev/null
+++ b/arch/ia64/include/asm/atomic.h
@@ -0,0 +1,226 @@
1#ifndef _ASM_IA64_ATOMIC_H
2#define _ASM_IA64_ATOMIC_H
3
4/*
5 * Atomic operations that C can't guarantee us. Useful for
6 * resource counting etc..
7 *
8 * NOTE: don't mess with the types below! The "unsigned long" and
9 * "int" types were carefully placed so as to ensure proper operation
10 * of the macros.
11 *
12 * Copyright (C) 1998, 1999, 2002-2003 Hewlett-Packard Co
13 * David Mosberger-Tang <davidm@hpl.hp.com>
14 */
15#include <linux/types.h>
16
17#include <asm/intrinsics.h>
18#include <asm/system.h>
19
20/*
21 * On IA-64, counter must always be volatile to ensure that that the
22 * memory accesses are ordered.
23 */
24typedef struct { volatile __s32 counter; } atomic_t;
25typedef struct { volatile __s64 counter; } atomic64_t;
26
27#define ATOMIC_INIT(i) ((atomic_t) { (i) })
28#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
29
30#define atomic_read(v) ((v)->counter)
31#define atomic64_read(v) ((v)->counter)
32
33#define atomic_set(v,i) (((v)->counter) = (i))
34#define atomic64_set(v,i) (((v)->counter) = (i))
35
36static __inline__ int
37ia64_atomic_add (int i, atomic_t *v)
38{
39 __s32 old, new;
40 CMPXCHG_BUGCHECK_DECL
41
42 do {
43 CMPXCHG_BUGCHECK(v);
44 old = atomic_read(v);
45 new = old + i;
46 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
47 return new;
48}
49
50static __inline__ int
51ia64_atomic64_add (__s64 i, atomic64_t *v)
52{
53 __s64 old, new;
54 CMPXCHG_BUGCHECK_DECL
55
56 do {
57 CMPXCHG_BUGCHECK(v);
58 old = atomic64_read(v);
59 new = old + i;
60 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
61 return new;
62}
63
64static __inline__ int
65ia64_atomic_sub (int i, atomic_t *v)
66{
67 __s32 old, new;
68 CMPXCHG_BUGCHECK_DECL
69
70 do {
71 CMPXCHG_BUGCHECK(v);
72 old = atomic_read(v);
73 new = old - i;
74 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic_t)) != old);
75 return new;
76}
77
78static __inline__ int
79ia64_atomic64_sub (__s64 i, atomic64_t *v)
80{
81 __s64 old, new;
82 CMPXCHG_BUGCHECK_DECL
83
84 do {
85 CMPXCHG_BUGCHECK(v);
86 old = atomic64_read(v);
87 new = old - i;
88 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
89 return new;
90}
91
92#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
93#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
94
95#define atomic64_cmpxchg(v, old, new) \
96 (cmpxchg(&((v)->counter), old, new))
97#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
98
99static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
100{
101 int c, old;
102 c = atomic_read(v);
103 for (;;) {
104 if (unlikely(c == (u)))
105 break;
106 old = atomic_cmpxchg((v), c, c + (a));
107 if (likely(old == c))
108 break;
109 c = old;
110 }
111 return c != (u);
112}
113
114#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
115
116static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
117{
118 long c, old;
119 c = atomic64_read(v);
120 for (;;) {
121 if (unlikely(c == (u)))
122 break;
123 old = atomic64_cmpxchg((v), c, c + (a));
124 if (likely(old == c))
125 break;
126 c = old;
127 }
128 return c != (u);
129}
130
131#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
132
133#define atomic_add_return(i,v) \
134({ \
135 int __ia64_aar_i = (i); \
136 (__builtin_constant_p(i) \
137 && ( (__ia64_aar_i == 1) || (__ia64_aar_i == 4) \
138 || (__ia64_aar_i == 8) || (__ia64_aar_i == 16) \
139 || (__ia64_aar_i == -1) || (__ia64_aar_i == -4) \
140 || (__ia64_aar_i == -8) || (__ia64_aar_i == -16))) \
141 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
142 : ia64_atomic_add(__ia64_aar_i, v); \
143})
144
145#define atomic64_add_return(i,v) \
146({ \
147 long __ia64_aar_i = (i); \
148 (__builtin_constant_p(i) \
149 && ( (__ia64_aar_i == 1) || (__ia64_aar_i == 4) \
150 || (__ia64_aar_i == 8) || (__ia64_aar_i == 16) \
151 || (__ia64_aar_i == -1) || (__ia64_aar_i == -4) \
152 || (__ia64_aar_i == -8) || (__ia64_aar_i == -16))) \
153 ? ia64_fetch_and_add(__ia64_aar_i, &(v)->counter) \
154 : ia64_atomic64_add(__ia64_aar_i, v); \
155})
156
157/*
158 * Atomically add I to V and return TRUE if the resulting value is
159 * negative.
160 */
161static __inline__ int
162atomic_add_negative (int i, atomic_t *v)
163{
164 return atomic_add_return(i, v) < 0;
165}
166
167static __inline__ int
168atomic64_add_negative (__s64 i, atomic64_t *v)
169{
170 return atomic64_add_return(i, v) < 0;
171}
172
173#define atomic_sub_return(i,v) \
174({ \
175 int __ia64_asr_i = (i); \
176 (__builtin_constant_p(i) \
177 && ( (__ia64_asr_i == 1) || (__ia64_asr_i == 4) \
178 || (__ia64_asr_i == 8) || (__ia64_asr_i == 16) \
179 || (__ia64_asr_i == -1) || (__ia64_asr_i == -4) \
180 || (__ia64_asr_i == -8) || (__ia64_asr_i == -16))) \
181 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
182 : ia64_atomic_sub(__ia64_asr_i, v); \
183})
184
185#define atomic64_sub_return(i,v) \
186({ \
187 long __ia64_asr_i = (i); \
188 (__builtin_constant_p(i) \
189 && ( (__ia64_asr_i == 1) || (__ia64_asr_i == 4) \
190 || (__ia64_asr_i == 8) || (__ia64_asr_i == 16) \
191 || (__ia64_asr_i == -1) || (__ia64_asr_i == -4) \
192 || (__ia64_asr_i == -8) || (__ia64_asr_i == -16))) \
193 ? ia64_fetch_and_add(-__ia64_asr_i, &(v)->counter) \
194 : ia64_atomic64_sub(__ia64_asr_i, v); \
195})
196
197#define atomic_dec_return(v) atomic_sub_return(1, (v))
198#define atomic_inc_return(v) atomic_add_return(1, (v))
199#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
200#define atomic64_inc_return(v) atomic64_add_return(1, (v))
201
202#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
203#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
204#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
205#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
206#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
207#define atomic64_inc_and_test(v) (atomic64_add_return(1, (v)) == 0)
208
209#define atomic_add(i,v) atomic_add_return((i), (v))
210#define atomic_sub(i,v) atomic_sub_return((i), (v))
211#define atomic_inc(v) atomic_add(1, (v))
212#define atomic_dec(v) atomic_sub(1, (v))
213
214#define atomic64_add(i,v) atomic64_add_return((i), (v))
215#define atomic64_sub(i,v) atomic64_sub_return((i), (v))
216#define atomic64_inc(v) atomic64_add(1, (v))
217#define atomic64_dec(v) atomic64_sub(1, (v))
218
219/* Atomic operations are already serializing */
220#define smp_mb__before_atomic_dec() barrier()
221#define smp_mb__after_atomic_dec() barrier()
222#define smp_mb__before_atomic_inc() barrier()
223#define smp_mb__after_atomic_inc() barrier()
224
225#include <asm-generic/atomic.h>
226#endif /* _ASM_IA64_ATOMIC_H */
diff --git a/arch/ia64/include/asm/auxvec.h b/arch/ia64/include/asm/auxvec.h
new file mode 100644
index 000000000000..23cebe5685b9
--- /dev/null
+++ b/arch/ia64/include/asm/auxvec.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_IA64_AUXVEC_H
2#define _ASM_IA64_AUXVEC_H
3
4/*
5 * Architecture-neutral AT_ values are in the range 0-17. Leave some room for more of
6 * them, start the architecture-specific ones at 32.
7 */
8#define AT_SYSINFO 32
9#define AT_SYSINFO_EHDR 33
10
11#endif /* _ASM_IA64_AUXVEC_H */
diff --git a/arch/ia64/include/asm/bitops.h b/arch/ia64/include/asm/bitops.h
new file mode 100644
index 000000000000..e2ca80037335
--- /dev/null
+++ b/arch/ia64/include/asm/bitops.h
@@ -0,0 +1,468 @@
1#ifndef _ASM_IA64_BITOPS_H
2#define _ASM_IA64_BITOPS_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
9 * O(1) scheduler patch
10 */
11
12#ifndef _LINUX_BITOPS_H
13#error only <linux/bitops.h> can be included directly
14#endif
15
16#include <linux/compiler.h>
17#include <linux/types.h>
18#include <asm/intrinsics.h>
19
20/**
21 * set_bit - Atomically set a bit in memory
22 * @nr: the bit to set
23 * @addr: the address to start counting from
24 *
25 * This function is atomic and may not be reordered. See __set_bit()
26 * if you do not require the atomic guarantees.
27 * Note that @nr may be almost arbitrarily large; this function is not
28 * restricted to acting on a single-word quantity.
29 *
30 * The address must be (at least) "long" aligned.
31 * Note that there are driver (e.g., eepro100) which use these operations to
32 * operate on hw-defined data-structures, so we can't easily change these
33 * operations to force a bigger alignment.
34 *
35 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
36 */
37static __inline__ void
38set_bit (int nr, volatile void *addr)
39{
40 __u32 bit, old, new;
41 volatile __u32 *m;
42 CMPXCHG_BUGCHECK_DECL
43
44 m = (volatile __u32 *) addr + (nr >> 5);
45 bit = 1 << (nr & 31);
46 do {
47 CMPXCHG_BUGCHECK(m);
48 old = *m;
49 new = old | bit;
50 } while (cmpxchg_acq(m, old, new) != old);
51}
52
53/**
54 * __set_bit - Set a bit in memory
55 * @nr: the bit to set
56 * @addr: the address to start counting from
57 *
58 * Unlike set_bit(), this function is non-atomic and may be reordered.
59 * If it's called on the same region of memory simultaneously, the effect
60 * may be that only one operation succeeds.
61 */
62static __inline__ void
63__set_bit (int nr, volatile void *addr)
64{
65 *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
66}
67
68/*
69 * clear_bit() has "acquire" semantics.
70 */
71#define smp_mb__before_clear_bit() smp_mb()
72#define smp_mb__after_clear_bit() do { /* skip */; } while (0)
73
74/**
75 * clear_bit - Clears a bit in memory
76 * @nr: Bit to clear
77 * @addr: Address to start counting from
78 *
79 * clear_bit() is atomic and may not be reordered. However, it does
80 * not contain a memory barrier, so if it is used for locking purposes,
81 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
82 * in order to ensure changes are visible on other processors.
83 */
84static __inline__ void
85clear_bit (int nr, volatile void *addr)
86{
87 __u32 mask, old, new;
88 volatile __u32 *m;
89 CMPXCHG_BUGCHECK_DECL
90
91 m = (volatile __u32 *) addr + (nr >> 5);
92 mask = ~(1 << (nr & 31));
93 do {
94 CMPXCHG_BUGCHECK(m);
95 old = *m;
96 new = old & mask;
97 } while (cmpxchg_acq(m, old, new) != old);
98}
99
100/**
101 * clear_bit_unlock - Clears a bit in memory with release
102 * @nr: Bit to clear
103 * @addr: Address to start counting from
104 *
105 * clear_bit_unlock() is atomic and may not be reordered. It does
106 * contain a memory barrier suitable for unlock type operations.
107 */
108static __inline__ void
109clear_bit_unlock (int nr, volatile void *addr)
110{
111 __u32 mask, old, new;
112 volatile __u32 *m;
113 CMPXCHG_BUGCHECK_DECL
114
115 m = (volatile __u32 *) addr + (nr >> 5);
116 mask = ~(1 << (nr & 31));
117 do {
118 CMPXCHG_BUGCHECK(m);
119 old = *m;
120 new = old & mask;
121 } while (cmpxchg_rel(m, old, new) != old);
122}
123
124/**
125 * __clear_bit_unlock - Non-atomically clears a bit in memory with release
126 * @nr: Bit to clear
127 * @addr: Address to start counting from
128 *
129 * Similarly to clear_bit_unlock, the implementation uses a store
130 * with release semantics. See also __raw_spin_unlock().
131 */
132static __inline__ void
133__clear_bit_unlock(int nr, void *addr)
134{
135 __u32 * const m = (__u32 *) addr + (nr >> 5);
136 __u32 const new = *m & ~(1 << (nr & 31));
137
138 ia64_st4_rel_nta(m, new);
139}
140
141/**
142 * __clear_bit - Clears a bit in memory (non-atomic version)
143 * @nr: the bit to clear
144 * @addr: the address to start counting from
145 *
146 * Unlike clear_bit(), this function is non-atomic and may be reordered.
147 * If it's called on the same region of memory simultaneously, the effect
148 * may be that only one operation succeeds.
149 */
150static __inline__ void
151__clear_bit (int nr, volatile void *addr)
152{
153 *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
154}
155
156/**
157 * change_bit - Toggle a bit in memory
158 * @nr: Bit to toggle
159 * @addr: Address to start counting from
160 *
161 * change_bit() is atomic and may not be reordered.
162 * Note that @nr may be almost arbitrarily large; this function is not
163 * restricted to acting on a single-word quantity.
164 */
165static __inline__ void
166change_bit (int nr, volatile void *addr)
167{
168 __u32 bit, old, new;
169 volatile __u32 *m;
170 CMPXCHG_BUGCHECK_DECL
171
172 m = (volatile __u32 *) addr + (nr >> 5);
173 bit = (1 << (nr & 31));
174 do {
175 CMPXCHG_BUGCHECK(m);
176 old = *m;
177 new = old ^ bit;
178 } while (cmpxchg_acq(m, old, new) != old);
179}
180
181/**
182 * __change_bit - Toggle a bit in memory
183 * @nr: the bit to toggle
184 * @addr: the address to start counting from
185 *
186 * Unlike change_bit(), this function is non-atomic and may be reordered.
187 * If it's called on the same region of memory simultaneously, the effect
188 * may be that only one operation succeeds.
189 */
190static __inline__ void
191__change_bit (int nr, volatile void *addr)
192{
193 *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
194}
195
196/**
197 * test_and_set_bit - Set a bit and return its old value
198 * @nr: Bit to set
199 * @addr: Address to count from
200 *
201 * This operation is atomic and cannot be reordered.
202 * It also implies the acquisition side of the memory barrier.
203 */
204static __inline__ int
205test_and_set_bit (int nr, volatile void *addr)
206{
207 __u32 bit, old, new;
208 volatile __u32 *m;
209 CMPXCHG_BUGCHECK_DECL
210
211 m = (volatile __u32 *) addr + (nr >> 5);
212 bit = 1 << (nr & 31);
213 do {
214 CMPXCHG_BUGCHECK(m);
215 old = *m;
216 new = old | bit;
217 } while (cmpxchg_acq(m, old, new) != old);
218 return (old & bit) != 0;
219}
220
221/**
222 * test_and_set_bit_lock - Set a bit and return its old value for lock
223 * @nr: Bit to set
224 * @addr: Address to count from
225 *
226 * This is the same as test_and_set_bit on ia64
227 */
228#define test_and_set_bit_lock test_and_set_bit
229
230/**
231 * __test_and_set_bit - Set a bit and return its old value
232 * @nr: Bit to set
233 * @addr: Address to count from
234 *
235 * This operation is non-atomic and can be reordered.
236 * If two examples of this operation race, one can appear to succeed
237 * but actually fail. You must protect multiple accesses with a lock.
238 */
239static __inline__ int
240__test_and_set_bit (int nr, volatile void *addr)
241{
242 __u32 *p = (__u32 *) addr + (nr >> 5);
243 __u32 m = 1 << (nr & 31);
244 int oldbitset = (*p & m) != 0;
245
246 *p |= m;
247 return oldbitset;
248}
249
250/**
251 * test_and_clear_bit - Clear a bit and return its old value
252 * @nr: Bit to clear
253 * @addr: Address to count from
254 *
255 * This operation is atomic and cannot be reordered.
256 * It also implies the acquisition side of the memory barrier.
257 */
258static __inline__ int
259test_and_clear_bit (int nr, volatile void *addr)
260{
261 __u32 mask, old, new;
262 volatile __u32 *m;
263 CMPXCHG_BUGCHECK_DECL
264
265 m = (volatile __u32 *) addr + (nr >> 5);
266 mask = ~(1 << (nr & 31));
267 do {
268 CMPXCHG_BUGCHECK(m);
269 old = *m;
270 new = old & mask;
271 } while (cmpxchg_acq(m, old, new) != old);
272 return (old & ~mask) != 0;
273}
274
275/**
276 * __test_and_clear_bit - Clear a bit and return its old value
277 * @nr: Bit to clear
278 * @addr: Address to count from
279 *
280 * This operation is non-atomic and can be reordered.
281 * If two examples of this operation race, one can appear to succeed
282 * but actually fail. You must protect multiple accesses with a lock.
283 */
284static __inline__ int
285__test_and_clear_bit(int nr, volatile void * addr)
286{
287 __u32 *p = (__u32 *) addr + (nr >> 5);
288 __u32 m = 1 << (nr & 31);
289 int oldbitset = *p & m;
290
291 *p &= ~m;
292 return oldbitset;
293}
294
295/**
296 * test_and_change_bit - Change a bit and return its old value
297 * @nr: Bit to change
298 * @addr: Address to count from
299 *
300 * This operation is atomic and cannot be reordered.
301 * It also implies the acquisition side of the memory barrier.
302 */
303static __inline__ int
304test_and_change_bit (int nr, volatile void *addr)
305{
306 __u32 bit, old, new;
307 volatile __u32 *m;
308 CMPXCHG_BUGCHECK_DECL
309
310 m = (volatile __u32 *) addr + (nr >> 5);
311 bit = (1 << (nr & 31));
312 do {
313 CMPXCHG_BUGCHECK(m);
314 old = *m;
315 new = old ^ bit;
316 } while (cmpxchg_acq(m, old, new) != old);
317 return (old & bit) != 0;
318}
319
320/**
321 * __test_and_change_bit - Change a bit and return its old value
322 * @nr: Bit to change
323 * @addr: Address to count from
324 *
325 * This operation is non-atomic and can be reordered.
326 */
327static __inline__ int
328__test_and_change_bit (int nr, void *addr)
329{
330 __u32 old, bit = (1 << (nr & 31));
331 __u32 *m = (__u32 *) addr + (nr >> 5);
332
333 old = *m;
334 *m = old ^ bit;
335 return (old & bit) != 0;
336}
337
338static __inline__ int
339test_bit (int nr, const volatile void *addr)
340{
341 return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
342}
343
344/**
345 * ffz - find the first zero bit in a long word
346 * @x: The long word to find the bit in
347 *
348 * Returns the bit-number (0..63) of the first (least significant) zero bit.
349 * Undefined if no zero exists, so code should check against ~0UL first...
350 */
351static inline unsigned long
352ffz (unsigned long x)
353{
354 unsigned long result;
355
356 result = ia64_popcnt(x & (~x - 1));
357 return result;
358}
359
360/**
361 * __ffs - find first bit in word.
362 * @x: The word to search
363 *
364 * Undefined if no bit exists, so code should check against 0 first.
365 */
366static __inline__ unsigned long
367__ffs (unsigned long x)
368{
369 unsigned long result;
370
371 result = ia64_popcnt((x-1) & ~x);
372 return result;
373}
374
375#ifdef __KERNEL__
376
377/*
378 * Return bit number of last (most-significant) bit set. Undefined
379 * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
380 */
381static inline unsigned long
382ia64_fls (unsigned long x)
383{
384 long double d = x;
385 long exp;
386
387 exp = ia64_getf_exp(d);
388 return exp - 0xffff;
389}
390
391/*
392 * Find the last (most significant) bit set. Returns 0 for x==0 and
393 * bits are numbered from 1..32 (e.g., fls(9) == 4).
394 */
395static inline int
396fls (int t)
397{
398 unsigned long x = t & 0xffffffffu;
399
400 if (!x)
401 return 0;
402 x |= x >> 1;
403 x |= x >> 2;
404 x |= x >> 4;
405 x |= x >> 8;
406 x |= x >> 16;
407 return ia64_popcnt(x);
408}
409
410/*
411 * Find the last (most significant) bit set. Undefined for x==0.
412 * Bits are numbered from 0..63 (e.g., __fls(9) == 3).
413 */
414static inline unsigned long
415__fls (unsigned long x)
416{
417 x |= x >> 1;
418 x |= x >> 2;
419 x |= x >> 4;
420 x |= x >> 8;
421 x |= x >> 16;
422 x |= x >> 32;
423 return ia64_popcnt(x) - 1;
424}
425
426#include <asm-generic/bitops/fls64.h>
427
428/*
429 * ffs: find first bit set. This is defined the same way as the libc and
430 * compiler builtin ffs routines, therefore differs in spirit from the above
431 * ffz (man ffs): it operates on "int" values only and the result value is the
432 * bit number + 1. ffs(0) is defined to return zero.
433 */
434#define ffs(x) __builtin_ffs(x)
435
436/*
437 * hweightN: returns the hamming weight (i.e. the number
438 * of bits set) of a N-bit word
439 */
440static __inline__ unsigned long
441hweight64 (unsigned long x)
442{
443 unsigned long result;
444 result = ia64_popcnt(x);
445 return result;
446}
447
448#define hweight32(x) (unsigned int) hweight64((x) & 0xfffffffful)
449#define hweight16(x) (unsigned int) hweight64((x) & 0xfffful)
450#define hweight8(x) (unsigned int) hweight64((x) & 0xfful)
451
452#endif /* __KERNEL__ */
453
454#include <asm-generic/bitops/find.h>
455
456#ifdef __KERNEL__
457
458#include <asm-generic/bitops/ext2-non-atomic.h>
459
460#define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a)
461#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
462
463#include <asm-generic/bitops/minix.h>
464#include <asm-generic/bitops/sched.h>
465
466#endif /* __KERNEL__ */
467
468#endif /* _ASM_IA64_BITOPS_H */
diff --git a/arch/ia64/include/asm/break.h b/arch/ia64/include/asm/break.h
new file mode 100644
index 000000000000..f03402039896
--- /dev/null
+++ b/arch/ia64/include/asm/break.h
@@ -0,0 +1,23 @@
1#ifndef _ASM_IA64_BREAK_H
2#define _ASM_IA64_BREAK_H
3
4/*
5 * IA-64 Linux break numbers.
6 *
7 * Copyright (C) 1999 Hewlett-Packard Co
8 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11/*
12 * OS-specific debug break numbers:
13 */
14#define __IA64_BREAK_KDB 0x80100
15#define __IA64_BREAK_KPROBE 0x81000 /* .. 0x81fff */
16#define __IA64_BREAK_JPROBE 0x82000
17
18/*
19 * OS-specific break numbers:
20 */
21#define __IA64_BREAK_SYSCALL 0x100000
22
23#endif /* _ASM_IA64_BREAK_H */
diff --git a/arch/ia64/include/asm/bug.h b/arch/ia64/include/asm/bug.h
new file mode 100644
index 000000000000..823616b5020b
--- /dev/null
+++ b/arch/ia64/include/asm/bug.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_IA64_BUG_H
2#define _ASM_IA64_BUG_H
3
4#ifdef CONFIG_BUG
5#define ia64_abort() __builtin_trap()
6#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
7
8/* should this BUG be made generic? */
9#define HAVE_ARCH_BUG
10#endif
11
12#include <asm-generic/bug.h>
13
14#endif
diff --git a/arch/ia64/include/asm/bugs.h b/arch/ia64/include/asm/bugs.h
new file mode 100644
index 000000000000..433523e3b2ed
--- /dev/null
+++ b/arch/ia64/include/asm/bugs.h
@@ -0,0 +1,19 @@
1/*
2 * This is included by init/main.c to check for architecture-dependent bugs.
3 *
4 * Needs:
5 * void check_bugs(void);
6 *
7 * Based on <asm-alpha/bugs.h>.
8 *
9 * Modified 1998, 1999, 2003
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
11 */
12#ifndef _ASM_IA64_BUGS_H
13#define _ASM_IA64_BUGS_H
14
15#include <asm/processor.h>
16
17extern void check_bugs (void);
18
19#endif /* _ASM_IA64_BUGS_H */
diff --git a/arch/ia64/include/asm/byteorder.h b/arch/ia64/include/asm/byteorder.h
new file mode 100644
index 000000000000..69bd41d7c26e
--- /dev/null
+++ b/arch/ia64/include/asm/byteorder.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_IA64_BYTEORDER_H
2#define _ASM_IA64_BYTEORDER_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
7 */
8
9#include <asm/types.h>
10#include <asm/intrinsics.h>
11#include <linux/compiler.h>
12
13static __inline__ __attribute_const__ __u64
14__ia64_swab64 (__u64 x)
15{
16 __u64 result;
17
18 result = ia64_mux1(x, ia64_mux1_rev);
19 return result;
20}
21
22static __inline__ __attribute_const__ __u32
23__ia64_swab32 (__u32 x)
24{
25 return __ia64_swab64(x) >> 32;
26}
27
28static __inline__ __attribute_const__ __u16
29__ia64_swab16(__u16 x)
30{
31 return __ia64_swab64(x) >> 48;
32}
33
34#define __arch__swab64(x) __ia64_swab64(x)
35#define __arch__swab32(x) __ia64_swab32(x)
36#define __arch__swab16(x) __ia64_swab16(x)
37
38#define __BYTEORDER_HAS_U64__
39
40#include <linux/byteorder/little_endian.h>
41
42#endif /* _ASM_IA64_BYTEORDER_H */
diff --git a/arch/ia64/include/asm/cache.h b/arch/ia64/include/asm/cache.h
new file mode 100644
index 000000000000..e7482bd628ff
--- /dev/null
+++ b/arch/ia64/include/asm/cache.h
@@ -0,0 +1,29 @@
1#ifndef _ASM_IA64_CACHE_H
2#define _ASM_IA64_CACHE_H
3
4
5/*
6 * Copyright (C) 1998-2000 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9
10/* Bytes per L1 (data) cache line. */
11#define L1_CACHE_SHIFT CONFIG_IA64_L1_CACHE_SHIFT
12#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
13
14#ifdef CONFIG_SMP
15# define SMP_CACHE_SHIFT L1_CACHE_SHIFT
16# define SMP_CACHE_BYTES L1_CACHE_BYTES
17#else
18 /*
19 * The "aligned" directive can only _increase_ alignment, so this is
20 * safe and provides an easy way to avoid wasting space on a
21 * uni-processor:
22 */
23# define SMP_CACHE_SHIFT 3
24# define SMP_CACHE_BYTES (1 << 3)
25#endif
26
27#define __read_mostly __attribute__((__section__(".data.read_mostly")))
28
29#endif /* _ASM_IA64_CACHE_H */
diff --git a/arch/ia64/include/asm/cacheflush.h b/arch/ia64/include/asm/cacheflush.h
new file mode 100644
index 000000000000..afcfbda76e20
--- /dev/null
+++ b/arch/ia64/include/asm/cacheflush.h
@@ -0,0 +1,51 @@
1#ifndef _ASM_IA64_CACHEFLUSH_H
2#define _ASM_IA64_CACHEFLUSH_H
3
4/*
5 * Copyright (C) 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <linux/page-flags.h>
10#include <linux/bitops.h>
11
12#include <asm/page.h>
13
14/*
15 * Cache flushing routines. This is the kind of stuff that can be very expensive, so try
16 * to avoid them whenever possible.
17 */
18
19#define flush_cache_all() do { } while (0)
20#define flush_cache_mm(mm) do { } while (0)
21#define flush_cache_dup_mm(mm) do { } while (0)
22#define flush_cache_range(vma, start, end) do { } while (0)
23#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
24#define flush_icache_page(vma,page) do { } while (0)
25#define flush_cache_vmap(start, end) do { } while (0)
26#define flush_cache_vunmap(start, end) do { } while (0)
27
28#define flush_dcache_page(page) \
29do { \
30 clear_bit(PG_arch_1, &(page)->flags); \
31} while (0)
32
33#define flush_dcache_mmap_lock(mapping) do { } while (0)
34#define flush_dcache_mmap_unlock(mapping) do { } while (0)
35
36extern void flush_icache_range (unsigned long start, unsigned long end);
37
38#define flush_icache_user_range(vma, page, user_addr, len) \
39do { \
40 unsigned long _addr = (unsigned long) page_address(page) + ((user_addr) & ~PAGE_MASK); \
41 flush_icache_range(_addr, _addr + (len)); \
42} while (0)
43
44#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
45do { memcpy(dst, src, len); \
46 flush_icache_user_range(vma, page, vaddr, len); \
47} while (0)
48#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
49 memcpy(dst, src, len)
50
51#endif /* _ASM_IA64_CACHEFLUSH_H */
diff --git a/arch/ia64/include/asm/checksum.h b/arch/ia64/include/asm/checksum.h
new file mode 100644
index 000000000000..97af155057e4
--- /dev/null
+++ b/arch/ia64/include/asm/checksum.h
@@ -0,0 +1,79 @@
1#ifndef _ASM_IA64_CHECKSUM_H
2#define _ASM_IA64_CHECKSUM_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9/*
10 * This is a version of ip_compute_csum() optimized for IP headers,
11 * which always checksum on 4 octet boundaries.
12 */
13extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
14
15/*
16 * Computes the checksum of the TCP/UDP pseudo-header returns a 16-bit
17 * checksum, already complemented
18 */
19extern __sum16 csum_tcpudp_magic (__be32 saddr, __be32 daddr,
20 unsigned short len,
21 unsigned short proto,
22 __wsum sum);
23
24extern __wsum csum_tcpudp_nofold (__be32 saddr, __be32 daddr,
25 unsigned short len,
26 unsigned short proto,
27 __wsum sum);
28
29/*
30 * Computes the checksum of a memory block at buff, length len,
31 * and adds in "sum" (32-bit)
32 *
33 * returns a 32-bit number suitable for feeding into itself
34 * or csum_tcpudp_magic
35 *
36 * this function must be called with even lengths, except
37 * for the last fragment, which may be odd
38 *
39 * it's best to have buff aligned on a 32-bit boundary
40 */
41extern __wsum csum_partial(const void *buff, int len, __wsum sum);
42
43/*
44 * Same as csum_partial, but copies from src while it checksums.
45 *
46 * Here it is even more important to align src and dst on a 32-bit (or
47 * even better 64-bit) boundary.
48 */
49extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
50 int len, __wsum sum,
51 int *errp);
52
53extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
54 int len, __wsum sum);
55
56/*
57 * This routine is used for miscellaneous IP-like checksums, mainly in
58 * icmp.c
59 */
60extern __sum16 ip_compute_csum(const void *buff, int len);
61
62/*
63 * Fold a partial checksum without adding pseudo headers.
64 */
65static inline __sum16 csum_fold(__wsum csum)
66{
67 u32 sum = (__force u32)csum;
68 sum = (sum & 0xffff) + (sum >> 16);
69 sum = (sum & 0xffff) + (sum >> 16);
70 return (__force __sum16)~sum;
71}
72
73#define _HAVE_ARCH_IPV6_CSUM 1
74struct in6_addr;
75extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
76 const struct in6_addr *daddr, __u32 len, unsigned short proto,
77 __wsum csum);
78
79#endif /* _ASM_IA64_CHECKSUM_H */
diff --git a/arch/ia64/include/asm/compat.h b/arch/ia64/include/asm/compat.h
new file mode 100644
index 000000000000..dfcf75b8426d
--- /dev/null
+++ b/arch/ia64/include/asm/compat.h
@@ -0,0 +1,207 @@
1#ifndef _ASM_IA64_COMPAT_H
2#define _ASM_IA64_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7
8#define COMPAT_USER_HZ 100
9
10typedef u32 compat_size_t;
11typedef s32 compat_ssize_t;
12typedef s32 compat_time_t;
13typedef s32 compat_clock_t;
14typedef s32 compat_key_t;
15typedef s32 compat_pid_t;
16typedef u16 __compat_uid_t;
17typedef u16 __compat_gid_t;
18typedef u32 __compat_uid32_t;
19typedef u32 __compat_gid32_t;
20typedef u16 compat_mode_t;
21typedef u32 compat_ino_t;
22typedef u16 compat_dev_t;
23typedef s32 compat_off_t;
24typedef s64 compat_loff_t;
25typedef u16 compat_nlink_t;
26typedef u16 compat_ipc_pid_t;
27typedef s32 compat_daddr_t;
28typedef u32 compat_caddr_t;
29typedef __kernel_fsid_t compat_fsid_t;
30typedef s32 compat_timer_t;
31
32typedef s32 compat_int_t;
33typedef s32 compat_long_t;
34typedef s64 __attribute__((aligned(4))) compat_s64;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37typedef u64 __attribute__((aligned(4))) compat_u64;
38
39struct compat_timespec {
40 compat_time_t tv_sec;
41 s32 tv_nsec;
42};
43
44struct compat_timeval {
45 compat_time_t tv_sec;
46 s32 tv_usec;
47};
48
49struct compat_stat {
50 compat_dev_t st_dev;
51 u16 __pad1;
52 compat_ino_t st_ino;
53 compat_mode_t st_mode;
54 compat_nlink_t st_nlink;
55 __compat_uid_t st_uid;
56 __compat_gid_t st_gid;
57 compat_dev_t st_rdev;
58 u16 __pad2;
59 u32 st_size;
60 u32 st_blksize;
61 u32 st_blocks;
62 u32 st_atime;
63 u32 st_atime_nsec;
64 u32 st_mtime;
65 u32 st_mtime_nsec;
66 u32 st_ctime;
67 u32 st_ctime_nsec;
68 u32 __unused4;
69 u32 __unused5;
70};
71
72struct compat_flock {
73 short l_type;
74 short l_whence;
75 compat_off_t l_start;
76 compat_off_t l_len;
77 compat_pid_t l_pid;
78};
79
80#define F_GETLK64 12
81#define F_SETLK64 13
82#define F_SETLKW64 14
83
84/*
85 * IA32 uses 4 byte alignment for 64 bit quantities,
86 * so we need to pack this structure.
87 */
88struct compat_flock64 {
89 short l_type;
90 short l_whence;
91 compat_loff_t l_start;
92 compat_loff_t l_len;
93 compat_pid_t l_pid;
94} __attribute__((packed));
95
96struct compat_statfs {
97 int f_type;
98 int f_bsize;
99 int f_blocks;
100 int f_bfree;
101 int f_bavail;
102 int f_files;
103 int f_ffree;
104 compat_fsid_t f_fsid;
105 int f_namelen; /* SunOS ignores this field. */
106 int f_frsize;
107 int f_spare[5];
108};
109
110#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
111#define COMPAT_RLIM_INFINITY 0xffffffff
112
113typedef u32 compat_old_sigset_t; /* at least 32 bits */
114
115#define _COMPAT_NSIG 64
116#define _COMPAT_NSIG_BPW 32
117
118typedef u32 compat_sigset_word;
119
120#define COMPAT_OFF_T_MAX 0x7fffffff
121#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
122
123struct compat_ipc64_perm {
124 compat_key_t key;
125 __compat_uid32_t uid;
126 __compat_gid32_t gid;
127 __compat_uid32_t cuid;
128 __compat_gid32_t cgid;
129 unsigned short mode;
130 unsigned short __pad1;
131 unsigned short seq;
132 unsigned short __pad2;
133 compat_ulong_t unused1;
134 compat_ulong_t unused2;
135};
136
137struct compat_semid64_ds {
138 struct compat_ipc64_perm sem_perm;
139 compat_time_t sem_otime;
140 compat_ulong_t __unused1;
141 compat_time_t sem_ctime;
142 compat_ulong_t __unused2;
143 compat_ulong_t sem_nsems;
144 compat_ulong_t __unused3;
145 compat_ulong_t __unused4;
146};
147
148struct compat_msqid64_ds {
149 struct compat_ipc64_perm msg_perm;
150 compat_time_t msg_stime;
151 compat_ulong_t __unused1;
152 compat_time_t msg_rtime;
153 compat_ulong_t __unused2;
154 compat_time_t msg_ctime;
155 compat_ulong_t __unused3;
156 compat_ulong_t msg_cbytes;
157 compat_ulong_t msg_qnum;
158 compat_ulong_t msg_qbytes;
159 compat_pid_t msg_lspid;
160 compat_pid_t msg_lrpid;
161 compat_ulong_t __unused4;
162 compat_ulong_t __unused5;
163};
164
165struct compat_shmid64_ds {
166 struct compat_ipc64_perm shm_perm;
167 compat_size_t shm_segsz;
168 compat_time_t shm_atime;
169 compat_ulong_t __unused1;
170 compat_time_t shm_dtime;
171 compat_ulong_t __unused2;
172 compat_time_t shm_ctime;
173 compat_ulong_t __unused3;
174 compat_pid_t shm_cpid;
175 compat_pid_t shm_lpid;
176 compat_ulong_t shm_nattch;
177 compat_ulong_t __unused4;
178 compat_ulong_t __unused5;
179};
180
181/*
182 * A pointer passed in from user mode. This should not be used for syscall parameters,
183 * just declare them as pointers because the syscall entry code will have appropriately
184 * converted them already.
185 */
186typedef u32 compat_uptr_t;
187
188static inline void __user *
189compat_ptr (compat_uptr_t uptr)
190{
191 return (void __user *) (unsigned long) uptr;
192}
193
194static inline compat_uptr_t
195ptr_to_compat(void __user *uptr)
196{
197 return (u32)(unsigned long)uptr;
198}
199
200static __inline__ void __user *
201compat_alloc_user_space (long len)
202{
203 struct pt_regs *regs = task_pt_regs(current);
204 return (void __user *) (((regs->r12 & 0xffffffff) & -16) - len);
205}
206
207#endif /* _ASM_IA64_COMPAT_H */
diff --git a/arch/ia64/include/asm/cpu.h b/arch/ia64/include/asm/cpu.h
new file mode 100644
index 000000000000..fcca30b9f110
--- /dev/null
+++ b/arch/ia64/include/asm/cpu.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_IA64_CPU_H_
2#define _ASM_IA64_CPU_H_
3
4#include <linux/device.h>
5#include <linux/cpu.h>
6#include <linux/topology.h>
7#include <linux/percpu.h>
8
9struct ia64_cpu {
10 struct cpu cpu;
11};
12
13DECLARE_PER_CPU(struct ia64_cpu, cpu_devices);
14
15DECLARE_PER_CPU(int, cpu_state);
16
17#ifdef CONFIG_HOTPLUG_CPU
18extern int arch_register_cpu(int num);
19extern void arch_unregister_cpu(int);
20#endif
21
22#endif /* _ASM_IA64_CPU_H_ */
diff --git a/arch/ia64/include/asm/cputime.h b/arch/ia64/include/asm/cputime.h
new file mode 100644
index 000000000000..d20b998cb91d
--- /dev/null
+++ b/arch/ia64/include/asm/cputime.h
@@ -0,0 +1,109 @@
1/*
2 * Definitions for measuring cputime on ia64 machines.
3 *
4 * Based on <asm-powerpc/cputime.h>.
5 *
6 * Copyright (C) 2007 FUJITSU LIMITED
7 * Copyright (C) 2007 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * If we have CONFIG_VIRT_CPU_ACCOUNTING, we measure cpu time in nsec.
15 * Otherwise we measure cpu time in jiffies using the generic definitions.
16 */
17
18#ifndef __IA64_CPUTIME_H
19#define __IA64_CPUTIME_H
20
21#ifndef CONFIG_VIRT_CPU_ACCOUNTING
22#include <asm-generic/cputime.h>
23#else
24
25#include <linux/time.h>
26#include <linux/jiffies.h>
27#include <asm/processor.h>
28
29typedef u64 cputime_t;
30typedef u64 cputime64_t;
31
32#define cputime_zero ((cputime_t)0)
33#define cputime_max ((~((cputime_t)0) >> 1) - 1)
34#define cputime_add(__a, __b) ((__a) + (__b))
35#define cputime_sub(__a, __b) ((__a) - (__b))
36#define cputime_div(__a, __n) ((__a) / (__n))
37#define cputime_halve(__a) ((__a) >> 1)
38#define cputime_eq(__a, __b) ((__a) == (__b))
39#define cputime_gt(__a, __b) ((__a) > (__b))
40#define cputime_ge(__a, __b) ((__a) >= (__b))
41#define cputime_lt(__a, __b) ((__a) < (__b))
42#define cputime_le(__a, __b) ((__a) <= (__b))
43
44#define cputime64_zero ((cputime64_t)0)
45#define cputime64_add(__a, __b) ((__a) + (__b))
46#define cputime64_sub(__a, __b) ((__a) - (__b))
47#define cputime_to_cputime64(__ct) (__ct)
48
49/*
50 * Convert cputime <-> jiffies (HZ)
51 */
52#define cputime_to_jiffies(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
53#define jiffies_to_cputime(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
54#define cputime64_to_jiffies64(__ct) ((__ct) / (NSEC_PER_SEC / HZ))
55#define jiffies64_to_cputime64(__jif) ((__jif) * (NSEC_PER_SEC / HZ))
56
57/*
58 * Convert cputime <-> milliseconds
59 */
60#define cputime_to_msecs(__ct) ((__ct) / NSEC_PER_MSEC)
61#define msecs_to_cputime(__msecs) ((__msecs) * NSEC_PER_MSEC)
62
63/*
64 * Convert cputime <-> seconds
65 */
66#define cputime_to_secs(__ct) ((__ct) / NSEC_PER_SEC)
67#define secs_to_cputime(__secs) ((__secs) * NSEC_PER_SEC)
68
69/*
70 * Convert cputime <-> timespec (nsec)
71 */
72static inline cputime_t timespec_to_cputime(const struct timespec *val)
73{
74 cputime_t ret = val->tv_sec * NSEC_PER_SEC;
75 return (ret + val->tv_nsec);
76}
77static inline void cputime_to_timespec(const cputime_t ct, struct timespec *val)
78{
79 val->tv_sec = ct / NSEC_PER_SEC;
80 val->tv_nsec = ct % NSEC_PER_SEC;
81}
82
83/*
84 * Convert cputime <-> timeval (msec)
85 */
86static inline cputime_t timeval_to_cputime(struct timeval *val)
87{
88 cputime_t ret = val->tv_sec * NSEC_PER_SEC;
89 return (ret + val->tv_usec * NSEC_PER_USEC);
90}
91static inline void cputime_to_timeval(const cputime_t ct, struct timeval *val)
92{
93 val->tv_sec = ct / NSEC_PER_SEC;
94 val->tv_usec = (ct % NSEC_PER_SEC) / NSEC_PER_USEC;
95}
96
97/*
98 * Convert cputime <-> clock (USER_HZ)
99 */
100#define cputime_to_clock_t(__ct) ((__ct) / (NSEC_PER_SEC / USER_HZ))
101#define clock_t_to_cputime(__x) ((__x) * (NSEC_PER_SEC / USER_HZ))
102
103/*
104 * Convert cputime64 to clock.
105 */
106#define cputime64_to_clock_t(__ct) cputime_to_clock_t((cputime_t)__ct)
107
108#endif /* CONFIG_VIRT_CPU_ACCOUNTING */
109#endif /* __IA64_CPUTIME_H */
diff --git a/arch/ia64/include/asm/current.h b/arch/ia64/include/asm/current.h
new file mode 100644
index 000000000000..c659f90fbfd9
--- /dev/null
+++ b/arch/ia64/include/asm/current.h
@@ -0,0 +1,17 @@
1#ifndef _ASM_IA64_CURRENT_H
2#define _ASM_IA64_CURRENT_H
3
4/*
5 * Modified 1998-2000
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9#include <asm/intrinsics.h>
10
11/*
12 * In kernel mode, thread pointer (r13) is used to point to the current task
13 * structure.
14 */
15#define current ((struct task_struct *) ia64_getreg(_IA64_REG_TP))
16
17#endif /* _ASM_IA64_CURRENT_H */
diff --git a/arch/ia64/include/asm/cyclone.h b/arch/ia64/include/asm/cyclone.h
new file mode 100644
index 000000000000..88f6500e84ab
--- /dev/null
+++ b/arch/ia64/include/asm/cyclone.h
@@ -0,0 +1,15 @@
1#ifndef ASM_IA64_CYCLONE_H
2#define ASM_IA64_CYCLONE_H
3
4#ifdef CONFIG_IA64_CYCLONE
5extern int use_cyclone;
6extern void __init cyclone_setup(void);
7#else /* CONFIG_IA64_CYCLONE */
8#define use_cyclone 0
9static inline void cyclone_setup(void)
10{
11 printk(KERN_ERR "Cyclone Counter: System not configured"
12 " w/ CONFIG_IA64_CYCLONE.\n");
13}
14#endif /* CONFIG_IA64_CYCLONE */
15#endif /* !ASM_IA64_CYCLONE_H */
diff --git a/arch/ia64/include/asm/delay.h b/arch/ia64/include/asm/delay.h
new file mode 100644
index 000000000000..a30a62f235e1
--- /dev/null
+++ b/arch/ia64/include/asm/delay.h
@@ -0,0 +1,88 @@
1#ifndef _ASM_IA64_DELAY_H
2#define _ASM_IA64_DELAY_H
3
4/*
5 * Delay routines using a pre-computed "cycles/usec" value.
6 *
7 * Copyright (C) 1998, 1999 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 1999 VA Linux Systems
10 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
11 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
12 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
13 */
14
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/compiler.h>
18
19#include <asm/intrinsics.h>
20#include <asm/processor.h>
21
22static __inline__ void
23ia64_set_itm (unsigned long val)
24{
25 ia64_setreg(_IA64_REG_CR_ITM, val);
26 ia64_srlz_d();
27}
28
29static __inline__ unsigned long
30ia64_get_itm (void)
31{
32 unsigned long result;
33
34 result = ia64_getreg(_IA64_REG_CR_ITM);
35 ia64_srlz_d();
36 return result;
37}
38
39static __inline__ void
40ia64_set_itv (unsigned long val)
41{
42 ia64_setreg(_IA64_REG_CR_ITV, val);
43 ia64_srlz_d();
44}
45
46static __inline__ unsigned long
47ia64_get_itv (void)
48{
49 return ia64_getreg(_IA64_REG_CR_ITV);
50}
51
52static __inline__ void
53ia64_set_itc (unsigned long val)
54{
55 ia64_setreg(_IA64_REG_AR_ITC, val);
56 ia64_srlz_d();
57}
58
59static __inline__ unsigned long
60ia64_get_itc (void)
61{
62 unsigned long result;
63
64 result = ia64_getreg(_IA64_REG_AR_ITC);
65 ia64_barrier();
66#ifdef CONFIG_ITANIUM
67 while (unlikely((__s32) result == -1)) {
68 result = ia64_getreg(_IA64_REG_AR_ITC);
69 ia64_barrier();
70 }
71#endif
72 return result;
73}
74
75extern void ia64_delay_loop (unsigned long loops);
76
77static __inline__ void
78__delay (unsigned long loops)
79{
80 if (unlikely(loops < 1))
81 return;
82
83 ia64_delay_loop (loops - 1);
84}
85
86extern void udelay (unsigned long usecs);
87
88#endif /* _ASM_IA64_DELAY_H */
diff --git a/arch/ia64/include/asm/device.h b/arch/ia64/include/asm/device.h
new file mode 100644
index 000000000000..3db6daf7f251
--- /dev/null
+++ b/arch/ia64/include/asm/device.h
@@ -0,0 +1,15 @@
1/*
2 * Arch specific extensions to struct device
3 *
4 * This file is released under the GPLv2
5 */
6#ifndef _ASM_IA64_DEVICE_H
7#define _ASM_IA64_DEVICE_H
8
9struct dev_archdata {
10#ifdef CONFIG_ACPI
11 void *acpi_handle;
12#endif
13};
14
15#endif /* _ASM_IA64_DEVICE_H */
diff --git a/arch/ia64/include/asm/div64.h b/arch/ia64/include/asm/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/arch/ia64/include/asm/div64.h
@@ -0,0 +1 @@
#include <asm-generic/div64.h>
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
new file mode 100644
index 000000000000..9f0df9bd46b7
--- /dev/null
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -0,0 +1,97 @@
1#ifndef _ASM_IA64_DMA_MAPPING_H
2#define _ASM_IA64_DMA_MAPPING_H
3
4/*
5 * Copyright (C) 2003-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8#include <asm/machvec.h>
9#include <linux/scatterlist.h>
10
11#define dma_alloc_coherent platform_dma_alloc_coherent
12/* coherent mem. is cheap */
13static inline void *
14dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
15 gfp_t flag)
16{
17 return dma_alloc_coherent(dev, size, dma_handle, flag);
18}
19#define dma_free_coherent platform_dma_free_coherent
20static inline void
21dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
22 dma_addr_t dma_handle)
23{
24 dma_free_coherent(dev, size, cpu_addr, dma_handle);
25}
26#define dma_map_single_attrs platform_dma_map_single_attrs
27static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
28 size_t size, int dir)
29{
30 return dma_map_single_attrs(dev, cpu_addr, size, dir, NULL);
31}
32#define dma_map_sg_attrs platform_dma_map_sg_attrs
33static inline int dma_map_sg(struct device *dev, struct scatterlist *sgl,
34 int nents, int dir)
35{
36 return dma_map_sg_attrs(dev, sgl, nents, dir, NULL);
37}
38#define dma_unmap_single_attrs platform_dma_unmap_single_attrs
39static inline void dma_unmap_single(struct device *dev, dma_addr_t cpu_addr,
40 size_t size, int dir)
41{
42 return dma_unmap_single_attrs(dev, cpu_addr, size, dir, NULL);
43}
44#define dma_unmap_sg_attrs platform_dma_unmap_sg_attrs
45static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
46 int nents, int dir)
47{
48 return dma_unmap_sg_attrs(dev, sgl, nents, dir, NULL);
49}
50#define dma_sync_single_for_cpu platform_dma_sync_single_for_cpu
51#define dma_sync_sg_for_cpu platform_dma_sync_sg_for_cpu
52#define dma_sync_single_for_device platform_dma_sync_single_for_device
53#define dma_sync_sg_for_device platform_dma_sync_sg_for_device
54#define dma_mapping_error platform_dma_mapping_error
55
56#define dma_map_page(dev, pg, off, size, dir) \
57 dma_map_single(dev, page_address(pg) + (off), (size), (dir))
58#define dma_unmap_page(dev, dma_addr, size, dir) \
59 dma_unmap_single(dev, dma_addr, size, dir)
60
61/*
62 * Rest of this file is part of the "Advanced DMA API". Use at your own risk.
63 * See Documentation/DMA-API.txt for details.
64 */
65
66#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir) \
67 dma_sync_single_for_cpu(dev, dma_handle, size, dir)
68#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir) \
69 dma_sync_single_for_device(dev, dma_handle, size, dir)
70
71#define dma_supported platform_dma_supported
72
73static inline int
74dma_set_mask (struct device *dev, u64 mask)
75{
76 if (!dev->dma_mask || !dma_supported(dev, mask))
77 return -EIO;
78 *dev->dma_mask = mask;
79 return 0;
80}
81
82extern int dma_get_cache_alignment(void);
83
84static inline void
85dma_cache_sync (struct device *dev, void *vaddr, size_t size,
86 enum dma_data_direction dir)
87{
88 /*
89 * IA-64 is cache-coherent, so this is mostly a no-op. However, we do need to
90 * ensure that dma_cache_sync() enforces order, hence the mb().
91 */
92 mb();
93}
94
95#define dma_is_consistent(d, h) (1) /* all we do is coherent memory... */
96
97#endif /* _ASM_IA64_DMA_MAPPING_H */
diff --git a/arch/ia64/include/asm/dma.h b/arch/ia64/include/asm/dma.h
new file mode 100644
index 000000000000..4d97f60f1ef5
--- /dev/null
+++ b/arch/ia64/include/asm/dma.h
@@ -0,0 +1,24 @@
1#ifndef _ASM_IA64_DMA_H
2#define _ASM_IA64_DMA_H
3
4/*
5 * Copyright (C) 1998-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <asm/io.h> /* need byte IO */
11
12extern unsigned long MAX_DMA_ADDRESS;
13
14#ifdef CONFIG_PCI
15 extern int isa_dma_bridge_buggy;
16#else
17# define isa_dma_bridge_buggy (0)
18#endif
19
20#define free_dma(x)
21
22void dma_mark_clean(void *addr, size_t size);
23
24#endif /* _ASM_IA64_DMA_H */
diff --git a/arch/ia64/include/asm/dmi.h b/arch/ia64/include/asm/dmi.h
new file mode 100644
index 000000000000..00eb1b130b63
--- /dev/null
+++ b/arch/ia64/include/asm/dmi.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_DMI_H
2#define _ASM_DMI_H 1
3
4#include <asm/io.h>
5
6/* Use normal IO mappings for DMI */
7#define dmi_ioremap ioremap
8#define dmi_iounmap(x,l) iounmap(x)
9#define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
10
11#endif
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
new file mode 100644
index 000000000000..5e0c1a6bce8d
--- /dev/null
+++ b/arch/ia64/include/asm/elf.h
@@ -0,0 +1,269 @@
1#ifndef _ASM_IA64_ELF_H
2#define _ASM_IA64_ELF_H
3
4/*
5 * ELF-specific definitions.
6 *
7 * Copyright (C) 1998-1999, 2002-2004 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11
12#include <asm/fpu.h>
13#include <asm/page.h>
14#include <asm/auxvec.h>
15
16/*
17 * This is used to ensure we don't load something for the wrong architecture.
18 */
19#define elf_check_arch(x) ((x)->e_machine == EM_IA_64)
20
21/*
22 * These are used to set parameters in the core dumps.
23 */
24#define ELF_CLASS ELFCLASS64
25#define ELF_DATA ELFDATA2LSB
26#define ELF_ARCH EM_IA_64
27
28#define USE_ELF_CORE_DUMP
29#define CORE_DUMP_USE_REGSET
30
31/* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are
32 interpreted as follows by Linux: */
33#define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1 /* is stack (& heap) executable by default? */
34
35#define ELF_EXEC_PAGESIZE PAGE_SIZE
36
37/*
38 * This is the location that an ET_DYN program is loaded if exec'ed.
39 * Typical use of this is to invoke "./ld.so someprog" to test out a
40 * new version of the loader. We need to make sure that it is out of
41 * the way of the program that it will "exec", and that there is
42 * sufficient room for the brk.
43 */
44#define ELF_ET_DYN_BASE (TASK_UNMAPPED_BASE + 0x800000000UL)
45
46#define PT_IA_64_UNWIND 0x70000001
47
48/* IA-64 relocations: */
49#define R_IA64_NONE 0x00 /* none */
50#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */
51#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */
52#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */
53#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */
54#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */
55#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */
56#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */
57#define R_IA64_GPREL22 0x2a /* @gprel(sym+add), add imm22 */
58#define R_IA64_GPREL64I 0x2b /* @gprel(sym+add), mov imm64 */
59#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym+add), data4 MSB */
60#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym+add), data4 LSB */
61#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym+add), data8 MSB */
62#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym+add), data8 LSB */
63#define R_IA64_LTOFF22 0x32 /* @ltoff(sym+add), add imm22 */
64#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym+add), mov imm64 */
65#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym+add), add imm22 */
66#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym+add), mov imm64 */
67#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym+add), data8 MSB */
68#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym+add), data8 LSB */
69#define R_IA64_FPTR64I 0x43 /* @fptr(sym+add), mov imm64 */
70#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym+add), data4 MSB */
71#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym+add), data4 LSB */
72#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym+add), data8 MSB */
73#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym+add), data8 LSB */
74#define R_IA64_PCREL60B 0x48 /* @pcrel(sym+add), brl */
75#define R_IA64_PCREL21B 0x49 /* @pcrel(sym+add), ptb, call */
76#define R_IA64_PCREL21M 0x4a /* @pcrel(sym+add), chk.s */
77#define R_IA64_PCREL21F 0x4b /* @pcrel(sym+add), fchkf */
78#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym+add), data4 MSB */
79#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym+add), data4 LSB */
80#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym+add), data8 MSB */
81#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym+add), data8 LSB */
82#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */
83#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */
84#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), 4 MSB */
85#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), 4 LSB */
86#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), 8 MSB */
87#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), 8 LSB */
88#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym+add), data4 MSB */
89#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym+add), data4 LSB */
90#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym+add), data8 MSB */
91#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym+add), data8 LSB */
92#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym+add), data4 MSB */
93#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym+add), data4 LSB */
94#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym+add), data8 MSB */
95#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym+add), data8 LSB */
96#define R_IA64_REL32MSB 0x6c /* data 4 + REL */
97#define R_IA64_REL32LSB 0x6d /* data 4 + REL */
98#define R_IA64_REL64MSB 0x6e /* data 8 + REL */
99#define R_IA64_REL64LSB 0x6f /* data 8 + REL */
100#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */
101#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */
102#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */
103#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */
104#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym+add), ptb, call */
105#define R_IA64_PCREL22 0x7a /* @pcrel(sym+add), imm22 */
106#define R_IA64_PCREL64I 0x7b /* @pcrel(sym+add), imm64 */
107#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */
108#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */
109#define R_IA64_COPY 0x84 /* dynamic reloc, data copy */
110#define R_IA64_SUB 0x85 /* -symbol + addend, add imm22 */
111#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */
112#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */
113#define R_IA64_TPREL14 0x91 /* @tprel(sym+add), add imm14 */
114#define R_IA64_TPREL22 0x92 /* @tprel(sym+add), add imm22 */
115#define R_IA64_TPREL64I 0x93 /* @tprel(sym+add), add imm64 */
116#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym+add), data8 MSB */
117#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym+add), data8 LSB */
118#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), add imm22 */
119#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym+add), data8 MSB */
120#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym+add), data8 LSB */
121#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(s+a)), imm22 */
122#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym+add), imm14 */
123#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym+add), imm22 */
124#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym+add), imm64 */
125#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym+add), data4 MSB */
126#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym+add), data4 LSB */
127#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym+add), data8 MSB */
128#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym+add), data8 LSB */
129#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */
130
131/* IA-64 specific section flags: */
132#define SHF_IA_64_SHORT 0x10000000 /* section near gp */
133
134/*
135 * We use (abuse?) this macro to insert the (empty) vm_area that is
136 * used to map the register backing store. I don't see any better
137 * place to do this, but we should discuss this with Linus once we can
138 * talk to him...
139 */
140extern void ia64_init_addr_space (void);
141#define ELF_PLAT_INIT(_r, load_addr) ia64_init_addr_space()
142
143/* ELF register definitions. This is needed for core dump support. */
144
145/*
146 * elf_gregset_t contains the application-level state in the following order:
147 * r0-r31
148 * NaT bits (for r0-r31; bit N == 1 iff rN is a NaT)
149 * predicate registers (p0-p63)
150 * b0-b7
151 * ip cfm psr
152 * ar.rsc ar.bsp ar.bspstore ar.rnat
153 * ar.ccv ar.unat ar.fpsr ar.pfs ar.lc ar.ec ar.csd ar.ssd
154 */
155#define ELF_NGREG 128 /* we really need just 72 but let's leave some headroom... */
156#define ELF_NFPREG 128 /* f0 and f1 could be omitted, but so what... */
157
158/* elf_gregset_t register offsets */
159#define ELF_GR_0_OFFSET 0
160#define ELF_NAT_OFFSET (32 * sizeof(elf_greg_t))
161#define ELF_PR_OFFSET (33 * sizeof(elf_greg_t))
162#define ELF_BR_0_OFFSET (34 * sizeof(elf_greg_t))
163#define ELF_CR_IIP_OFFSET (42 * sizeof(elf_greg_t))
164#define ELF_CFM_OFFSET (43 * sizeof(elf_greg_t))
165#define ELF_CR_IPSR_OFFSET (44 * sizeof(elf_greg_t))
166#define ELF_GR_OFFSET(i) (ELF_GR_0_OFFSET + i * sizeof(elf_greg_t))
167#define ELF_BR_OFFSET(i) (ELF_BR_0_OFFSET + i * sizeof(elf_greg_t))
168#define ELF_AR_RSC_OFFSET (45 * sizeof(elf_greg_t))
169#define ELF_AR_BSP_OFFSET (46 * sizeof(elf_greg_t))
170#define ELF_AR_BSPSTORE_OFFSET (47 * sizeof(elf_greg_t))
171#define ELF_AR_RNAT_OFFSET (48 * sizeof(elf_greg_t))
172#define ELF_AR_CCV_OFFSET (49 * sizeof(elf_greg_t))
173#define ELF_AR_UNAT_OFFSET (50 * sizeof(elf_greg_t))
174#define ELF_AR_FPSR_OFFSET (51 * sizeof(elf_greg_t))
175#define ELF_AR_PFS_OFFSET (52 * sizeof(elf_greg_t))
176#define ELF_AR_LC_OFFSET (53 * sizeof(elf_greg_t))
177#define ELF_AR_EC_OFFSET (54 * sizeof(elf_greg_t))
178#define ELF_AR_CSD_OFFSET (55 * sizeof(elf_greg_t))
179#define ELF_AR_SSD_OFFSET (56 * sizeof(elf_greg_t))
180#define ELF_AR_END_OFFSET (57 * sizeof(elf_greg_t))
181
182typedef unsigned long elf_fpxregset_t;
183
184typedef unsigned long elf_greg_t;
185typedef elf_greg_t elf_gregset_t[ELF_NGREG];
186
187typedef struct ia64_fpreg elf_fpreg_t;
188typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
189
190
191
192struct pt_regs; /* forward declaration... */
193extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
194#define ELF_CORE_COPY_REGS(_dest,_regs) ia64_elf_core_copy_regs(_regs, _dest);
195
196/* This macro yields a bitmask that programs can use to figure out
197 what instruction set this CPU supports. */
198#define ELF_HWCAP 0
199
200/* This macro yields a string that ld.so will use to load
201 implementation specific libraries for optimization. Not terribly
202 relevant until we have real hardware to play with... */
203#define ELF_PLATFORM NULL
204
205#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
206#define elf_read_implies_exec(ex, executable_stack) \
207 ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
208
209struct task_struct;
210
211#define GATE_EHDR ((const struct elfhdr *) GATE_ADDR)
212
213/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
214#define ARCH_DLINFO \
215do { \
216 extern char __kernel_syscall_via_epc[]; \
217 NEW_AUX_ENT(AT_SYSINFO, (unsigned long) __kernel_syscall_via_epc); \
218 NEW_AUX_ENT(AT_SYSINFO_EHDR, (unsigned long) GATE_EHDR); \
219} while (0)
220
221
222/*
223 * These macros parameterize elf_core_dump in fs/binfmt_elf.c to write out
224 * extra segments containing the gate DSO contents. Dumping its
225 * contents makes post-mortem fully interpretable later without matching up
226 * the same kernel and hardware config to see what PC values meant.
227 * Dumping its extra ELF program headers includes all the other information
228 * a debugger needs to easily find how the gate DSO was being used.
229 */
230#define ELF_CORE_EXTRA_PHDRS (GATE_EHDR->e_phnum)
231#define ELF_CORE_WRITE_EXTRA_PHDRS \
232do { \
233 const struct elf_phdr *const gate_phdrs = \
234 (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff); \
235 int i; \
236 Elf64_Off ofs = 0; \
237 for (i = 0; i < GATE_EHDR->e_phnum; ++i) { \
238 struct elf_phdr phdr = gate_phdrs[i]; \
239 if (phdr.p_type == PT_LOAD) { \
240 phdr.p_memsz = PAGE_ALIGN(phdr.p_memsz); \
241 phdr.p_filesz = phdr.p_memsz; \
242 if (ofs == 0) { \
243 ofs = phdr.p_offset = offset; \
244 offset += phdr.p_filesz; \
245 } \
246 else \
247 phdr.p_offset = ofs; \
248 } \
249 else \
250 phdr.p_offset += ofs; \
251 phdr.p_paddr = 0; /* match other core phdrs */ \
252 DUMP_WRITE(&phdr, sizeof(phdr)); \
253 } \
254} while (0)
255#define ELF_CORE_WRITE_EXTRA_DATA \
256do { \
257 const struct elf_phdr *const gate_phdrs = \
258 (const struct elf_phdr *) (GATE_ADDR + GATE_EHDR->e_phoff); \
259 int i; \
260 for (i = 0; i < GATE_EHDR->e_phnum; ++i) { \
261 if (gate_phdrs[i].p_type == PT_LOAD) { \
262 DUMP_WRITE((void *) gate_phdrs[i].p_vaddr, \
263 PAGE_ALIGN(gate_phdrs[i].p_memsz)); \
264 break; \
265 } \
266 } \
267} while (0)
268
269#endif /* _ASM_IA64_ELF_H */
diff --git a/arch/ia64/include/asm/emergency-restart.h b/arch/ia64/include/asm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/arch/ia64/include/asm/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/ia64/include/asm/errno.h b/arch/ia64/include/asm/errno.h
new file mode 100644
index 000000000000..4c82b503d92f
--- /dev/null
+++ b/arch/ia64/include/asm/errno.h
@@ -0,0 +1 @@
#include <asm-generic/errno.h>
diff --git a/arch/ia64/include/asm/esi.h b/arch/ia64/include/asm/esi.h
new file mode 100644
index 000000000000..40991c6ba647
--- /dev/null
+++ b/arch/ia64/include/asm/esi.h
@@ -0,0 +1,29 @@
1/*
2 * ESI service calls.
3 *
4 * Copyright (c) Copyright 2005-2006 Hewlett-Packard Development Company, L.P.
5 * Alex Williamson <alex.williamson@hp.com>
6 */
7#ifndef esi_h
8#define esi_h
9
10#include <linux/efi.h>
11
12#define ESI_QUERY 0x00000001
13#define ESI_OPEN_HANDLE 0x02000000
14#define ESI_CLOSE_HANDLE 0x02000001
15
16enum esi_proc_type {
17 ESI_PROC_SERIALIZED, /* calls need to be serialized */
18 ESI_PROC_MP_SAFE, /* MP-safe, but not reentrant */
19 ESI_PROC_REENTRANT /* MP-safe and reentrant */
20};
21
22extern struct ia64_sal_retval esi_call_phys (void *, u64 *);
23extern int ia64_esi_call(efi_guid_t, struct ia64_sal_retval *,
24 enum esi_proc_type,
25 u64, u64, u64, u64, u64, u64, u64, u64);
26extern int ia64_esi_call_phys(efi_guid_t, struct ia64_sal_retval *, u64, u64,
27 u64, u64, u64, u64, u64, u64);
28
29#endif /* esi_h */
diff --git a/arch/ia64/include/asm/fb.h b/arch/ia64/include/asm/fb.h
new file mode 100644
index 000000000000..89a397cee90a
--- /dev/null
+++ b/arch/ia64/include/asm/fb.h
@@ -0,0 +1,23 @@
1#ifndef _ASM_FB_H_
2#define _ASM_FB_H_
3
4#include <linux/fb.h>
5#include <linux/fs.h>
6#include <linux/efi.h>
7#include <asm/page.h>
8
9static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
10 unsigned long off)
11{
12 if (efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
13 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
14 else
15 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
16}
17
18static inline int fb_is_primary_device(struct fb_info *info)
19{
20 return 0;
21}
22
23#endif /* _ASM_FB_H_ */
diff --git a/arch/ia64/include/asm/fcntl.h b/arch/ia64/include/asm/fcntl.h
new file mode 100644
index 000000000000..1dd275dc8f65
--- /dev/null
+++ b/arch/ia64/include/asm/fcntl.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_IA64_FCNTL_H
2#define _ASM_IA64_FCNTL_H
3/*
4 * Modified 1998-2000
5 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co.
6 */
7
8#define force_o_largefile() \
9 (personality(current->personality) != PER_LINUX32)
10
11#include <asm-generic/fcntl.h>
12
13#endif /* _ASM_IA64_FCNTL_H */
diff --git a/arch/ia64/include/asm/fpswa.h b/arch/ia64/include/asm/fpswa.h
new file mode 100644
index 000000000000..62edfceadaa6
--- /dev/null
+++ b/arch/ia64/include/asm/fpswa.h
@@ -0,0 +1,73 @@
1#ifndef _ASM_IA64_FPSWA_H
2#define _ASM_IA64_FPSWA_H
3
4/*
5 * Floating-point Software Assist
6 *
7 * Copyright (C) 1999 Intel Corporation.
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Goutham Rao <goutham.rao@intel.com>
10 */
11
12typedef struct {
13 /* 4 * 128 bits */
14 unsigned long fp_lp[4*2];
15} fp_state_low_preserved_t;
16
17typedef struct {
18 /* 10 * 128 bits */
19 unsigned long fp_lv[10 * 2];
20} fp_state_low_volatile_t;
21
22typedef struct {
23 /* 16 * 128 bits */
24 unsigned long fp_hp[16 * 2];
25} fp_state_high_preserved_t;
26
27typedef struct {
28 /* 96 * 128 bits */
29 unsigned long fp_hv[96 * 2];
30} fp_state_high_volatile_t;
31
32/**
33 * floating point state to be passed to the FP emulation library by
34 * the trap/fault handler
35 */
36typedef struct {
37 unsigned long bitmask_low64;
38 unsigned long bitmask_high64;
39 fp_state_low_preserved_t *fp_state_low_preserved;
40 fp_state_low_volatile_t *fp_state_low_volatile;
41 fp_state_high_preserved_t *fp_state_high_preserved;
42 fp_state_high_volatile_t *fp_state_high_volatile;
43} fp_state_t;
44
45typedef struct {
46 unsigned long status;
47 unsigned long err0;
48 unsigned long err1;
49 unsigned long err2;
50} fpswa_ret_t;
51
52/**
53 * function header for the Floating Point software assist
54 * library. This function is invoked by the Floating point software
55 * assist trap/fault handler.
56 */
57typedef fpswa_ret_t (*efi_fpswa_t) (unsigned long trap_type, void *bundle, unsigned long *ipsr,
58 unsigned long *fsr, unsigned long *isr, unsigned long *preds,
59 unsigned long *ifs, fp_state_t *fp_state);
60
61/**
62 * This is the FPSWA library interface as defined by EFI. We need to pass a
63 * pointer to the interface itself on a call to the assist library
64 */
65typedef struct {
66 unsigned int revision;
67 unsigned int reserved;
68 efi_fpswa_t fpswa;
69} fpswa_interface_t;
70
71extern fpswa_interface_t *fpswa_interface;
72
73#endif /* _ASM_IA64_FPSWA_H */
diff --git a/arch/ia64/include/asm/fpu.h b/arch/ia64/include/asm/fpu.h
new file mode 100644
index 000000000000..3859558ff0a4
--- /dev/null
+++ b/arch/ia64/include/asm/fpu.h
@@ -0,0 +1,66 @@
1#ifndef _ASM_IA64_FPU_H
2#define _ASM_IA64_FPU_H
3
4/*
5 * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm/types.h>
10
11/* floating point status register: */
12#define FPSR_TRAP_VD (1 << 0) /* invalid op trap disabled */
13#define FPSR_TRAP_DD (1 << 1) /* denormal trap disabled */
14#define FPSR_TRAP_ZD (1 << 2) /* zero-divide trap disabled */
15#define FPSR_TRAP_OD (1 << 3) /* overflow trap disabled */
16#define FPSR_TRAP_UD (1 << 4) /* underflow trap disabled */
17#define FPSR_TRAP_ID (1 << 5) /* inexact trap disabled */
18#define FPSR_S0(x) ((x) << 6)
19#define FPSR_S1(x) ((x) << 19)
20#define FPSR_S2(x) (__IA64_UL(x) << 32)
21#define FPSR_S3(x) (__IA64_UL(x) << 45)
22
23/* floating-point status field controls: */
24#define FPSF_FTZ (1 << 0) /* flush-to-zero */
25#define FPSF_WRE (1 << 1) /* widest-range exponent */
26#define FPSF_PC(x) (((x) & 0x3) << 2) /* precision control */
27#define FPSF_RC(x) (((x) & 0x3) << 4) /* rounding control */
28#define FPSF_TD (1 << 6) /* trap disabled */
29
30/* floating-point status field flags: */
31#define FPSF_V (1 << 7) /* invalid operation flag */
32#define FPSF_D (1 << 8) /* denormal/unnormal operand flag */
33#define FPSF_Z (1 << 9) /* zero divide (IEEE) flag */
34#define FPSF_O (1 << 10) /* overflow (IEEE) flag */
35#define FPSF_U (1 << 11) /* underflow (IEEE) flag */
36#define FPSF_I (1 << 12) /* inexact (IEEE) flag) */
37
38/* floating-point rounding control: */
39#define FPRC_NEAREST 0x0
40#define FPRC_NEGINF 0x1
41#define FPRC_POSINF 0x2
42#define FPRC_TRUNC 0x3
43
44#define FPSF_DEFAULT (FPSF_PC (0x3) | FPSF_RC (FPRC_NEAREST))
45
46/* This default value is the same as HP-UX uses. Don't change it
47 without a very good reason. */
48#define FPSR_DEFAULT (FPSR_TRAP_VD | FPSR_TRAP_DD | FPSR_TRAP_ZD \
49 | FPSR_TRAP_OD | FPSR_TRAP_UD | FPSR_TRAP_ID \
50 | FPSR_S0 (FPSF_DEFAULT) \
51 | FPSR_S1 (FPSF_DEFAULT | FPSF_TD | FPSF_WRE) \
52 | FPSR_S2 (FPSF_DEFAULT | FPSF_TD) \
53 | FPSR_S3 (FPSF_DEFAULT | FPSF_TD))
54
55# ifndef __ASSEMBLY__
56
57struct ia64_fpreg {
58 union {
59 unsigned long bits[2];
60 long double __dummy; /* force 16-byte alignment */
61 } u;
62};
63
64# endif /* __ASSEMBLY__ */
65
66#endif /* _ASM_IA64_FPU_H */
diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h
new file mode 100644
index 000000000000..c7f0f062239c
--- /dev/null
+++ b/arch/ia64/include/asm/futex.h
@@ -0,0 +1,124 @@
1#ifndef _ASM_FUTEX_H
2#define _ASM_FUTEX_H
3
4#include <linux/futex.h>
5#include <linux/uaccess.h>
6#include <asm/errno.h>
7#include <asm/system.h>
8
9#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
10do { \
11 register unsigned long r8 __asm ("r8") = 0; \
12 __asm__ __volatile__( \
13 " mf;; \n" \
14 "[1:] " insn ";; \n" \
15 " .xdata4 \"__ex_table\", 1b-., 2f-. \n" \
16 "[2:]" \
17 : "+r" (r8), "=r" (oldval) \
18 : "r" (uaddr), "r" (oparg) \
19 : "memory"); \
20 ret = r8; \
21} while (0)
22
23#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
24do { \
25 register unsigned long r8 __asm ("r8") = 0; \
26 int val, newval; \
27 do { \
28 __asm__ __volatile__( \
29 " mf;; \n" \
30 "[1:] ld4 %3=[%4];; \n" \
31 " mov %2=%3 \n" \
32 insn ";; \n" \
33 " mov ar.ccv=%2;; \n" \
34 "[2:] cmpxchg4.acq %1=[%4],%3,ar.ccv;; \n" \
35 " .xdata4 \"__ex_table\", 1b-., 3f-.\n" \
36 " .xdata4 \"__ex_table\", 2b-., 3f-.\n" \
37 "[3:]" \
38 : "+r" (r8), "=r" (val), "=&r" (oldval), \
39 "=&r" (newval) \
40 : "r" (uaddr), "r" (oparg) \
41 : "memory"); \
42 if (unlikely (r8)) \
43 break; \
44 } while (unlikely (val != oldval)); \
45 ret = r8; \
46} while (0)
47
48static inline int
49futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
50{
51 int op = (encoded_op >> 28) & 7;
52 int cmp = (encoded_op >> 24) & 15;
53 int oparg = (encoded_op << 8) >> 20;
54 int cmparg = (encoded_op << 20) >> 20;
55 int oldval = 0, ret;
56 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
57 oparg = 1 << oparg;
58
59 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
60 return -EFAULT;
61
62 pagefault_disable();
63
64 switch (op) {
65 case FUTEX_OP_SET:
66 __futex_atomic_op1("xchg4 %1=[%2],%3", ret, oldval, uaddr,
67 oparg);
68 break;
69 case FUTEX_OP_ADD:
70 __futex_atomic_op2("add %3=%3,%5", ret, oldval, uaddr, oparg);
71 break;
72 case FUTEX_OP_OR:
73 __futex_atomic_op2("or %3=%3,%5", ret, oldval, uaddr, oparg);
74 break;
75 case FUTEX_OP_ANDN:
76 __futex_atomic_op2("and %3=%3,%5", ret, oldval, uaddr,
77 ~oparg);
78 break;
79 case FUTEX_OP_XOR:
80 __futex_atomic_op2("xor %3=%3,%5", ret, oldval, uaddr, oparg);
81 break;
82 default:
83 ret = -ENOSYS;
84 }
85
86 pagefault_enable();
87
88 if (!ret) {
89 switch (cmp) {
90 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
91 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
92 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
93 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
94 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
95 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
96 default: ret = -ENOSYS;
97 }
98 }
99 return ret;
100}
101
102static inline int
103futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
104{
105 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
106 return -EFAULT;
107
108 {
109 register unsigned long r8 __asm ("r8");
110 __asm__ __volatile__(
111 " mf;; \n"
112 " mov ar.ccv=%3;; \n"
113 "[1:] cmpxchg4.acq %0=[%1],%2,ar.ccv \n"
114 " .xdata4 \"__ex_table\", 1b-., 2f-. \n"
115 "[2:]"
116 : "=r" (r8)
117 : "r" (uaddr), "r" (newval),
118 "rO" ((long) (unsigned) oldval)
119 : "memory");
120 return r8;
121 }
122}
123
124#endif /* _ASM_FUTEX_H */
diff --git a/arch/ia64/include/asm/gcc_intrin.h b/arch/ia64/include/asm/gcc_intrin.h
new file mode 100644
index 000000000000..0f5b55921758
--- /dev/null
+++ b/arch/ia64/include/asm/gcc_intrin.h
@@ -0,0 +1,620 @@
1#ifndef _ASM_IA64_GCC_INTRIN_H
2#define _ASM_IA64_GCC_INTRIN_H
3/*
4 *
5 * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
6 * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
7 */
8
9#include <linux/compiler.h>
10
11/* define this macro to get some asm stmts included in 'c' files */
12#define ASM_SUPPORTED
13
14/* Optimization barrier */
15/* The "volatile" is due to gcc bugs */
16#define ia64_barrier() asm volatile ("":::"memory")
17
18#define ia64_stop() asm volatile (";;"::)
19
20#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum))
21
22#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum))
23
24#define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
25
26#define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
27
28extern void ia64_bad_param_for_setreg (void);
29extern void ia64_bad_param_for_getreg (void);
30
31#ifdef __KERNEL__
32register unsigned long ia64_r13 asm ("r13") __used;
33#endif
34
35#define ia64_native_setreg(regnum, val) \
36({ \
37 switch (regnum) { \
38 case _IA64_REG_PSR_L: \
39 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
40 break; \
41 case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
42 asm volatile ("mov ar%0=%1" :: \
43 "i" (regnum - _IA64_REG_AR_KR0), \
44 "r"(val): "memory"); \
45 break; \
46 case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
47 asm volatile ("mov cr%0=%1" :: \
48 "i" (regnum - _IA64_REG_CR_DCR), \
49 "r"(val): "memory" ); \
50 break; \
51 case _IA64_REG_SP: \
52 asm volatile ("mov r12=%0" :: \
53 "r"(val): "memory"); \
54 break; \
55 case _IA64_REG_GP: \
56 asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \
57 break; \
58 default: \
59 ia64_bad_param_for_setreg(); \
60 break; \
61 } \
62})
63
64#define ia64_native_getreg(regnum) \
65({ \
66 __u64 ia64_intri_res; \
67 \
68 switch (regnum) { \
69 case _IA64_REG_GP: \
70 asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \
71 break; \
72 case _IA64_REG_IP: \
73 asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \
74 break; \
75 case _IA64_REG_PSR: \
76 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
77 break; \
78 case _IA64_REG_TP: /* for current() */ \
79 ia64_intri_res = ia64_r13; \
80 break; \
81 case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
82 asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \
83 : "i"(regnum - _IA64_REG_AR_KR0)); \
84 break; \
85 case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
86 asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \
87 : "i" (regnum - _IA64_REG_CR_DCR)); \
88 break; \
89 case _IA64_REG_SP: \
90 asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \
91 break; \
92 default: \
93 ia64_bad_param_for_getreg(); \
94 break; \
95 } \
96 ia64_intri_res; \
97})
98
99#define ia64_hint_pause 0
100
101#define ia64_hint(mode) \
102({ \
103 switch (mode) { \
104 case ia64_hint_pause: \
105 asm volatile ("hint @pause" ::: "memory"); \
106 break; \
107 } \
108})
109
110
111/* Integer values for mux1 instruction */
112#define ia64_mux1_brcst 0
113#define ia64_mux1_mix 8
114#define ia64_mux1_shuf 9
115#define ia64_mux1_alt 10
116#define ia64_mux1_rev 11
117
118#define ia64_mux1(x, mode) \
119({ \
120 __u64 ia64_intri_res; \
121 \
122 switch (mode) { \
123 case ia64_mux1_brcst: \
124 asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \
125 break; \
126 case ia64_mux1_mix: \
127 asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \
128 break; \
129 case ia64_mux1_shuf: \
130 asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \
131 break; \
132 case ia64_mux1_alt: \
133 asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \
134 break; \
135 case ia64_mux1_rev: \
136 asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \
137 break; \
138 } \
139 ia64_intri_res; \
140})
141
142#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
143# define ia64_popcnt(x) __builtin_popcountl(x)
144#else
145# define ia64_popcnt(x) \
146 ({ \
147 __u64 ia64_intri_res; \
148 asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
149 \
150 ia64_intri_res; \
151 })
152#endif
153
154#define ia64_getf_exp(x) \
155({ \
156 long ia64_intri_res; \
157 \
158 asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \
159 \
160 ia64_intri_res; \
161})
162
163#define ia64_shrp(a, b, count) \
164({ \
165 __u64 ia64_intri_res; \
166 asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \
167 ia64_intri_res; \
168})
169
170#define ia64_ldfs(regnum, x) \
171({ \
172 register double __f__ asm ("f"#regnum); \
173 asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \
174})
175
176#define ia64_ldfd(regnum, x) \
177({ \
178 register double __f__ asm ("f"#regnum); \
179 asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \
180})
181
182#define ia64_ldfe(regnum, x) \
183({ \
184 register double __f__ asm ("f"#regnum); \
185 asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \
186})
187
188#define ia64_ldf8(regnum, x) \
189({ \
190 register double __f__ asm ("f"#regnum); \
191 asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \
192})
193
194#define ia64_ldf_fill(regnum, x) \
195({ \
196 register double __f__ asm ("f"#regnum); \
197 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
198})
199
200#define ia64_st4_rel_nta(m, val) \
201({ \
202 asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
203})
204
205#define ia64_stfs(x, regnum) \
206({ \
207 register double __f__ asm ("f"#regnum); \
208 asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
209})
210
211#define ia64_stfd(x, regnum) \
212({ \
213 register double __f__ asm ("f"#regnum); \
214 asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
215})
216
217#define ia64_stfe(x, regnum) \
218({ \
219 register double __f__ asm ("f"#regnum); \
220 asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
221})
222
223#define ia64_stf8(x, regnum) \
224({ \
225 register double __f__ asm ("f"#regnum); \
226 asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
227})
228
229#define ia64_stf_spill(x, regnum) \
230({ \
231 register double __f__ asm ("f"#regnum); \
232 asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
233})
234
235#define ia64_fetchadd4_acq(p, inc) \
236({ \
237 \
238 __u64 ia64_intri_res; \
239 asm volatile ("fetchadd4.acq %0=[%1],%2" \
240 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
241 : "memory"); \
242 \
243 ia64_intri_res; \
244})
245
246#define ia64_fetchadd4_rel(p, inc) \
247({ \
248 __u64 ia64_intri_res; \
249 asm volatile ("fetchadd4.rel %0=[%1],%2" \
250 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
251 : "memory"); \
252 \
253 ia64_intri_res; \
254})
255
256#define ia64_fetchadd8_acq(p, inc) \
257({ \
258 \
259 __u64 ia64_intri_res; \
260 asm volatile ("fetchadd8.acq %0=[%1],%2" \
261 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
262 : "memory"); \
263 \
264 ia64_intri_res; \
265})
266
267#define ia64_fetchadd8_rel(p, inc) \
268({ \
269 __u64 ia64_intri_res; \
270 asm volatile ("fetchadd8.rel %0=[%1],%2" \
271 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
272 : "memory"); \
273 \
274 ia64_intri_res; \
275})
276
277#define ia64_xchg1(ptr,x) \
278({ \
279 __u64 ia64_intri_res; \
280 asm volatile ("xchg1 %0=[%1],%2" \
281 : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \
282 ia64_intri_res; \
283})
284
285#define ia64_xchg2(ptr,x) \
286({ \
287 __u64 ia64_intri_res; \
288 asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \
289 : "r" (ptr), "r" (x) : "memory"); \
290 ia64_intri_res; \
291})
292
293#define ia64_xchg4(ptr,x) \
294({ \
295 __u64 ia64_intri_res; \
296 asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \
297 : "r" (ptr), "r" (x) : "memory"); \
298 ia64_intri_res; \
299})
300
301#define ia64_xchg8(ptr,x) \
302({ \
303 __u64 ia64_intri_res; \
304 asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \
305 : "r" (ptr), "r" (x) : "memory"); \
306 ia64_intri_res; \
307})
308
309#define ia64_cmpxchg1_acq(ptr, new, old) \
310({ \
311 __u64 ia64_intri_res; \
312 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
313 asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \
314 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
315 ia64_intri_res; \
316})
317
318#define ia64_cmpxchg1_rel(ptr, new, old) \
319({ \
320 __u64 ia64_intri_res; \
321 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
322 asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \
323 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
324 ia64_intri_res; \
325})
326
327#define ia64_cmpxchg2_acq(ptr, new, old) \
328({ \
329 __u64 ia64_intri_res; \
330 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
331 asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \
332 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
333 ia64_intri_res; \
334})
335
336#define ia64_cmpxchg2_rel(ptr, new, old) \
337({ \
338 __u64 ia64_intri_res; \
339 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
340 \
341 asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \
342 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
343 ia64_intri_res; \
344})
345
346#define ia64_cmpxchg4_acq(ptr, new, old) \
347({ \
348 __u64 ia64_intri_res; \
349 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
350 asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
351 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
352 ia64_intri_res; \
353})
354
355#define ia64_cmpxchg4_rel(ptr, new, old) \
356({ \
357 __u64 ia64_intri_res; \
358 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
359 asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \
360 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
361 ia64_intri_res; \
362})
363
364#define ia64_cmpxchg8_acq(ptr, new, old) \
365({ \
366 __u64 ia64_intri_res; \
367 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
368 asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \
369 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
370 ia64_intri_res; \
371})
372
373#define ia64_cmpxchg8_rel(ptr, new, old) \
374({ \
375 __u64 ia64_intri_res; \
376 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
377 \
378 asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \
379 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
380 ia64_intri_res; \
381})
382
383#define ia64_mf() asm volatile ("mf" ::: "memory")
384#define ia64_mfa() asm volatile ("mf.a" ::: "memory")
385
386#define ia64_invala() asm volatile ("invala" ::: "memory")
387
388#define ia64_native_thash(addr) \
389({ \
390 __u64 ia64_intri_res; \
391 asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
392 ia64_intri_res; \
393})
394
395#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
396#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory");
397
398#ifdef HAVE_SERIALIZE_DIRECTIVE
399# define ia64_dv_serialize_data() asm volatile (".serialize.data");
400# define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction");
401#else
402# define ia64_dv_serialize_data()
403# define ia64_dv_serialize_instruction()
404#endif
405
406#define ia64_nop(x) asm volatile ("nop %0"::"i"(x));
407
408#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
409
410#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
411
412
413#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \
414 :: "r"(trnum), "r"(addr) : "memory")
415
416#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \
417 :: "r"(trnum), "r"(addr) : "memory")
418
419#define ia64_tpa(addr) \
420({ \
421 __u64 ia64_pa; \
422 asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \
423 ia64_pa; \
424})
425
426#define __ia64_set_dbr(index, val) \
427 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
428
429#define ia64_set_ibr(index, val) \
430 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
431
432#define ia64_set_pkr(index, val) \
433 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
434
435#define ia64_set_pmc(index, val) \
436 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
437
438#define ia64_set_pmd(index, val) \
439 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
440
441#define ia64_native_set_rr(index, val) \
442 asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
443
444#define ia64_native_get_cpuid(index) \
445({ \
446 __u64 ia64_intri_res; \
447 asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \
448 ia64_intri_res; \
449})
450
451#define __ia64_get_dbr(index) \
452({ \
453 __u64 ia64_intri_res; \
454 asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
455 ia64_intri_res; \
456})
457
458#define ia64_get_ibr(index) \
459({ \
460 __u64 ia64_intri_res; \
461 asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
462 ia64_intri_res; \
463})
464
465#define ia64_get_pkr(index) \
466({ \
467 __u64 ia64_intri_res; \
468 asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
469 ia64_intri_res; \
470})
471
472#define ia64_get_pmc(index) \
473({ \
474 __u64 ia64_intri_res; \
475 asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
476 ia64_intri_res; \
477})
478
479
480#define ia64_native_get_pmd(index) \
481({ \
482 __u64 ia64_intri_res; \
483 asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
484 ia64_intri_res; \
485})
486
487#define ia64_native_get_rr(index) \
488({ \
489 __u64 ia64_intri_res; \
490 asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
491 ia64_intri_res; \
492})
493
494#define ia64_native_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
495
496
497#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
498
499#define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory")
500#define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory")
501#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory")
502#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory")
503
504#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
505
506#define ia64_native_ptcga(addr, size) \
507do { \
508 asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \
509 ia64_dv_serialize_data(); \
510} while (0)
511
512#define ia64_ptcl(addr, size) \
513do { \
514 asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \
515 ia64_dv_serialize_data(); \
516} while (0)
517
518#define ia64_ptri(addr, size) \
519 asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
520
521#define ia64_ptrd(addr, size) \
522 asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
523
524#define ia64_ttag(addr) \
525({ \
526 __u64 ia64_intri_res; \
527 asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
528 ia64_intri_res; \
529})
530
531
532/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
533
534#define ia64_lfhint_none 0
535#define ia64_lfhint_nt1 1
536#define ia64_lfhint_nt2 2
537#define ia64_lfhint_nta 3
538
539#define ia64_lfetch(lfhint, y) \
540({ \
541 switch (lfhint) { \
542 case ia64_lfhint_none: \
543 asm volatile ("lfetch [%0]" : : "r"(y)); \
544 break; \
545 case ia64_lfhint_nt1: \
546 asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \
547 break; \
548 case ia64_lfhint_nt2: \
549 asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \
550 break; \
551 case ia64_lfhint_nta: \
552 asm volatile ("lfetch.nta [%0]" : : "r"(y)); \
553 break; \
554 } \
555})
556
557#define ia64_lfetch_excl(lfhint, y) \
558({ \
559 switch (lfhint) { \
560 case ia64_lfhint_none: \
561 asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
562 break; \
563 case ia64_lfhint_nt1: \
564 asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
565 break; \
566 case ia64_lfhint_nt2: \
567 asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
568 break; \
569 case ia64_lfhint_nta: \
570 asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
571 break; \
572 } \
573})
574
575#define ia64_lfetch_fault(lfhint, y) \
576({ \
577 switch (lfhint) { \
578 case ia64_lfhint_none: \
579 asm volatile ("lfetch.fault [%0]" : : "r"(y)); \
580 break; \
581 case ia64_lfhint_nt1: \
582 asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \
583 break; \
584 case ia64_lfhint_nt2: \
585 asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \
586 break; \
587 case ia64_lfhint_nta: \
588 asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \
589 break; \
590 } \
591})
592
593#define ia64_lfetch_fault_excl(lfhint, y) \
594({ \
595 switch (lfhint) { \
596 case ia64_lfhint_none: \
597 asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
598 break; \
599 case ia64_lfhint_nt1: \
600 asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
601 break; \
602 case ia64_lfhint_nt2: \
603 asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
604 break; \
605 case ia64_lfhint_nta: \
606 asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
607 break; \
608 } \
609})
610
611#define ia64_native_intrin_local_irq_restore(x) \
612do { \
613 asm volatile (";; cmp.ne p6,p7=%0,r0;;" \
614 "(p6) ssm psr.i;" \
615 "(p7) rsm psr.i;;" \
616 "(p6) srlz.d" \
617 :: "r"((x)) : "p6", "p7", "memory"); \
618} while (0)
619
620#endif /* _ASM_IA64_GCC_INTRIN_H */
diff --git a/arch/ia64/include/asm/hardirq.h b/arch/ia64/include/asm/hardirq.h
new file mode 100644
index 000000000000..140e495b8e0e
--- /dev/null
+++ b/arch/ia64/include/asm/hardirq.h
@@ -0,0 +1,37 @@
1#ifndef _ASM_IA64_HARDIRQ_H
2#define _ASM_IA64_HARDIRQ_H
3
4/*
5 * Modified 1998-2002, 2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <linux/threads.h>
11#include <linux/irq.h>
12
13#include <asm/processor.h>
14
15/*
16 * No irq_cpustat_t for IA-64. The data is held in the per-CPU data structure.
17 */
18
19#define __ARCH_IRQ_STAT 1
20
21#define local_softirq_pending() (local_cpu_data->softirq_pending)
22
23#define HARDIRQ_BITS 14
24
25/*
26 * The hardirq mask has to be large enough to have space for potentially all IRQ sources
27 * in the system nesting on a single CPU:
28 */
29#if (1 << HARDIRQ_BITS) < NR_IRQS
30# error HARDIRQ_BITS is too low!
31#endif
32
33extern void __iomem *ipi_base_addr;
34
35void ack_bad_irq(unsigned int irq);
36
37#endif /* _ASM_IA64_HARDIRQ_H */
diff --git a/arch/ia64/include/asm/hpsim.h b/arch/ia64/include/asm/hpsim.h
new file mode 100644
index 000000000000..892ab198a9da
--- /dev/null
+++ b/arch/ia64/include/asm/hpsim.h
@@ -0,0 +1,16 @@
1#ifndef _ASMIA64_HPSIM_H
2#define _ASMIA64_HPSIM_H
3
4#ifndef CONFIG_HP_SIMSERIAL_CONSOLE
5static inline int simcons_register(void) { return 1; }
6#else
7int simcons_register(void);
8#endif
9
10struct tty_driver;
11extern struct tty_driver *hp_simserial_driver;
12
13void ia64_ssc_connect_irq(long intr, long irq);
14void ia64_ctl_trace(long on);
15
16#endif
diff --git a/arch/ia64/include/asm/hugetlb.h b/arch/ia64/include/asm/hugetlb.h
new file mode 100644
index 000000000000..da55c63728e0
--- /dev/null
+++ b/arch/ia64/include/asm/hugetlb.h
@@ -0,0 +1,80 @@
1#ifndef _ASM_IA64_HUGETLB_H
2#define _ASM_IA64_HUGETLB_H
3
4#include <asm/page.h>
5
6
7void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr,
8 unsigned long end, unsigned long floor,
9 unsigned long ceiling);
10
11int prepare_hugepage_range(struct file *file,
12 unsigned long addr, unsigned long len);
13
14static inline int is_hugepage_only_range(struct mm_struct *mm,
15 unsigned long addr,
16 unsigned long len)
17{
18 return (REGION_NUMBER(addr) == RGN_HPAGE ||
19 REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE);
20}
21
22static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
23{
24}
25
26static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
27 pte_t *ptep, pte_t pte)
28{
29 set_pte_at(mm, addr, ptep, pte);
30}
31
32static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
33 unsigned long addr, pte_t *ptep)
34{
35 return ptep_get_and_clear(mm, addr, ptep);
36}
37
38static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
39 unsigned long addr, pte_t *ptep)
40{
41}
42
43static inline int huge_pte_none(pte_t pte)
44{
45 return pte_none(pte);
46}
47
48static inline pte_t huge_pte_wrprotect(pte_t pte)
49{
50 return pte_wrprotect(pte);
51}
52
53static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
54 unsigned long addr, pte_t *ptep)
55{
56 ptep_set_wrprotect(mm, addr, ptep);
57}
58
59static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
60 unsigned long addr, pte_t *ptep,
61 pte_t pte, int dirty)
62{
63 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
64}
65
66static inline pte_t huge_ptep_get(pte_t *ptep)
67{
68 return *ptep;
69}
70
71static inline int arch_prepare_hugepage(struct page *page)
72{
73 return 0;
74}
75
76static inline void arch_release_hugepage(struct page *page)
77{
78}
79
80#endif /* _ASM_IA64_HUGETLB_H */
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h
new file mode 100644
index 000000000000..5c99cbcb8a0d
--- /dev/null
+++ b/arch/ia64/include/asm/hw_irq.h
@@ -0,0 +1,192 @@
1#ifndef _ASM_IA64_HW_IRQ_H
2#define _ASM_IA64_HW_IRQ_H
3
4/*
5 * Copyright (C) 2001-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <linux/interrupt.h>
10#include <linux/sched.h>
11#include <linux/types.h>
12#include <linux/profile.h>
13
14#include <asm/machvec.h>
15#include <asm/ptrace.h>
16#include <asm/smp.h>
17
18#ifndef CONFIG_PARAVIRT
19typedef u8 ia64_vector;
20#else
21typedef u16 ia64_vector;
22#endif
23
24/*
25 * 0 special
26 *
27 * 1,3-14 are reserved from firmware
28 *
29 * 16-255 (vectored external interrupts) are available
30 *
31 * 15 spurious interrupt (see IVR)
32 *
33 * 16 lowest priority, 255 highest priority
34 *
35 * 15 classes of 16 interrupts each.
36 */
37#define IA64_MIN_VECTORED_IRQ 16
38#define IA64_MAX_VECTORED_IRQ 255
39#define IA64_NUM_VECTORS 256
40
41#define AUTO_ASSIGN -1
42
43#define IA64_SPURIOUS_INT_VECTOR 0x0f
44
45/*
46 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
47 */
48#define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */
49#define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
50#define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */
51#define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
52/*
53 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
54 * Use vectors 0x30-0xe7 as the default device vector range for ia64.
55 * Platforms may choose to reduce this range in platform_irq_setup, but the
56 * platform range must fall within
57 * [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR]
58 */
59extern int ia64_first_device_vector;
60extern int ia64_last_device_vector;
61
62#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30
63#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7
64#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector
65#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector
66#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
67#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
68
69#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */
70#define IA64_PERFMON_VECTOR 0xee /* performance monitor interrupt vector */
71#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */
72#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
73#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */
74#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */
75#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */
76
77/* Used for encoding redirected irqs */
78
79#define IA64_IRQ_REDIRECTED (1 << 31)
80
81/* IA64 inter-cpu interrupt related definitions */
82
83#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000
84
85/* Delivery modes for inter-cpu interrupts */
86enum {
87 IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */
88 IA64_IPI_DM_PMI = 0x2, /* pend a PMI */
89 IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */
90 IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */
91 IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */
92};
93
94extern __u8 isa_irq_to_vector_map[16];
95#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)]
96
97struct irq_cfg {
98 ia64_vector vector;
99 cpumask_t domain;
100 cpumask_t old_domain;
101 unsigned move_cleanup_count;
102 u8 move_in_progress : 1;
103};
104extern spinlock_t vector_lock;
105extern struct irq_cfg irq_cfg[NR_IRQS];
106#define irq_to_domain(x) irq_cfg[(x)].domain
107DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq);
108
109extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
110
111#ifdef CONFIG_PARAVIRT_GUEST
112#include <asm/paravirt.h>
113#else
114#define ia64_register_ipi ia64_native_register_ipi
115#define assign_irq_vector ia64_native_assign_irq_vector
116#define free_irq_vector ia64_native_free_irq_vector
117#define register_percpu_irq ia64_native_register_percpu_irq
118#define ia64_resend_irq ia64_native_resend_irq
119#endif
120
121extern void ia64_native_register_ipi(void);
122extern int bind_irq_vector(int irq, int vector, cpumask_t domain);
123extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */
124extern void ia64_native_free_irq_vector (int vector);
125extern int reserve_irq_vector (int vector);
126extern void __setup_vector_irq(int cpu);
127extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
128extern void ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action);
129extern int check_irq_used (int irq);
130extern void destroy_and_reserve_irq (unsigned int irq);
131
132#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG))
133extern int irq_prepare_move(int irq, int cpu);
134extern void irq_complete_move(unsigned int irq);
135#else
136static inline int irq_prepare_move(int irq, int cpu) { return 0; }
137static inline void irq_complete_move(unsigned int irq) {}
138#endif
139
140static inline void ia64_native_resend_irq(unsigned int vector)
141{
142 platform_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0);
143}
144
145/*
146 * Default implementations for the irq-descriptor API:
147 */
148
149extern irq_desc_t irq_desc[NR_IRQS];
150
151#ifndef CONFIG_IA64_GENERIC
152static inline ia64_vector __ia64_irq_to_vector(int irq)
153{
154 return irq_cfg[irq].vector;
155}
156
157static inline unsigned int
158__ia64_local_vector_to_irq (ia64_vector vec)
159{
160 return __get_cpu_var(vector_irq)[vec];
161}
162#endif
163
164/*
165 * Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt
166 * vectors. On smaller systems, there is a one-to-one correspondence between interrupt
167 * vectors and the Linux irq numbers. However, larger systems may have multiple interrupt
168 * domains meaning that the translation from vector number to irq number depends on the
169 * interrupt domain that a CPU belongs to. This API abstracts such platform-dependent
170 * differences and provides a uniform means to translate between vector and irq numbers
171 * and to obtain the irq descriptor for a given irq number.
172 */
173
174/* Extract the IA-64 vector that corresponds to IRQ. */
175static inline ia64_vector
176irq_to_vector (int irq)
177{
178 return platform_irq_to_vector(irq);
179}
180
181/*
182 * Convert the local IA-64 vector to the corresponding irq number. This translation is
183 * done in the context of the interrupt domain that the currently executing CPU belongs
184 * to.
185 */
186static inline unsigned int
187local_vector_to_irq (ia64_vector vec)
188{
189 return platform_local_vector_to_irq(vec);
190}
191
192#endif /* _ASM_IA64_HW_IRQ_H */
diff --git a/arch/ia64/include/asm/ia32.h b/arch/ia64/include/asm/ia32.h
new file mode 100644
index 000000000000..2390ee145aa1
--- /dev/null
+++ b/arch/ia64/include/asm/ia32.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_IA64_IA32_H
2#define _ASM_IA64_IA32_H
3
4
5#include <asm/ptrace.h>
6#include <asm/signal.h>
7
8#define IA32_NR_syscalls 285 /* length of syscall table */
9#define IA32_PAGE_SHIFT 12 /* 4KB pages */
10
11#ifndef __ASSEMBLY__
12
13# ifdef CONFIG_IA32_SUPPORT
14
15#define IA32_PAGE_OFFSET 0xc0000000
16
17extern void ia32_cpu_init (void);
18extern void ia32_mem_init (void);
19extern void ia32_gdt_init (void);
20extern int ia32_exception (struct pt_regs *regs, unsigned long isr);
21extern int ia32_intercept (struct pt_regs *regs, unsigned long isr);
22extern int ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs);
23
24# endif /* !CONFIG_IA32_SUPPORT */
25
26/* Declare this unconditionally, so we don't get warnings for unreachable code. */
27extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
28 sigset_t *set, struct pt_regs *regs);
29#if PAGE_SHIFT > IA32_PAGE_SHIFT
30extern int ia32_copy_ia64_partial_page_list(struct task_struct *,
31 unsigned long);
32extern void ia32_drop_ia64_partial_page_list(struct task_struct *);
33#else
34# define ia32_copy_ia64_partial_page_list(a1, a2) 0
35# define ia32_drop_ia64_partial_page_list(a1) do { ; } while (0)
36#endif
37
38#endif /* !__ASSEMBLY__ */
39
40#endif /* _ASM_IA64_IA32_H */
diff --git a/arch/ia64/include/asm/ia64regs.h b/arch/ia64/include/asm/ia64regs.h
new file mode 100644
index 000000000000..1757f1c11ad4
--- /dev/null
+++ b/arch/ia64/include/asm/ia64regs.h
@@ -0,0 +1,100 @@
1/*
2 * Copyright (C) 2002,2003 Intel Corp.
3 * Jun Nakajima <jun.nakajima@intel.com>
4 * Suresh Siddha <suresh.b.siddha@intel.com>
5 */
6
7#ifndef _ASM_IA64_IA64REGS_H
8#define _ASM_IA64_IA64REGS_H
9
10/*
11 * Register Names for getreg() and setreg().
12 *
13 * The "magic" numbers happen to match the values used by the Intel compiler's
14 * getreg()/setreg() intrinsics.
15 */
16
17/* Special Registers */
18
19#define _IA64_REG_IP 1016 /* getreg only */
20#define _IA64_REG_PSR 1019
21#define _IA64_REG_PSR_L 1019
22
23/* General Integer Registers */
24
25#define _IA64_REG_GP 1025 /* R1 */
26#define _IA64_REG_R8 1032 /* R8 */
27#define _IA64_REG_R9 1033 /* R9 */
28#define _IA64_REG_SP 1036 /* R12 */
29#define _IA64_REG_TP 1037 /* R13 */
30
31/* Application Registers */
32
33#define _IA64_REG_AR_KR0 3072
34#define _IA64_REG_AR_KR1 3073
35#define _IA64_REG_AR_KR2 3074
36#define _IA64_REG_AR_KR3 3075
37#define _IA64_REG_AR_KR4 3076
38#define _IA64_REG_AR_KR5 3077
39#define _IA64_REG_AR_KR6 3078
40#define _IA64_REG_AR_KR7 3079
41#define _IA64_REG_AR_RSC 3088
42#define _IA64_REG_AR_BSP 3089
43#define _IA64_REG_AR_BSPSTORE 3090
44#define _IA64_REG_AR_RNAT 3091
45#define _IA64_REG_AR_FCR 3093
46#define _IA64_REG_AR_EFLAG 3096
47#define _IA64_REG_AR_CSD 3097
48#define _IA64_REG_AR_SSD 3098
49#define _IA64_REG_AR_CFLAG 3099
50#define _IA64_REG_AR_FSR 3100
51#define _IA64_REG_AR_FIR 3101
52#define _IA64_REG_AR_FDR 3102
53#define _IA64_REG_AR_CCV 3104
54#define _IA64_REG_AR_UNAT 3108
55#define _IA64_REG_AR_FPSR 3112
56#define _IA64_REG_AR_ITC 3116
57#define _IA64_REG_AR_PFS 3136
58#define _IA64_REG_AR_LC 3137
59#define _IA64_REG_AR_EC 3138
60
61/* Control Registers */
62
63#define _IA64_REG_CR_DCR 4096
64#define _IA64_REG_CR_ITM 4097
65#define _IA64_REG_CR_IVA 4098
66#define _IA64_REG_CR_PTA 4104
67#define _IA64_REG_CR_IPSR 4112
68#define _IA64_REG_CR_ISR 4113
69#define _IA64_REG_CR_IIP 4115
70#define _IA64_REG_CR_IFA 4116
71#define _IA64_REG_CR_ITIR 4117
72#define _IA64_REG_CR_IIPA 4118
73#define _IA64_REG_CR_IFS 4119
74#define _IA64_REG_CR_IIM 4120
75#define _IA64_REG_CR_IHA 4121
76#define _IA64_REG_CR_LID 4160
77#define _IA64_REG_CR_IVR 4161 /* getreg only */
78#define _IA64_REG_CR_TPR 4162
79#define _IA64_REG_CR_EOI 4163
80#define _IA64_REG_CR_IRR0 4164 /* getreg only */
81#define _IA64_REG_CR_IRR1 4165 /* getreg only */
82#define _IA64_REG_CR_IRR2 4166 /* getreg only */
83#define _IA64_REG_CR_IRR3 4167 /* getreg only */
84#define _IA64_REG_CR_ITV 4168
85#define _IA64_REG_CR_PMV 4169
86#define _IA64_REG_CR_CMCV 4170
87#define _IA64_REG_CR_LRR0 4176
88#define _IA64_REG_CR_LRR1 4177
89
90/* Indirect Registers for getindreg() and setindreg() */
91
92#define _IA64_REG_INDR_CPUID 9000 /* getindreg only */
93#define _IA64_REG_INDR_DBR 9001
94#define _IA64_REG_INDR_IBR 9002
95#define _IA64_REG_INDR_PKR 9003
96#define _IA64_REG_INDR_PMC 9004
97#define _IA64_REG_INDR_PMD 9005
98#define _IA64_REG_INDR_RR 9006
99
100#endif /* _ASM_IA64_IA64REGS_H */
diff --git a/arch/ia64/include/asm/intel_intrin.h b/arch/ia64/include/asm/intel_intrin.h
new file mode 100644
index 000000000000..53cec577558a
--- /dev/null
+++ b/arch/ia64/include/asm/intel_intrin.h
@@ -0,0 +1,161 @@
1#ifndef _ASM_IA64_INTEL_INTRIN_H
2#define _ASM_IA64_INTEL_INTRIN_H
3/*
4 * Intel Compiler Intrinsics
5 *
6 * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
7 * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
8 * Copyright (C) 2005,2006 Hongjiu Lu <hongjiu.lu@intel.com>
9 *
10 */
11#include <ia64intrin.h>
12
13#define ia64_barrier() __memory_barrier()
14
15#define ia64_stop() /* Nothing: As of now stop bit is generated for each
16 * intrinsic
17 */
18
19#define ia64_native_getreg __getReg
20#define ia64_native_setreg __setReg
21
22#define ia64_hint __hint
23#define ia64_hint_pause __hint_pause
24
25#define ia64_mux1_brcst _m64_mux1_brcst
26#define ia64_mux1_mix _m64_mux1_mix
27#define ia64_mux1_shuf _m64_mux1_shuf
28#define ia64_mux1_alt _m64_mux1_alt
29#define ia64_mux1_rev _m64_mux1_rev
30
31#define ia64_mux1(x,v) _m_to_int64(_m64_mux1(_m_from_int64(x), (v)))
32#define ia64_popcnt _m64_popcnt
33#define ia64_getf_exp __getf_exp
34#define ia64_shrp _m64_shrp
35
36#define ia64_tpa __tpa
37#define ia64_invala __invala
38#define ia64_invala_gr __invala_gr
39#define ia64_invala_fr __invala_fr
40#define ia64_nop __nop
41#define ia64_sum __sum
42#define ia64_native_ssm __ssm
43#define ia64_rum __rum
44#define ia64_native_rsm __rsm
45#define ia64_native_fc __fc
46
47#define ia64_ldfs __ldfs
48#define ia64_ldfd __ldfd
49#define ia64_ldfe __ldfe
50#define ia64_ldf8 __ldf8
51#define ia64_ldf_fill __ldf_fill
52
53#define ia64_stfs __stfs
54#define ia64_stfd __stfd
55#define ia64_stfe __stfe
56#define ia64_stf8 __stf8
57#define ia64_stf_spill __stf_spill
58
59#define ia64_mf __mf
60#define ia64_mfa __mfa
61
62#define ia64_fetchadd4_acq __fetchadd4_acq
63#define ia64_fetchadd4_rel __fetchadd4_rel
64#define ia64_fetchadd8_acq __fetchadd8_acq
65#define ia64_fetchadd8_rel __fetchadd8_rel
66
67#define ia64_xchg1 _InterlockedExchange8
68#define ia64_xchg2 _InterlockedExchange16
69#define ia64_xchg4 _InterlockedExchange
70#define ia64_xchg8 _InterlockedExchange64
71
72#define ia64_cmpxchg1_rel _InterlockedCompareExchange8_rel
73#define ia64_cmpxchg1_acq _InterlockedCompareExchange8_acq
74#define ia64_cmpxchg2_rel _InterlockedCompareExchange16_rel
75#define ia64_cmpxchg2_acq _InterlockedCompareExchange16_acq
76#define ia64_cmpxchg4_rel _InterlockedCompareExchange_rel
77#define ia64_cmpxchg4_acq _InterlockedCompareExchange_acq
78#define ia64_cmpxchg8_rel _InterlockedCompareExchange64_rel
79#define ia64_cmpxchg8_acq _InterlockedCompareExchange64_acq
80
81#define __ia64_set_dbr(index, val) \
82 __setIndReg(_IA64_REG_INDR_DBR, index, val)
83#define ia64_set_ibr(index, val) \
84 __setIndReg(_IA64_REG_INDR_IBR, index, val)
85#define ia64_set_pkr(index, val) \
86 __setIndReg(_IA64_REG_INDR_PKR, index, val)
87#define ia64_set_pmc(index, val) \
88 __setIndReg(_IA64_REG_INDR_PMC, index, val)
89#define ia64_set_pmd(index, val) \
90 __setIndReg(_IA64_REG_INDR_PMD, index, val)
91#define ia64_native_set_rr(index, val) \
92 __setIndReg(_IA64_REG_INDR_RR, index, val)
93
94#define ia64_native_get_cpuid(index) \
95 __getIndReg(_IA64_REG_INDR_CPUID, index)
96#define __ia64_get_dbr(index) __getIndReg(_IA64_REG_INDR_DBR, index)
97#define ia64_get_ibr(index) __getIndReg(_IA64_REG_INDR_IBR, index)
98#define ia64_get_pkr(index) __getIndReg(_IA64_REG_INDR_PKR, index)
99#define ia64_get_pmc(index) __getIndReg(_IA64_REG_INDR_PMC, index)
100#define ia64_native_get_pmd(index) __getIndReg(_IA64_REG_INDR_PMD, index)
101#define ia64_native_get_rr(index) __getIndReg(_IA64_REG_INDR_RR, index)
102
103#define ia64_srlz_d __dsrlz
104#define ia64_srlz_i __isrlz
105
106#define ia64_dv_serialize_data()
107#define ia64_dv_serialize_instruction()
108
109#define ia64_st1_rel __st1_rel
110#define ia64_st2_rel __st2_rel
111#define ia64_st4_rel __st4_rel
112#define ia64_st8_rel __st8_rel
113
114/* FIXME: need st4.rel.nta intrinsic */
115#define ia64_st4_rel_nta __st4_rel
116
117#define ia64_ld1_acq __ld1_acq
118#define ia64_ld2_acq __ld2_acq
119#define ia64_ld4_acq __ld4_acq
120#define ia64_ld8_acq __ld8_acq
121
122#define ia64_sync_i __synci
123#define ia64_native_thash __thash
124#define ia64_native_ttag __ttag
125#define ia64_itcd __itcd
126#define ia64_itci __itci
127#define ia64_itrd __itrd
128#define ia64_itri __itri
129#define ia64_ptce __ptce
130#define ia64_ptcl __ptcl
131#define ia64_native_ptcg __ptcg
132#define ia64_native_ptcga __ptcga
133#define ia64_ptri __ptri
134#define ia64_ptrd __ptrd
135#define ia64_dep_mi _m64_dep_mi
136
137/* Values for lfhint in __lfetch and __lfetch_fault */
138
139#define ia64_lfhint_none __lfhint_none
140#define ia64_lfhint_nt1 __lfhint_nt1
141#define ia64_lfhint_nt2 __lfhint_nt2
142#define ia64_lfhint_nta __lfhint_nta
143
144#define ia64_lfetch __lfetch
145#define ia64_lfetch_excl __lfetch_excl
146#define ia64_lfetch_fault __lfetch_fault
147#define ia64_lfetch_fault_excl __lfetch_fault_excl
148
149#define ia64_native_intrin_local_irq_restore(x) \
150do { \
151 if ((x) != 0) { \
152 ia64_native_ssm(IA64_PSR_I); \
153 ia64_srlz_d(); \
154 } else { \
155 ia64_native_rsm(IA64_PSR_I); \
156 } \
157} while (0)
158
159#define __builtin_trap() __break(0);
160
161#endif /* _ASM_IA64_INTEL_INTRIN_H */
diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h
new file mode 100644
index 000000000000..47d686dba1eb
--- /dev/null
+++ b/arch/ia64/include/asm/intrinsics.h
@@ -0,0 +1,241 @@
1#ifndef _ASM_IA64_INTRINSICS_H
2#define _ASM_IA64_INTRINSICS_H
3
4/*
5 * Compiler-dependent intrinsics.
6 *
7 * Copyright (C) 2002-2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11#ifndef __ASSEMBLY__
12
13/* include compiler specific intrinsics */
14#include <asm/ia64regs.h>
15#ifdef __INTEL_COMPILER
16# include <asm/intel_intrin.h>
17#else
18# include <asm/gcc_intrin.h>
19#endif
20
21#define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I)
22
23#define ia64_native_set_rr0_to_rr4(val0, val1, val2, val3, val4) \
24do { \
25 ia64_native_set_rr(0x0000000000000000UL, (val0)); \
26 ia64_native_set_rr(0x2000000000000000UL, (val1)); \
27 ia64_native_set_rr(0x4000000000000000UL, (val2)); \
28 ia64_native_set_rr(0x6000000000000000UL, (val3)); \
29 ia64_native_set_rr(0x8000000000000000UL, (val4)); \
30} while (0)
31
32/*
33 * Force an unresolved reference if someone tries to use
34 * ia64_fetch_and_add() with a bad value.
35 */
36extern unsigned long __bad_size_for_ia64_fetch_and_add (void);
37extern unsigned long __bad_increment_for_ia64_fetch_and_add (void);
38
39#define IA64_FETCHADD(tmp,v,n,sz,sem) \
40({ \
41 switch (sz) { \
42 case 4: \
43 tmp = ia64_fetchadd4_##sem((unsigned int *) v, n); \
44 break; \
45 \
46 case 8: \
47 tmp = ia64_fetchadd8_##sem((unsigned long *) v, n); \
48 break; \
49 \
50 default: \
51 __bad_size_for_ia64_fetch_and_add(); \
52 } \
53})
54
55#define ia64_fetchadd(i,v,sem) \
56({ \
57 __u64 _tmp; \
58 volatile __typeof__(*(v)) *_v = (v); \
59 /* Can't use a switch () here: gcc isn't always smart enough for that... */ \
60 if ((i) == -16) \
61 IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v)), sem); \
62 else if ((i) == -8) \
63 IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v)), sem); \
64 else if ((i) == -4) \
65 IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v)), sem); \
66 else if ((i) == -1) \
67 IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v)), sem); \
68 else if ((i) == 1) \
69 IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v)), sem); \
70 else if ((i) == 4) \
71 IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v)), sem); \
72 else if ((i) == 8) \
73 IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v)), sem); \
74 else if ((i) == 16) \
75 IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v)), sem); \
76 else \
77 _tmp = __bad_increment_for_ia64_fetch_and_add(); \
78 (__typeof__(*(v))) (_tmp); /* return old value */ \
79})
80
81#define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */
82
83/*
84 * This function doesn't exist, so you'll get a linker error if
85 * something tries to do an invalid xchg().
86 */
87extern void ia64_xchg_called_with_bad_pointer (void);
88
89#define __xchg(x,ptr,size) \
90({ \
91 unsigned long __xchg_result; \
92 \
93 switch (size) { \
94 case 1: \
95 __xchg_result = ia64_xchg1((__u8 *)ptr, x); \
96 break; \
97 \
98 case 2: \
99 __xchg_result = ia64_xchg2((__u16 *)ptr, x); \
100 break; \
101 \
102 case 4: \
103 __xchg_result = ia64_xchg4((__u32 *)ptr, x); \
104 break; \
105 \
106 case 8: \
107 __xchg_result = ia64_xchg8((__u64 *)ptr, x); \
108 break; \
109 default: \
110 ia64_xchg_called_with_bad_pointer(); \
111 } \
112 __xchg_result; \
113})
114
115#define xchg(ptr,x) \
116 ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr))))
117
118/*
119 * Atomic compare and exchange. Compare OLD with MEM, if identical,
120 * store NEW in MEM. Return the initial value in MEM. Success is
121 * indicated by comparing RETURN with OLD.
122 */
123
124#define __HAVE_ARCH_CMPXCHG 1
125
126/*
127 * This function doesn't exist, so you'll get a linker error
128 * if something tries to do an invalid cmpxchg().
129 */
130extern long ia64_cmpxchg_called_with_bad_pointer (void);
131
132#define ia64_cmpxchg(sem,ptr,old,new,size) \
133({ \
134 __u64 _o_, _r_; \
135 \
136 switch (size) { \
137 case 1: _o_ = (__u8 ) (long) (old); break; \
138 case 2: _o_ = (__u16) (long) (old); break; \
139 case 4: _o_ = (__u32) (long) (old); break; \
140 case 8: _o_ = (__u64) (long) (old); break; \
141 default: break; \
142 } \
143 switch (size) { \
144 case 1: \
145 _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_); \
146 break; \
147 \
148 case 2: \
149 _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_); \
150 break; \
151 \
152 case 4: \
153 _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_); \
154 break; \
155 \
156 case 8: \
157 _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_); \
158 break; \
159 \
160 default: \
161 _r_ = ia64_cmpxchg_called_with_bad_pointer(); \
162 break; \
163 } \
164 (__typeof__(old)) _r_; \
165})
166
167#define cmpxchg_acq(ptr, o, n) \
168 ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr)))
169#define cmpxchg_rel(ptr, o, n) \
170 ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr)))
171
172/* for compatibility with other platforms: */
173#define cmpxchg(ptr, o, n) cmpxchg_acq((ptr), (o), (n))
174#define cmpxchg64(ptr, o, n) cmpxchg_acq((ptr), (o), (n))
175
176#define cmpxchg_local cmpxchg
177#define cmpxchg64_local cmpxchg64
178
179#ifdef CONFIG_IA64_DEBUG_CMPXCHG
180# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128;
181# define CMPXCHG_BUGCHECK(v) \
182 do { \
183 if (_cmpxchg_bugcheck_count-- <= 0) { \
184 void *ip; \
185 extern int printk(const char *fmt, ...); \
186 ip = (void *) ia64_getreg(_IA64_REG_IP); \
187 printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \
188 break; \
189 } \
190 } while (0)
191#else /* !CONFIG_IA64_DEBUG_CMPXCHG */
192# define CMPXCHG_BUGCHECK_DECL
193# define CMPXCHG_BUGCHECK(v)
194#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */
195
196#endif
197
198#ifdef __KERNEL__
199#include <asm/paravirt_privop.h>
200#endif
201
202#ifndef __ASSEMBLY__
203#if defined(CONFIG_PARAVIRT) && defined(__KERNEL__)
204#define IA64_INTRINSIC_API(name) pv_cpu_ops.name
205#define IA64_INTRINSIC_MACRO(name) paravirt_ ## name
206#else
207#define IA64_INTRINSIC_API(name) ia64_native_ ## name
208#define IA64_INTRINSIC_MACRO(name) ia64_native_ ## name
209#endif
210
211/************************************************/
212/* Instructions paravirtualized for correctness */
213/************************************************/
214/* fc, thash, get_cpuid, get_pmd, get_eflags, set_eflags */
215/* Note that "ttag" and "cover" are also privilege-sensitive; "ttag"
216 * is not currently used (though it may be in a long-format VHPT system!)
217 */
218#define ia64_fc IA64_INTRINSIC_API(fc)
219#define ia64_thash IA64_INTRINSIC_API(thash)
220#define ia64_get_cpuid IA64_INTRINSIC_API(get_cpuid)
221#define ia64_get_pmd IA64_INTRINSIC_API(get_pmd)
222
223
224/************************************************/
225/* Instructions paravirtualized for performance */
226/************************************************/
227#define ia64_ssm IA64_INTRINSIC_MACRO(ssm)
228#define ia64_rsm IA64_INTRINSIC_MACRO(rsm)
229#define ia64_getreg IA64_INTRINSIC_API(getreg)
230#define ia64_setreg IA64_INTRINSIC_API(setreg)
231#define ia64_set_rr IA64_INTRINSIC_API(set_rr)
232#define ia64_get_rr IA64_INTRINSIC_API(get_rr)
233#define ia64_ptcga IA64_INTRINSIC_API(ptcga)
234#define ia64_get_psr_i IA64_INTRINSIC_API(get_psr_i)
235#define ia64_intrin_local_irq_restore \
236 IA64_INTRINSIC_API(intrin_local_irq_restore)
237#define ia64_set_rr0_to_rr4 IA64_INTRINSIC_API(set_rr0_to_rr4)
238
239#endif /* !__ASSEMBLY__ */
240
241#endif /* _ASM_IA64_INTRINSICS_H */
diff --git a/arch/ia64/include/asm/io.h b/arch/ia64/include/asm/io.h
new file mode 100644
index 000000000000..260a85ac9d6a
--- /dev/null
+++ b/arch/ia64/include/asm/io.h
@@ -0,0 +1,459 @@
1#ifndef _ASM_IA64_IO_H
2#define _ASM_IA64_IO_H
3
4/*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
21
22/* We don't use IO slowdowns on the ia64, but.. */
23#define __SLOW_DOWN_IO do { } while (0)
24#define SLOW_DOWN_IO do { } while (0)
25
26#define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
27
28/*
29 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
30 * large machines may have multiple other I/O spaces so we can't place any a priori limit
31 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
32 */
33#define IO_SPACE_LIMIT 0xffffffffffffffffUL
34
35#define MAX_IO_SPACES_BITS 8
36#define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
37#define IO_SPACE_BITS 24
38#define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
39
40#define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
41#define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
42#define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
43
44#define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
45
46struct io_space {
47 unsigned long mmio_base; /* base in MMIO space */
48 int sparse;
49};
50
51extern struct io_space io_space[];
52extern unsigned int num_io_spaces;
53
54# ifdef __KERNEL__
55
56/*
57 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
58 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
59 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
60 *
61 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
62 * code that uses bare port numbers without the prerequisite pci_iomap().
63 */
64#define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
65#define PIO_MASK (PIO_OFFSET - 1)
66#define PIO_RESERVED __IA64_UNCACHED_OFFSET
67#define HAVE_ARCH_PIO_SIZE
68
69#include <asm/intrinsics.h>
70#include <asm/machvec.h>
71#include <asm/page.h>
72#include <asm/system.h>
73#include <asm-generic/iomap.h>
74
75/*
76 * Change virtual addresses to physical addresses and vv.
77 */
78static inline unsigned long
79virt_to_phys (volatile void *address)
80{
81 return (unsigned long) address - PAGE_OFFSET;
82}
83
84static inline void*
85phys_to_virt (unsigned long address)
86{
87 return (void *) (address + PAGE_OFFSET);
88}
89
90#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
91extern u64 kern_mem_attribute (unsigned long phys_addr, unsigned long size);
92extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
93extern int valid_mmap_phys_addr_range (unsigned long pfn, size_t count);
94
95/*
96 * The following two macros are deprecated and scheduled for removal.
97 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
98 */
99#define bus_to_virt phys_to_virt
100#define virt_to_bus virt_to_phys
101#define page_to_bus page_to_phys
102
103# endif /* KERNEL */
104
105/*
106 * Memory fence w/accept. This should never be used in code that is
107 * not IA-64 specific.
108 */
109#define __ia64_mf_a() ia64_mfa()
110
111/**
112 * ___ia64_mmiowb - I/O write barrier
113 *
114 * Ensure ordering of I/O space writes. This will make sure that writes
115 * following the barrier will arrive after all previous writes. For most
116 * ia64 platforms, this is a simple 'mf.a' instruction.
117 *
118 * See Documentation/DocBook/deviceiobook.tmpl for more information.
119 */
120static inline void ___ia64_mmiowb(void)
121{
122 ia64_mfa();
123}
124
125static inline void*
126__ia64_mk_io_addr (unsigned long port)
127{
128 struct io_space *space;
129 unsigned long offset;
130
131 space = &io_space[IO_SPACE_NR(port)];
132 port = IO_SPACE_PORT(port);
133 if (space->sparse)
134 offset = IO_SPACE_SPARSE_ENCODING(port);
135 else
136 offset = port;
137
138 return (void *) (space->mmio_base | offset);
139}
140
141#define __ia64_inb ___ia64_inb
142#define __ia64_inw ___ia64_inw
143#define __ia64_inl ___ia64_inl
144#define __ia64_outb ___ia64_outb
145#define __ia64_outw ___ia64_outw
146#define __ia64_outl ___ia64_outl
147#define __ia64_readb ___ia64_readb
148#define __ia64_readw ___ia64_readw
149#define __ia64_readl ___ia64_readl
150#define __ia64_readq ___ia64_readq
151#define __ia64_readb_relaxed ___ia64_readb
152#define __ia64_readw_relaxed ___ia64_readw
153#define __ia64_readl_relaxed ___ia64_readl
154#define __ia64_readq_relaxed ___ia64_readq
155#define __ia64_writeb ___ia64_writeb
156#define __ia64_writew ___ia64_writew
157#define __ia64_writel ___ia64_writel
158#define __ia64_writeq ___ia64_writeq
159#define __ia64_mmiowb ___ia64_mmiowb
160
161/*
162 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
163 * that the access has completed before executing other I/O accesses. Since we're doing
164 * the accesses through an uncachable (UC) translation, the CPU will execute them in
165 * program order. However, we still need to tell the compiler not to shuffle them around
166 * during optimization, which is why we use "volatile" pointers.
167 */
168
169static inline unsigned int
170___ia64_inb (unsigned long port)
171{
172 volatile unsigned char *addr = __ia64_mk_io_addr(port);
173 unsigned char ret;
174
175 ret = *addr;
176 __ia64_mf_a();
177 return ret;
178}
179
180static inline unsigned int
181___ia64_inw (unsigned long port)
182{
183 volatile unsigned short *addr = __ia64_mk_io_addr(port);
184 unsigned short ret;
185
186 ret = *addr;
187 __ia64_mf_a();
188 return ret;
189}
190
191static inline unsigned int
192___ia64_inl (unsigned long port)
193{
194 volatile unsigned int *addr = __ia64_mk_io_addr(port);
195 unsigned int ret;
196
197 ret = *addr;
198 __ia64_mf_a();
199 return ret;
200}
201
202static inline void
203___ia64_outb (unsigned char val, unsigned long port)
204{
205 volatile unsigned char *addr = __ia64_mk_io_addr(port);
206
207 *addr = val;
208 __ia64_mf_a();
209}
210
211static inline void
212___ia64_outw (unsigned short val, unsigned long port)
213{
214 volatile unsigned short *addr = __ia64_mk_io_addr(port);
215
216 *addr = val;
217 __ia64_mf_a();
218}
219
220static inline void
221___ia64_outl (unsigned int val, unsigned long port)
222{
223 volatile unsigned int *addr = __ia64_mk_io_addr(port);
224
225 *addr = val;
226 __ia64_mf_a();
227}
228
229static inline void
230__insb (unsigned long port, void *dst, unsigned long count)
231{
232 unsigned char *dp = dst;
233
234 while (count--)
235 *dp++ = platform_inb(port);
236}
237
238static inline void
239__insw (unsigned long port, void *dst, unsigned long count)
240{
241 unsigned short *dp = dst;
242
243 while (count--)
244 *dp++ = platform_inw(port);
245}
246
247static inline void
248__insl (unsigned long port, void *dst, unsigned long count)
249{
250 unsigned int *dp = dst;
251
252 while (count--)
253 *dp++ = platform_inl(port);
254}
255
256static inline void
257__outsb (unsigned long port, const void *src, unsigned long count)
258{
259 const unsigned char *sp = src;
260
261 while (count--)
262 platform_outb(*sp++, port);
263}
264
265static inline void
266__outsw (unsigned long port, const void *src, unsigned long count)
267{
268 const unsigned short *sp = src;
269
270 while (count--)
271 platform_outw(*sp++, port);
272}
273
274static inline void
275__outsl (unsigned long port, const void *src, unsigned long count)
276{
277 const unsigned int *sp = src;
278
279 while (count--)
280 platform_outl(*sp++, port);
281}
282
283/*
284 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
285 * specification regarding legacy I/O support. Thus, we have to make these operations
286 * platform dependent...
287 */
288#define __inb platform_inb
289#define __inw platform_inw
290#define __inl platform_inl
291#define __outb platform_outb
292#define __outw platform_outw
293#define __outl platform_outl
294#define __mmiowb platform_mmiowb
295
296#define inb(p) __inb(p)
297#define inw(p) __inw(p)
298#define inl(p) __inl(p)
299#define insb(p,d,c) __insb(p,d,c)
300#define insw(p,d,c) __insw(p,d,c)
301#define insl(p,d,c) __insl(p,d,c)
302#define outb(v,p) __outb(v,p)
303#define outw(v,p) __outw(v,p)
304#define outl(v,p) __outl(v,p)
305#define outsb(p,s,c) __outsb(p,s,c)
306#define outsw(p,s,c) __outsw(p,s,c)
307#define outsl(p,s,c) __outsl(p,s,c)
308#define mmiowb() __mmiowb()
309
310/*
311 * The address passed to these functions are ioremap()ped already.
312 *
313 * We need these to be machine vectors since some platforms don't provide
314 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
315 * a good idea). Writes are ok though for all existing ia64 platforms (and
316 * hopefully it'll stay that way).
317 */
318static inline unsigned char
319___ia64_readb (const volatile void __iomem *addr)
320{
321 return *(volatile unsigned char __force *)addr;
322}
323
324static inline unsigned short
325___ia64_readw (const volatile void __iomem *addr)
326{
327 return *(volatile unsigned short __force *)addr;
328}
329
330static inline unsigned int
331___ia64_readl (const volatile void __iomem *addr)
332{
333 return *(volatile unsigned int __force *) addr;
334}
335
336static inline unsigned long
337___ia64_readq (const volatile void __iomem *addr)
338{
339 return *(volatile unsigned long __force *) addr;
340}
341
342static inline void
343__writeb (unsigned char val, volatile void __iomem *addr)
344{
345 *(volatile unsigned char __force *) addr = val;
346}
347
348static inline void
349__writew (unsigned short val, volatile void __iomem *addr)
350{
351 *(volatile unsigned short __force *) addr = val;
352}
353
354static inline void
355__writel (unsigned int val, volatile void __iomem *addr)
356{
357 *(volatile unsigned int __force *) addr = val;
358}
359
360static inline void
361__writeq (unsigned long val, volatile void __iomem *addr)
362{
363 *(volatile unsigned long __force *) addr = val;
364}
365
366#define __readb platform_readb
367#define __readw platform_readw
368#define __readl platform_readl
369#define __readq platform_readq
370#define __readb_relaxed platform_readb_relaxed
371#define __readw_relaxed platform_readw_relaxed
372#define __readl_relaxed platform_readl_relaxed
373#define __readq_relaxed platform_readq_relaxed
374
375#define readb(a) __readb((a))
376#define readw(a) __readw((a))
377#define readl(a) __readl((a))
378#define readq(a) __readq((a))
379#define readb_relaxed(a) __readb_relaxed((a))
380#define readw_relaxed(a) __readw_relaxed((a))
381#define readl_relaxed(a) __readl_relaxed((a))
382#define readq_relaxed(a) __readq_relaxed((a))
383#define __raw_readb readb
384#define __raw_readw readw
385#define __raw_readl readl
386#define __raw_readq readq
387#define __raw_readb_relaxed readb_relaxed
388#define __raw_readw_relaxed readw_relaxed
389#define __raw_readl_relaxed readl_relaxed
390#define __raw_readq_relaxed readq_relaxed
391#define writeb(v,a) __writeb((v), (a))
392#define writew(v,a) __writew((v), (a))
393#define writel(v,a) __writel((v), (a))
394#define writeq(v,a) __writeq((v), (a))
395#define __raw_writeb writeb
396#define __raw_writew writew
397#define __raw_writel writel
398#define __raw_writeq writeq
399
400#ifndef inb_p
401# define inb_p inb
402#endif
403#ifndef inw_p
404# define inw_p inw
405#endif
406#ifndef inl_p
407# define inl_p inl
408#endif
409
410#ifndef outb_p
411# define outb_p outb
412#endif
413#ifndef outw_p
414# define outw_p outw
415#endif
416#ifndef outl_p
417# define outl_p outl
418#endif
419
420# ifdef __KERNEL__
421
422extern void __iomem * ioremap(unsigned long offset, unsigned long size);
423extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
424extern void iounmap (volatile void __iomem *addr);
425
426/*
427 * String version of IO memory access ops:
428 */
429extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
430extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
431extern void memset_io(volatile void __iomem *s, int c, long n);
432
433# endif /* __KERNEL__ */
434
435/*
436 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
437 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
438 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
439 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
440 * over BIO-level virtual merging.
441 */
442extern unsigned long ia64_max_iommu_merge_mask;
443#if 1
444#define BIO_VMERGE_BOUNDARY 0
445#else
446/*
447 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
448 * replaced by dma_merge_mask() or something of that sort. Note: the only way
449 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
450 * expanded into:
451 *
452 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
453 *
454 * which is precisely what we want.
455 */
456#define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
457#endif
458
459#endif /* _ASM_IA64_IO_H */
diff --git a/arch/ia64/include/asm/ioctl.h b/arch/ia64/include/asm/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/arch/ia64/include/asm/ioctl.h
@@ -0,0 +1 @@
#include <asm-generic/ioctl.h>
diff --git a/arch/ia64/include/asm/ioctls.h b/arch/ia64/include/asm/ioctls.h
new file mode 100644
index 000000000000..f41b636a0bf6
--- /dev/null
+++ b/arch/ia64/include/asm/ioctls.h
@@ -0,0 +1,93 @@
1#ifndef _ASM_IA64_IOCTLS_H
2#define _ASM_IA64_IOCTLS_H
3
4/*
5 * Based on <asm-i386/ioctls.h>
6 *
7 * Modified 1998, 1999, 2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#include <asm/ioctl.h>
12
13/* 0x54 is just a magic number to make these relatively unique ('T') */
14
15#define TCGETS 0x5401
16#define TCSETS 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
17#define TCSETSW 0x5403
18#define TCSETSF 0x5404
19#define TCGETA 0x5405
20#define TCSETA 0x5406
21#define TCSETAW 0x5407
22#define TCSETAF 0x5408
23#define TCSBRK 0x5409
24#define TCXONC 0x540A
25#define TCFLSH 0x540B
26#define TIOCEXCL 0x540C
27#define TIOCNXCL 0x540D
28#define TIOCSCTTY 0x540E
29#define TIOCGPGRP 0x540F
30#define TIOCSPGRP 0x5410
31#define TIOCOUTQ 0x5411
32#define TIOCSTI 0x5412
33#define TIOCGWINSZ 0x5413
34#define TIOCSWINSZ 0x5414
35#define TIOCMGET 0x5415
36#define TIOCMBIS 0x5416
37#define TIOCMBIC 0x5417
38#define TIOCMSET 0x5418
39#define TIOCGSOFTCAR 0x5419
40#define TIOCSSOFTCAR 0x541A
41#define FIONREAD 0x541B
42#define TIOCINQ FIONREAD
43#define TIOCLINUX 0x541C
44#define TIOCCONS 0x541D
45#define TIOCGSERIAL 0x541E
46#define TIOCSSERIAL 0x541F
47#define TIOCPKT 0x5420
48#define FIONBIO 0x5421
49#define TIOCNOTTY 0x5422
50#define TIOCSETD 0x5423
51#define TIOCGETD 0x5424
52#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
53#define TIOCSBRK 0x5427 /* BSD compatibility */
54#define TIOCCBRK 0x5428 /* BSD compatibility */
55#define TIOCGSID 0x5429 /* Return the session ID of FD */
56#define TCGETS2 _IOR('T',0x2A, struct termios2)
57#define TCSETS2 _IOW('T',0x2B, struct termios2)
58#define TCSETSW2 _IOW('T',0x2C, struct termios2)
59#define TCSETSF2 _IOW('T',0x2D, struct termios2)
60#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
61#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
62
63#define FIONCLEX 0x5450 /* these numbers need to be adjusted. */
64#define FIOCLEX 0x5451
65#define FIOASYNC 0x5452
66#define TIOCSERCONFIG 0x5453
67#define TIOCSERGWILD 0x5454
68#define TIOCSERSWILD 0x5455
69#define TIOCGLCKTRMIOS 0x5456
70#define TIOCSLCKTRMIOS 0x5457
71#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
72#define TIOCSERGETLSR 0x5459 /* Get line status register */
73#define TIOCSERGETMULTI 0x545A /* Get multiport config */
74#define TIOCSERSETMULTI 0x545B /* Set multiport config */
75
76#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
77#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
78#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
79#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
80#define FIOQSIZE 0x5460
81
82/* Used for packet mode */
83#define TIOCPKT_DATA 0
84#define TIOCPKT_FLUSHREAD 1
85#define TIOCPKT_FLUSHWRITE 2
86#define TIOCPKT_STOP 4
87#define TIOCPKT_START 8
88#define TIOCPKT_NOSTOP 16
89#define TIOCPKT_DOSTOP 32
90
91#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
92
93#endif /* _ASM_IA64_IOCTLS_H */
diff --git a/arch/ia64/include/asm/iosapic.h b/arch/ia64/include/asm/iosapic.h
new file mode 100644
index 000000000000..b9c102e15f22
--- /dev/null
+++ b/arch/ia64/include/asm/iosapic.h
@@ -0,0 +1,126 @@
1#ifndef __ASM_IA64_IOSAPIC_H
2#define __ASM_IA64_IOSAPIC_H
3
4#define IOSAPIC_REG_SELECT 0x0
5#define IOSAPIC_WINDOW 0x10
6#define IOSAPIC_EOI 0x40
7
8#define IOSAPIC_VERSION 0x1
9
10/*
11 * Redirection table entry
12 */
13#define IOSAPIC_RTE_LOW(i) (0x10+i*2)
14#define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
15
16#define IOSAPIC_DEST_SHIFT 16
17
18/*
19 * Delivery mode
20 */
21#define IOSAPIC_DELIVERY_SHIFT 8
22#define IOSAPIC_FIXED 0x0
23#define IOSAPIC_LOWEST_PRIORITY 0x1
24#define IOSAPIC_PMI 0x2
25#define IOSAPIC_NMI 0x4
26#define IOSAPIC_INIT 0x5
27#define IOSAPIC_EXTINT 0x7
28
29/*
30 * Interrupt polarity
31 */
32#define IOSAPIC_POLARITY_SHIFT 13
33#define IOSAPIC_POL_HIGH 0
34#define IOSAPIC_POL_LOW 1
35
36/*
37 * Trigger mode
38 */
39#define IOSAPIC_TRIGGER_SHIFT 15
40#define IOSAPIC_EDGE 0
41#define IOSAPIC_LEVEL 1
42
43/*
44 * Mask bit
45 */
46
47#define IOSAPIC_MASK_SHIFT 16
48#define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
49
50#define IOSAPIC_VECTOR_MASK 0xffffff00
51
52#ifndef __ASSEMBLY__
53
54#ifdef CONFIG_IOSAPIC
55
56#define NR_IOSAPICS 256
57
58#ifdef CONFIG_PARAVIRT_GUEST
59#include <asm/paravirt.h>
60#else
61#define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init
62#define __iosapic_read __ia64_native_iosapic_read
63#define __iosapic_write __ia64_native_iosapic_write
64#define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip
65#endif
66
67extern void __init ia64_native_iosapic_pcat_compat_init(void);
68extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
69
70static inline unsigned int
71__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
72{
73 writel(reg, iosapic + IOSAPIC_REG_SELECT);
74 return readl(iosapic + IOSAPIC_WINDOW);
75}
76
77static inline void
78__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
79{
80 writel(reg, iosapic + IOSAPIC_REG_SELECT);
81 writel(val, iosapic + IOSAPIC_WINDOW);
82}
83
84static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
85{
86 writel(vector, iosapic + IOSAPIC_EOI);
87}
88
89extern void __init iosapic_system_init (int pcat_compat);
90extern int __devinit iosapic_init (unsigned long address,
91 unsigned int gsi_base);
92#ifdef CONFIG_HOTPLUG
93extern int iosapic_remove (unsigned int gsi_base);
94#else
95#define iosapic_remove(gsi_base) (-EINVAL)
96#endif /* CONFIG_HOTPLUG */
97extern int gsi_to_irq (unsigned int gsi);
98extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
99 unsigned long trigger);
100extern void iosapic_unregister_intr (unsigned int irq);
101extern void __devinit iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
102 unsigned long polarity,
103 unsigned long trigger);
104extern int __init iosapic_register_platform_intr (u32 int_type,
105 unsigned int gsi,
106 int pmi_vector,
107 u16 eid, u16 id,
108 unsigned long polarity,
109 unsigned long trigger);
110
111#ifdef CONFIG_NUMA
112extern void __devinit map_iosapic_to_node (unsigned int, int);
113#endif
114#else
115#define iosapic_system_init(pcat_compat) do { } while (0)
116#define iosapic_init(address,gsi_base) (-EINVAL)
117#define iosapic_remove(gsi_base) (-ENODEV)
118#define iosapic_register_intr(gsi,polarity,trigger) (gsi)
119#define iosapic_unregister_intr(irq) do { } while (0)
120#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0)
121#define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
122 polarity,trigger) (gsi)
123#endif
124
125# endif /* !__ASSEMBLY__ */
126#endif /* __ASM_IA64_IOSAPIC_H */
diff --git a/arch/ia64/include/asm/ipcbuf.h b/arch/ia64/include/asm/ipcbuf.h
new file mode 100644
index 000000000000..079899ae7d32
--- /dev/null
+++ b/arch/ia64/include/asm/ipcbuf.h
@@ -0,0 +1,28 @@
1#ifndef _ASM_IA64_IPCBUF_H
2#define _ASM_IA64_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit seq
11 * - 2 miscellaneous 64-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid_t uid;
18 __kernel_gid_t gid;
19 __kernel_uid_t cuid;
20 __kernel_gid_t cgid;
21 __kernel_mode_t mode;
22 unsigned short seq;
23 unsigned short __pad1;
24 unsigned long __unused1;
25 unsigned long __unused2;
26};
27
28#endif /* _ASM_IA64_IPCBUF_H */
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
new file mode 100644
index 000000000000..3627116fb0e2
--- /dev/null
+++ b/arch/ia64/include/asm/irq.h
@@ -0,0 +1,34 @@
1#ifndef _ASM_IA64_IRQ_H
2#define _ASM_IA64_IRQ_H
3
4/*
5 * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 *
9 * 11/24/98 S.Eranian updated TIMER_IRQ and irq_canonicalize
10 * 01/20/99 S.Eranian added keyboard interrupt
11 * 02/29/00 D.Mosberger moved most things into hw_irq.h
12 */
13
14#include <linux/types.h>
15#include <linux/cpumask.h>
16#include <asm-ia64/nr-irqs.h>
17
18static __inline__ int
19irq_canonicalize (int irq)
20{
21 /*
22 * We do the legacy thing here of pretending that irqs < 16
23 * are 8259 irqs. This really shouldn't be necessary at all,
24 * but we keep it here as serial.c still uses it...
25 */
26 return ((irq == 2) ? 9 : irq);
27}
28
29extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
30bool is_affinity_mask_valid(cpumask_t cpumask);
31
32#define is_affinity_mask_valid is_affinity_mask_valid
33
34#endif /* _ASM_IA64_IRQ_H */
diff --git a/arch/ia64/include/asm/irq_regs.h b/arch/ia64/include/asm/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/arch/ia64/include/asm/irq_regs.h
@@ -0,0 +1 @@
#include <asm-generic/irq_regs.h>
diff --git a/arch/ia64/include/asm/kdebug.h b/arch/ia64/include/asm/kdebug.h
new file mode 100644
index 000000000000..d11a69855036
--- /dev/null
+++ b/arch/ia64/include/asm/kdebug.h
@@ -0,0 +1,57 @@
1#ifndef _IA64_KDEBUG_H
2#define _IA64_KDEBUG_H 1
3/*
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) Intel Corporation, 2005
19 *
20 * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
21 * <anil.s.keshavamurthy@intel.com> adopted from
22 * include/asm-x86_64/kdebug.h
23 *
24 * 2005-Oct Keith Owens <kaos@sgi.com>. Expand notify_die to cover more
25 * events.
26 */
27
28enum die_val {
29 DIE_BREAK = 1,
30 DIE_FAULT,
31 DIE_OOPS,
32 DIE_MACHINE_HALT,
33 DIE_MACHINE_RESTART,
34 DIE_MCA_MONARCH_ENTER,
35 DIE_MCA_MONARCH_PROCESS,
36 DIE_MCA_MONARCH_LEAVE,
37 DIE_MCA_SLAVE_ENTER,
38 DIE_MCA_SLAVE_PROCESS,
39 DIE_MCA_SLAVE_LEAVE,
40 DIE_MCA_RENDZVOUS_ENTER,
41 DIE_MCA_RENDZVOUS_PROCESS,
42 DIE_MCA_RENDZVOUS_LEAVE,
43 DIE_MCA_NEW_TIMEOUT,
44 DIE_INIT_ENTER,
45 DIE_INIT_MONARCH_ENTER,
46 DIE_INIT_MONARCH_PROCESS,
47 DIE_INIT_MONARCH_LEAVE,
48 DIE_INIT_SLAVE_ENTER,
49 DIE_INIT_SLAVE_PROCESS,
50 DIE_INIT_SLAVE_LEAVE,
51 DIE_KDEBUG_ENTER,
52 DIE_KDEBUG_LEAVE,
53 DIE_KDUMP_ENTER,
54 DIE_KDUMP_LEAVE,
55};
56
57#endif
diff --git a/arch/ia64/include/asm/kexec.h b/arch/ia64/include/asm/kexec.h
new file mode 100644
index 000000000000..541be835fc5a
--- /dev/null
+++ b/arch/ia64/include/asm/kexec.h
@@ -0,0 +1,44 @@
1#ifndef _ASM_IA64_KEXEC_H
2#define _ASM_IA64_KEXEC_H
3
4
5/* Maximum physical address we can use pages from */
6#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
7/* Maximum address we can reach in physical address mode */
8#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
9/* Maximum address we can use for the control code buffer */
10#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
11
12#define KEXEC_CONTROL_CODE_SIZE (8192 + 8192 + 4096)
13
14/* The native architecture */
15#define KEXEC_ARCH KEXEC_ARCH_IA_64
16
17#define kexec_flush_icache_page(page) do { \
18 unsigned long page_addr = (unsigned long)page_address(page); \
19 flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
20 } while(0)
21
22extern struct kimage *ia64_kimage;
23extern const unsigned int relocate_new_kernel_size;
24extern void relocate_new_kernel(unsigned long, unsigned long,
25 struct ia64_boot_param *, unsigned long);
26static inline void
27crash_setup_regs(struct pt_regs *newregs, struct pt_regs *oldregs)
28{
29}
30extern struct resource efi_memmap_res;
31extern struct resource boot_param_res;
32extern void kdump_smp_send_stop(void);
33extern void kdump_smp_send_init(void);
34extern void kexec_disable_iosapic(void);
35extern void crash_save_this_cpu(void);
36struct rsvd_region;
37extern unsigned long kdump_find_rsvd_region(unsigned long size,
38 struct rsvd_region *rsvd_regions, int n);
39extern void kdump_cpu_freeze(struct unw_frame_info *info, void *arg);
40extern int kdump_status[];
41extern atomic_t kdump_cpu_freezed;
42extern atomic_t kdump_in_progress;
43
44#endif /* _ASM_IA64_KEXEC_H */
diff --git a/arch/ia64/include/asm/kmap_types.h b/arch/ia64/include/asm/kmap_types.h
new file mode 100644
index 000000000000..5d1658aa2b3b
--- /dev/null
+++ b/arch/ia64/include/asm/kmap_types.h
@@ -0,0 +1,30 @@
1#ifndef _ASM_IA64_KMAP_TYPES_H
2#define _ASM_IA64_KMAP_TYPES_H
3
4
5#ifdef CONFIG_DEBUG_HIGHMEM
6# define D(n) __KM_FENCE_##n ,
7#else
8# define D(n)
9#endif
10
11enum km_type {
12D(0) KM_BOUNCE_READ,
13D(1) KM_SKB_SUNRPC_DATA,
14D(2) KM_SKB_DATA_SOFTIRQ,
15D(3) KM_USER0,
16D(4) KM_USER1,
17D(5) KM_BIO_SRC_IRQ,
18D(6) KM_BIO_DST_IRQ,
19D(7) KM_PTE0,
20D(8) KM_PTE1,
21D(9) KM_IRQ0,
22D(10) KM_IRQ1,
23D(11) KM_SOFTIRQ0,
24D(12) KM_SOFTIRQ1,
25D(13) KM_TYPE_NR
26};
27
28#undef D
29
30#endif /* _ASM_IA64_KMAP_TYPES_H */
diff --git a/arch/ia64/include/asm/kprobes.h b/arch/ia64/include/asm/kprobes.h
new file mode 100644
index 000000000000..dbf83fb28db3
--- /dev/null
+++ b/arch/ia64/include/asm/kprobes.h
@@ -0,0 +1,132 @@
1#ifndef _ASM_KPROBES_H
2#define _ASM_KPROBES_H
3/*
4 * Kernel Probes (KProbes)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) IBM Corporation, 2002, 2004
21 * Copyright (C) Intel Corporation, 2005
22 *
23 * 2005-Apr Rusty Lynch <rusty.lynch@intel.com> and Anil S Keshavamurthy
24 * <anil.s.keshavamurthy@intel.com> adapted from i386
25 */
26#include <linux/types.h>
27#include <linux/ptrace.h>
28#include <linux/percpu.h>
29#include <asm/break.h>
30
31#define __ARCH_WANT_KPROBES_INSN_SLOT
32#define MAX_INSN_SIZE 2 /* last half is for kprobe-booster */
33#define BREAK_INST (long)(__IA64_BREAK_KPROBE << 6)
34#define NOP_M_INST (long)(1<<27)
35#define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \
36 (0x1L << 12) | /* many */ \
37 (((i1) & 1) << 36) | ((i2) << 13))) /* imm */
38
39typedef union cmp_inst {
40 struct {
41 unsigned long long qp : 6;
42 unsigned long long p1 : 6;
43 unsigned long long c : 1;
44 unsigned long long r2 : 7;
45 unsigned long long r3 : 7;
46 unsigned long long p2 : 6;
47 unsigned long long ta : 1;
48 unsigned long long x2 : 2;
49 unsigned long long tb : 1;
50 unsigned long long opcode : 4;
51 unsigned long long reserved : 23;
52 }f;
53 unsigned long long l;
54} cmp_inst_t;
55
56struct kprobe;
57
58typedef struct _bundle {
59 struct {
60 unsigned long long template : 5;
61 unsigned long long slot0 : 41;
62 unsigned long long slot1_p0 : 64-46;
63 } quad0;
64 struct {
65 unsigned long long slot1_p1 : 41 - (64-46);
66 unsigned long long slot2 : 41;
67 } quad1;
68} __attribute__((__aligned__(16))) bundle_t;
69
70struct prev_kprobe {
71 struct kprobe *kp;
72 unsigned long status;
73};
74
75#define MAX_PARAM_RSE_SIZE (0x60+0x60/0x3f)
76/* per-cpu kprobe control block */
77#define ARCH_PREV_KPROBE_SZ 2
78struct kprobe_ctlblk {
79 unsigned long kprobe_status;
80 struct pt_regs jprobe_saved_regs;
81 unsigned long jprobes_saved_stacked_regs[MAX_PARAM_RSE_SIZE];
82 unsigned long *bsp;
83 unsigned long cfm;
84 atomic_t prev_kprobe_index;
85 struct prev_kprobe prev_kprobe[ARCH_PREV_KPROBE_SZ];
86};
87
88#define kretprobe_blacklist_size 0
89
90#define SLOT0_OPCODE_SHIFT (37)
91#define SLOT1_p1_OPCODE_SHIFT (37 - (64-46))
92#define SLOT2_OPCODE_SHIFT (37)
93
94#define INDIRECT_CALL_OPCODE (1)
95#define IP_RELATIVE_CALL_OPCODE (5)
96#define IP_RELATIVE_BRANCH_OPCODE (4)
97#define IP_RELATIVE_PREDICT_OPCODE (7)
98#define LONG_BRANCH_OPCODE (0xC)
99#define LONG_CALL_OPCODE (0xD)
100#define flush_insn_slot(p) do { } while (0)
101
102typedef struct kprobe_opcode {
103 bundle_t bundle;
104} kprobe_opcode_t;
105
106struct fnptr {
107 unsigned long ip;
108 unsigned long gp;
109};
110
111/* Architecture specific copy of original instruction*/
112struct arch_specific_insn {
113 /* copy of the instruction to be emulated */
114 kprobe_opcode_t *insn;
115 #define INST_FLAG_FIX_RELATIVE_IP_ADDR 1
116 #define INST_FLAG_FIX_BRANCH_REG 2
117 #define INST_FLAG_BREAK_INST 4
118 #define INST_FLAG_BOOSTABLE 8
119 unsigned long inst_flag;
120 unsigned short target_br_reg;
121 unsigned short slot;
122};
123
124extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
125extern int kprobe_exceptions_notify(struct notifier_block *self,
126 unsigned long val, void *data);
127
128extern void invalidate_stacked_regs(void);
129extern void flush_register_stack(void);
130extern void arch_remove_kprobe(struct kprobe *p);
131
132#endif /* _ASM_KPROBES_H */
diff --git a/arch/ia64/include/asm/kregs.h b/arch/ia64/include/asm/kregs.h
new file mode 100644
index 000000000000..aefcdfee7f23
--- /dev/null
+++ b/arch/ia64/include/asm/kregs.h
@@ -0,0 +1,165 @@
1#ifndef _ASM_IA64_KREGS_H
2#define _ASM_IA64_KREGS_H
3
4/*
5 * Copyright (C) 2001-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * This file defines the kernel register usage convention used by Linux/ia64.
10 */
11
12/*
13 * Kernel registers:
14 */
15#define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */
16#define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */
17#define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */
18#define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
19#define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */
20#define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */
21#define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */
22
23#define _IA64_KR_PASTE(x,y) x##y
24#define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n)
25#define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n)
26
27/*
28 * Translation registers:
29 */
30#define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */
31#define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
32#define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
33
34#define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
35#define IA64_TR_ALLOC_MAX 32 /* Max number for dynamic use*/
36
37/* Processor status register bits: */
38#define IA64_PSR_BE_BIT 1
39#define IA64_PSR_UP_BIT 2
40#define IA64_PSR_AC_BIT 3
41#define IA64_PSR_MFL_BIT 4
42#define IA64_PSR_MFH_BIT 5
43#define IA64_PSR_IC_BIT 13
44#define IA64_PSR_I_BIT 14
45#define IA64_PSR_PK_BIT 15
46#define IA64_PSR_DT_BIT 17
47#define IA64_PSR_DFL_BIT 18
48#define IA64_PSR_DFH_BIT 19
49#define IA64_PSR_SP_BIT 20
50#define IA64_PSR_PP_BIT 21
51#define IA64_PSR_DI_BIT 22
52#define IA64_PSR_SI_BIT 23
53#define IA64_PSR_DB_BIT 24
54#define IA64_PSR_LP_BIT 25
55#define IA64_PSR_TB_BIT 26
56#define IA64_PSR_RT_BIT 27
57/* The following are not affected by save_flags()/restore_flags(): */
58#define IA64_PSR_CPL0_BIT 32
59#define IA64_PSR_CPL1_BIT 33
60#define IA64_PSR_IS_BIT 34
61#define IA64_PSR_MC_BIT 35
62#define IA64_PSR_IT_BIT 36
63#define IA64_PSR_ID_BIT 37
64#define IA64_PSR_DA_BIT 38
65#define IA64_PSR_DD_BIT 39
66#define IA64_PSR_SS_BIT 40
67#define IA64_PSR_RI_BIT 41
68#define IA64_PSR_ED_BIT 43
69#define IA64_PSR_BN_BIT 44
70#define IA64_PSR_IA_BIT 45
71
72/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
73 execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
74 execve(). */
75#define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
76 IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
77 IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA)
78#define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP)
79
80#define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
81#define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
82#define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
83#define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
84#define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
85#define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
86#define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
87#define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
88#define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
89#define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
90#define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
91#define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
92#define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
93#define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
94#define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
95#define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
96#define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
97#define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
98#define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
99/* The following are not affected by save_flags()/restore_flags(): */
100#define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT)
101#define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
102#define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
103#define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
104#define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
105#define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
106#define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
107#define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
108#define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
109#define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
110#define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
111#define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
112
113/* User mask bits: */
114#define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
115
116/* Default Control Register */
117#define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
118#define IA64_DCR_BE_BIT 1 /* big-endian default */
119#define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
120#define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
121#define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
122#define IA64_DCR_DK_BIT 10 /* defer key miss faults */
123#define IA64_DCR_DX_BIT 11 /* defer key permission faults */
124#define IA64_DCR_DR_BIT 12 /* defer access right faults */
125#define IA64_DCR_DA_BIT 13 /* defer access bit faults */
126#define IA64_DCR_DD_BIT 14 /* defer debug faults */
127
128#define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
129#define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
130#define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
131#define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
132#define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
133#define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
134#define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
135#define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
136#define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
137#define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
138
139/* Interrupt Status Register */
140#define IA64_ISR_X_BIT 32 /* execute access */
141#define IA64_ISR_W_BIT 33 /* write access */
142#define IA64_ISR_R_BIT 34 /* read access */
143#define IA64_ISR_NA_BIT 35 /* non-access */
144#define IA64_ISR_SP_BIT 36 /* speculative load exception */
145#define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
146#define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
147#define IA64_ISR_CODE_MASK 0xf
148
149#define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
150#define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
151#define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
152#define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
153#define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
154#define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
155#define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
156
157/* ISR code field for non-access instructions */
158#define IA64_ISR_CODE_TPA 0
159#define IA64_ISR_CODE_FC 1
160#define IA64_ISR_CODE_PROBE 2
161#define IA64_ISR_CODE_TAK 3
162#define IA64_ISR_CODE_LFETCH 4
163#define IA64_ISR_CODE_PROBEF 5
164
165#endif /* _ASM_IA64_kREGS_H */
diff --git a/arch/ia64/include/asm/kvm.h b/arch/ia64/include/asm/kvm.h
new file mode 100644
index 000000000000..f38472ac2267
--- /dev/null
+++ b/arch/ia64/include/asm/kvm.h
@@ -0,0 +1,211 @@
1#ifndef __ASM_IA64_KVM_H
2#define __ASM_IA64_KVM_H
3
4/*
5 * kvm structure definitions for ia64
6 *
7 * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
20 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 *
22 */
23
24#include <asm/types.h>
25
26#include <linux/ioctl.h>
27
28/* Architectural interrupt line count. */
29#define KVM_NR_INTERRUPTS 256
30
31#define KVM_IOAPIC_NUM_PINS 48
32
33struct kvm_ioapic_state {
34 __u64 base_address;
35 __u32 ioregsel;
36 __u32 id;
37 __u32 irr;
38 __u32 pad;
39 union {
40 __u64 bits;
41 struct {
42 __u8 vector;
43 __u8 delivery_mode:3;
44 __u8 dest_mode:1;
45 __u8 delivery_status:1;
46 __u8 polarity:1;
47 __u8 remote_irr:1;
48 __u8 trig_mode:1;
49 __u8 mask:1;
50 __u8 reserve:7;
51 __u8 reserved[4];
52 __u8 dest_id;
53 } fields;
54 } redirtbl[KVM_IOAPIC_NUM_PINS];
55};
56
57#define KVM_IRQCHIP_PIC_MASTER 0
58#define KVM_IRQCHIP_PIC_SLAVE 1
59#define KVM_IRQCHIP_IOAPIC 2
60
61#define KVM_CONTEXT_SIZE 8*1024
62
63struct kvm_fpreg {
64 union {
65 unsigned long bits[2];
66 long double __dummy; /* force 16-byte alignment */
67 } u;
68};
69
70union context {
71 /* 8K size */
72 char dummy[KVM_CONTEXT_SIZE];
73 struct {
74 unsigned long psr;
75 unsigned long pr;
76 unsigned long caller_unat;
77 unsigned long pad;
78 unsigned long gr[32];
79 unsigned long ar[128];
80 unsigned long br[8];
81 unsigned long cr[128];
82 unsigned long rr[8];
83 unsigned long ibr[8];
84 unsigned long dbr[8];
85 unsigned long pkr[8];
86 struct kvm_fpreg fr[128];
87 };
88};
89
90struct thash_data {
91 union {
92 struct {
93 unsigned long p : 1; /* 0 */
94 unsigned long rv1 : 1; /* 1 */
95 unsigned long ma : 3; /* 2-4 */
96 unsigned long a : 1; /* 5 */
97 unsigned long d : 1; /* 6 */
98 unsigned long pl : 2; /* 7-8 */
99 unsigned long ar : 3; /* 9-11 */
100 unsigned long ppn : 38; /* 12-49 */
101 unsigned long rv2 : 2; /* 50-51 */
102 unsigned long ed : 1; /* 52 */
103 unsigned long ig1 : 11; /* 53-63 */
104 };
105 struct {
106 unsigned long __rv1 : 53; /* 0-52 */
107 unsigned long contiguous : 1; /*53 */
108 unsigned long tc : 1; /* 54 TR or TC */
109 unsigned long cl : 1;
110 /* 55 I side or D side cache line */
111 unsigned long len : 4; /* 56-59 */
112 unsigned long io : 1; /* 60 entry is for io or not */
113 unsigned long nomap : 1;
114 /* 61 entry cann't be inserted into machine TLB.*/
115 unsigned long checked : 1;
116 /* 62 for VTLB/VHPT sanity check */
117 unsigned long invalid : 1;
118 /* 63 invalid entry */
119 };
120 unsigned long page_flags;
121 }; /* same for VHPT and TLB */
122
123 union {
124 struct {
125 unsigned long rv3 : 2;
126 unsigned long ps : 6;
127 unsigned long key : 24;
128 unsigned long rv4 : 32;
129 };
130 unsigned long itir;
131 };
132 union {
133 struct {
134 unsigned long ig2 : 12;
135 unsigned long vpn : 49;
136 unsigned long vrn : 3;
137 };
138 unsigned long ifa;
139 unsigned long vadr;
140 struct {
141 unsigned long tag : 63;
142 unsigned long ti : 1;
143 };
144 unsigned long etag;
145 };
146 union {
147 struct thash_data *next;
148 unsigned long rid;
149 unsigned long gpaddr;
150 };
151};
152
153#define NITRS 8
154#define NDTRS 8
155
156struct saved_vpd {
157 unsigned long vhpi;
158 unsigned long vgr[16];
159 unsigned long vbgr[16];
160 unsigned long vnat;
161 unsigned long vbnat;
162 unsigned long vcpuid[5];
163 unsigned long vpsr;
164 unsigned long vpr;
165 unsigned long vcr[128];
166};
167
168struct kvm_regs {
169 char *saved_guest;
170 char *saved_stack;
171 struct saved_vpd vpd;
172 /*Arch-regs*/
173 int mp_state;
174 unsigned long vmm_rr;
175 /* TR and TC. */
176 struct thash_data itrs[NITRS];
177 struct thash_data dtrs[NDTRS];
178 /* Bit is set if there is a tr/tc for the region. */
179 unsigned char itr_regions;
180 unsigned char dtr_regions;
181 unsigned char tc_regions;
182
183 char irq_check;
184 unsigned long saved_itc;
185 unsigned long itc_check;
186 unsigned long timer_check;
187 unsigned long timer_pending;
188 unsigned long last_itc;
189
190 unsigned long vrr[8];
191 unsigned long ibr[8];
192 unsigned long dbr[8];
193 unsigned long insvc[4]; /* Interrupt in service. */
194 unsigned long xtp;
195
196 unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
197 unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
198 unsigned long metaphysical_saved_rr0; /* from kvm_arch */
199 unsigned long metaphysical_saved_rr4; /* from kvm_arch */
200 unsigned long fp_psr; /*used for lazy float register */
201 unsigned long saved_gp;
202 /*for phycial emulation */
203};
204
205struct kvm_sregs {
206};
207
208struct kvm_fpu {
209};
210
211#endif
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
new file mode 100644
index 000000000000..1efe513a9941
--- /dev/null
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -0,0 +1,527 @@
1/*
2 * kvm_host.h: used for kvm module, and hold ia64-specific sections.
3 *
4 * Copyright (C) 2007, Intel Corporation.
5 *
6 * Xiantao Zhang <xiantao.zhang@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 *
21 */
22
23#ifndef __ASM_KVM_HOST_H
24#define __ASM_KVM_HOST_H
25
26
27#include <linux/types.h>
28#include <linux/mm.h>
29#include <linux/kvm.h>
30#include <linux/kvm_para.h>
31#include <linux/kvm_types.h>
32
33#include <asm/pal.h>
34#include <asm/sal.h>
35
36#define KVM_MAX_VCPUS 4
37#define KVM_MEMORY_SLOTS 32
38/* memory slots that does not exposed to userspace */
39#define KVM_PRIVATE_MEM_SLOTS 4
40
41#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
42
43/* define exit reasons from vmm to kvm*/
44#define EXIT_REASON_VM_PANIC 0
45#define EXIT_REASON_MMIO_INSTRUCTION 1
46#define EXIT_REASON_PAL_CALL 2
47#define EXIT_REASON_SAL_CALL 3
48#define EXIT_REASON_SWITCH_RR6 4
49#define EXIT_REASON_VM_DESTROY 5
50#define EXIT_REASON_EXTERNAL_INTERRUPT 6
51#define EXIT_REASON_IPI 7
52#define EXIT_REASON_PTC_G 8
53
54/*Define vmm address space and vm data space.*/
55#define KVM_VMM_SIZE (16UL<<20)
56#define KVM_VMM_SHIFT 24
57#define KVM_VMM_BASE 0xD000000000000000UL
58#define VMM_SIZE (8UL<<20)
59
60/*
61 * Define vm_buffer, used by PAL Services, base address.
62 * Note: vmbuffer is in the VMM-BLOCK, the size must be < 8M
63 */
64#define KVM_VM_BUFFER_BASE (KVM_VMM_BASE + VMM_SIZE)
65#define KVM_VM_BUFFER_SIZE (8UL<<20)
66
67/*Define Virtual machine data layout.*/
68#define KVM_VM_DATA_SHIFT 24
69#define KVM_VM_DATA_SIZE (1UL << KVM_VM_DATA_SHIFT)
70#define KVM_VM_DATA_BASE (KVM_VMM_BASE + KVM_VMM_SIZE)
71
72
73#define KVM_P2M_BASE KVM_VM_DATA_BASE
74#define KVM_P2M_OFS 0
75#define KVM_P2M_SIZE (8UL << 20)
76
77#define KVM_VHPT_BASE (KVM_P2M_BASE + KVM_P2M_SIZE)
78#define KVM_VHPT_OFS KVM_P2M_SIZE
79#define KVM_VHPT_BLOCK_SIZE (2UL << 20)
80#define VHPT_SHIFT 18
81#define VHPT_SIZE (1UL << VHPT_SHIFT)
82#define VHPT_NUM_ENTRIES (1<<(VHPT_SHIFT-5))
83
84#define KVM_VTLB_BASE (KVM_VHPT_BASE+KVM_VHPT_BLOCK_SIZE)
85#define KVM_VTLB_OFS (KVM_VHPT_OFS+KVM_VHPT_BLOCK_SIZE)
86#define KVM_VTLB_BLOCK_SIZE (1UL<<20)
87#define VTLB_SHIFT 17
88#define VTLB_SIZE (1UL<<VTLB_SHIFT)
89#define VTLB_NUM_ENTRIES (1<<(VTLB_SHIFT-5))
90
91#define KVM_VPD_BASE (KVM_VTLB_BASE+KVM_VTLB_BLOCK_SIZE)
92#define KVM_VPD_OFS (KVM_VTLB_OFS+KVM_VTLB_BLOCK_SIZE)
93#define KVM_VPD_BLOCK_SIZE (2UL<<20)
94#define VPD_SHIFT 16
95#define VPD_SIZE (1UL<<VPD_SHIFT)
96
97#define KVM_VCPU_BASE (KVM_VPD_BASE+KVM_VPD_BLOCK_SIZE)
98#define KVM_VCPU_OFS (KVM_VPD_OFS+KVM_VPD_BLOCK_SIZE)
99#define KVM_VCPU_BLOCK_SIZE (2UL<<20)
100#define VCPU_SHIFT 18
101#define VCPU_SIZE (1UL<<VCPU_SHIFT)
102#define MAX_VCPU_NUM KVM_VCPU_BLOCK_SIZE/VCPU_SIZE
103
104#define KVM_VM_BASE (KVM_VCPU_BASE+KVM_VCPU_BLOCK_SIZE)
105#define KVM_VM_OFS (KVM_VCPU_OFS+KVM_VCPU_BLOCK_SIZE)
106#define KVM_VM_BLOCK_SIZE (1UL<<19)
107
108#define KVM_MEM_DIRTY_LOG_BASE (KVM_VM_BASE+KVM_VM_BLOCK_SIZE)
109#define KVM_MEM_DIRTY_LOG_OFS (KVM_VM_OFS+KVM_VM_BLOCK_SIZE)
110#define KVM_MEM_DIRTY_LOG_SIZE (1UL<<19)
111
112/* Get vpd, vhpt, tlb, vcpu, base*/
113#define VPD_ADDR(n) (KVM_VPD_BASE+n*VPD_SIZE)
114#define VHPT_ADDR(n) (KVM_VHPT_BASE+n*VHPT_SIZE)
115#define VTLB_ADDR(n) (KVM_VTLB_BASE+n*VTLB_SIZE)
116#define VCPU_ADDR(n) (KVM_VCPU_BASE+n*VCPU_SIZE)
117
118/*IO section definitions*/
119#define IOREQ_READ 1
120#define IOREQ_WRITE 0
121
122#define STATE_IOREQ_NONE 0
123#define STATE_IOREQ_READY 1
124#define STATE_IOREQ_INPROCESS 2
125#define STATE_IORESP_READY 3
126
127/*Guest Physical address layout.*/
128#define GPFN_MEM (0UL << 60) /* Guest pfn is normal mem */
129#define GPFN_FRAME_BUFFER (1UL << 60) /* VGA framebuffer */
130#define GPFN_LOW_MMIO (2UL << 60) /* Low MMIO range */
131#define GPFN_PIB (3UL << 60) /* PIB base */
132#define GPFN_IOSAPIC (4UL << 60) /* IOSAPIC base */
133#define GPFN_LEGACY_IO (5UL << 60) /* Legacy I/O base */
134#define GPFN_GFW (6UL << 60) /* Guest Firmware */
135#define GPFN_HIGH_MMIO (7UL << 60) /* High MMIO range */
136
137#define GPFN_IO_MASK (7UL << 60) /* Guest pfn is I/O type */
138#define GPFN_INV_MASK (1UL << 63) /* Guest pfn is invalid */
139#define INVALID_MFN (~0UL)
140#define MEM_G (1UL << 30)
141#define MEM_M (1UL << 20)
142#define MMIO_START (3 * MEM_G)
143#define MMIO_SIZE (512 * MEM_M)
144#define VGA_IO_START 0xA0000UL
145#define VGA_IO_SIZE 0x20000
146#define LEGACY_IO_START (MMIO_START + MMIO_SIZE)
147#define LEGACY_IO_SIZE (64 * MEM_M)
148#define IO_SAPIC_START 0xfec00000UL
149#define IO_SAPIC_SIZE 0x100000
150#define PIB_START 0xfee00000UL
151#define PIB_SIZE 0x200000
152#define GFW_START (4 * MEM_G - 16 * MEM_M)
153#define GFW_SIZE (16 * MEM_M)
154
155/*Deliver mode, defined for ioapic.c*/
156#define dest_Fixed IOSAPIC_FIXED
157#define dest_LowestPrio IOSAPIC_LOWEST_PRIORITY
158
159#define NMI_VECTOR 2
160#define ExtINT_VECTOR 0
161#define NULL_VECTOR (-1)
162#define IA64_SPURIOUS_INT_VECTOR 0x0f
163
164#define VCPU_LID(v) (((u64)(v)->vcpu_id) << 24)
165
166/*
167 *Delivery mode
168 */
169#define SAPIC_DELIV_SHIFT 8
170#define SAPIC_FIXED 0x0
171#define SAPIC_LOWEST_PRIORITY 0x1
172#define SAPIC_PMI 0x2
173#define SAPIC_NMI 0x4
174#define SAPIC_INIT 0x5
175#define SAPIC_EXTINT 0x7
176
177/*
178 * vcpu->requests bit members for arch
179 */
180#define KVM_REQ_PTC_G 32
181#define KVM_REQ_RESUME 33
182
183#define KVM_PAGES_PER_HPAGE 1
184
185struct kvm;
186struct kvm_vcpu;
187struct kvm_guest_debug{
188};
189
190struct kvm_mmio_req {
191 uint64_t addr; /* physical address */
192 uint64_t size; /* size in bytes */
193 uint64_t data; /* data (or paddr of data) */
194 uint8_t state:4;
195 uint8_t dir:1; /* 1=read, 0=write */
196};
197
198/*Pal data struct */
199struct kvm_pal_call{
200 /*In area*/
201 uint64_t gr28;
202 uint64_t gr29;
203 uint64_t gr30;
204 uint64_t gr31;
205 /*Out area*/
206 struct ia64_pal_retval ret;
207};
208
209/* Sal data structure */
210struct kvm_sal_call{
211 /*In area*/
212 uint64_t in0;
213 uint64_t in1;
214 uint64_t in2;
215 uint64_t in3;
216 uint64_t in4;
217 uint64_t in5;
218 uint64_t in6;
219 uint64_t in7;
220 struct sal_ret_values ret;
221};
222
223/*Guest change rr6*/
224struct kvm_switch_rr6 {
225 uint64_t old_rr;
226 uint64_t new_rr;
227};
228
229union ia64_ipi_a{
230 unsigned long val;
231 struct {
232 unsigned long rv : 3;
233 unsigned long ir : 1;
234 unsigned long eid : 8;
235 unsigned long id : 8;
236 unsigned long ib_base : 44;
237 };
238};
239
240union ia64_ipi_d {
241 unsigned long val;
242 struct {
243 unsigned long vector : 8;
244 unsigned long dm : 3;
245 unsigned long ig : 53;
246 };
247};
248
249/*ipi check exit data*/
250struct kvm_ipi_data{
251 union ia64_ipi_a addr;
252 union ia64_ipi_d data;
253};
254
255/*global purge data*/
256struct kvm_ptc_g {
257 unsigned long vaddr;
258 unsigned long rr;
259 unsigned long ps;
260 struct kvm_vcpu *vcpu;
261};
262
263/*Exit control data */
264struct exit_ctl_data{
265 uint32_t exit_reason;
266 uint32_t vm_status;
267 union {
268 struct kvm_mmio_req ioreq;
269 struct kvm_pal_call pal_data;
270 struct kvm_sal_call sal_data;
271 struct kvm_switch_rr6 rr_data;
272 struct kvm_ipi_data ipi_data;
273 struct kvm_ptc_g ptc_g_data;
274 } u;
275};
276
277union pte_flags {
278 unsigned long val;
279 struct {
280 unsigned long p : 1; /*0 */
281 unsigned long : 1; /* 1 */
282 unsigned long ma : 3; /* 2-4 */
283 unsigned long a : 1; /* 5 */
284 unsigned long d : 1; /* 6 */
285 unsigned long pl : 2; /* 7-8 */
286 unsigned long ar : 3; /* 9-11 */
287 unsigned long ppn : 38; /* 12-49 */
288 unsigned long : 2; /* 50-51 */
289 unsigned long ed : 1; /* 52 */
290 };
291};
292
293union ia64_pta {
294 unsigned long val;
295 struct {
296 unsigned long ve : 1;
297 unsigned long reserved0 : 1;
298 unsigned long size : 6;
299 unsigned long vf : 1;
300 unsigned long reserved1 : 6;
301 unsigned long base : 49;
302 };
303};
304
305struct thash_cb {
306 /* THASH base information */
307 struct thash_data *hash; /* hash table pointer */
308 union ia64_pta pta;
309 int num;
310};
311
312struct kvm_vcpu_stat {
313};
314
315struct kvm_vcpu_arch {
316 int launched;
317 int last_exit;
318 int last_run_cpu;
319 int vmm_tr_slot;
320 int vm_tr_slot;
321
322#define KVM_MP_STATE_RUNNABLE 0
323#define KVM_MP_STATE_UNINITIALIZED 1
324#define KVM_MP_STATE_INIT_RECEIVED 2
325#define KVM_MP_STATE_HALTED 3
326 int mp_state;
327
328#define MAX_PTC_G_NUM 3
329 int ptc_g_count;
330 struct kvm_ptc_g ptc_g_data[MAX_PTC_G_NUM];
331
332 /*halt timer to wake up sleepy vcpus*/
333 struct hrtimer hlt_timer;
334 long ht_active;
335
336 struct kvm_lapic *apic; /* kernel irqchip context */
337 struct vpd *vpd;
338
339 /* Exit data for vmm_transition*/
340 struct exit_ctl_data exit_data;
341
342 cpumask_t cache_coherent_map;
343
344 unsigned long vmm_rr;
345 unsigned long host_rr6;
346 unsigned long psbits[8];
347 unsigned long cr_iipa;
348 unsigned long cr_isr;
349 unsigned long vsa_base;
350 unsigned long dirty_log_lock_pa;
351 unsigned long __gp;
352 /* TR and TC. */
353 struct thash_data itrs[NITRS];
354 struct thash_data dtrs[NDTRS];
355 /* Bit is set if there is a tr/tc for the region. */
356 unsigned char itr_regions;
357 unsigned char dtr_regions;
358 unsigned char tc_regions;
359 /* purge all */
360 unsigned long ptce_base;
361 unsigned long ptce_count[2];
362 unsigned long ptce_stride[2];
363 /* itc/itm */
364 unsigned long last_itc;
365 long itc_offset;
366 unsigned long itc_check;
367 unsigned long timer_check;
368 unsigned long timer_pending;
369
370 unsigned long vrr[8];
371 unsigned long ibr[8];
372 unsigned long dbr[8];
373 unsigned long insvc[4]; /* Interrupt in service. */
374 unsigned long xtp;
375
376 unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
377 unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
378 unsigned long metaphysical_saved_rr0; /* from kvm_arch */
379 unsigned long metaphysical_saved_rr4; /* from kvm_arch */
380 unsigned long fp_psr; /*used for lazy float register */
381 unsigned long saved_gp;
382 /*for phycial emulation */
383 int mode_flags;
384 struct thash_cb vtlb;
385 struct thash_cb vhpt;
386 char irq_check;
387 char irq_new_pending;
388
389 unsigned long opcode;
390 unsigned long cause;
391 union context host;
392 union context guest;
393};
394
395struct kvm_vm_stat {
396 u64 remote_tlb_flush;
397};
398
399struct kvm_sal_data {
400 unsigned long boot_ip;
401 unsigned long boot_gp;
402};
403
404struct kvm_arch {
405 unsigned long vm_base;
406 unsigned long metaphysical_rr0;
407 unsigned long metaphysical_rr4;
408 unsigned long vmm_init_rr;
409 unsigned long vhpt_base;
410 unsigned long vtlb_base;
411 unsigned long vpd_base;
412 spinlock_t dirty_log_lock;
413 struct kvm_ioapic *vioapic;
414 struct kvm_vm_stat stat;
415 struct kvm_sal_data rdv_sal_data;
416};
417
418union cpuid3_t {
419 u64 value;
420 struct {
421 u64 number : 8;
422 u64 revision : 8;
423 u64 model : 8;
424 u64 family : 8;
425 u64 archrev : 8;
426 u64 rv : 24;
427 };
428};
429
430struct kvm_pt_regs {
431 /* The following registers are saved by SAVE_MIN: */
432 unsigned long b6; /* scratch */
433 unsigned long b7; /* scratch */
434
435 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
436 unsigned long ar_ssd; /* reserved for future use (scratch) */
437
438 unsigned long r8; /* scratch (return value register 0) */
439 unsigned long r9; /* scratch (return value register 1) */
440 unsigned long r10; /* scratch (return value register 2) */
441 unsigned long r11; /* scratch (return value register 3) */
442
443 unsigned long cr_ipsr; /* interrupted task's psr */
444 unsigned long cr_iip; /* interrupted task's instruction pointer */
445 unsigned long cr_ifs; /* interrupted task's function state */
446
447 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
448 unsigned long ar_pfs; /* prev function state */
449 unsigned long ar_rsc; /* RSE configuration */
450 /* The following two are valid only if cr_ipsr.cpl > 0: */
451 unsigned long ar_rnat; /* RSE NaT */
452 unsigned long ar_bspstore; /* RSE bspstore */
453
454 unsigned long pr; /* 64 predicate registers (1 bit each) */
455 unsigned long b0; /* return pointer (bp) */
456 unsigned long loadrs; /* size of dirty partition << 16 */
457
458 unsigned long r1; /* the gp pointer */
459 unsigned long r12; /* interrupted task's memory stack pointer */
460 unsigned long r13; /* thread pointer */
461
462 unsigned long ar_fpsr; /* floating point status (preserved) */
463 unsigned long r15; /* scratch */
464
465 /* The remaining registers are NOT saved for system calls. */
466 unsigned long r14; /* scratch */
467 unsigned long r2; /* scratch */
468 unsigned long r3; /* scratch */
469 unsigned long r16; /* scratch */
470 unsigned long r17; /* scratch */
471 unsigned long r18; /* scratch */
472 unsigned long r19; /* scratch */
473 unsigned long r20; /* scratch */
474 unsigned long r21; /* scratch */
475 unsigned long r22; /* scratch */
476 unsigned long r23; /* scratch */
477 unsigned long r24; /* scratch */
478 unsigned long r25; /* scratch */
479 unsigned long r26; /* scratch */
480 unsigned long r27; /* scratch */
481 unsigned long r28; /* scratch */
482 unsigned long r29; /* scratch */
483 unsigned long r30; /* scratch */
484 unsigned long r31; /* scratch */
485 unsigned long ar_ccv; /* compare/exchange value (scratch) */
486
487 /*
488 * Floating point registers that the kernel considers scratch:
489 */
490 struct ia64_fpreg f6; /* scratch */
491 struct ia64_fpreg f7; /* scratch */
492 struct ia64_fpreg f8; /* scratch */
493 struct ia64_fpreg f9; /* scratch */
494 struct ia64_fpreg f10; /* scratch */
495 struct ia64_fpreg f11; /* scratch */
496
497 unsigned long r4; /* preserved */
498 unsigned long r5; /* preserved */
499 unsigned long r6; /* preserved */
500 unsigned long r7; /* preserved */
501 unsigned long eml_unat; /* used for emulating instruction */
502 unsigned long pad0; /* alignment pad */
503};
504
505static inline struct kvm_pt_regs *vcpu_regs(struct kvm_vcpu *v)
506{
507 return (struct kvm_pt_regs *) ((unsigned long) v + IA64_STK_OFFSET) - 1;
508}
509
510typedef int kvm_vmm_entry(void);
511typedef void kvm_tramp_entry(union context *host, union context *guest);
512
513struct kvm_vmm_info{
514 struct module *module;
515 kvm_vmm_entry *vmm_entry;
516 kvm_tramp_entry *tramp_entry;
517 unsigned long vmm_ivt;
518};
519
520int kvm_highest_pending_irq(struct kvm_vcpu *vcpu);
521int kvm_emulate_halt(struct kvm_vcpu *vcpu);
522int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run);
523void kvm_sal_emul(struct kvm_vcpu *vcpu);
524
525static inline void kvm_inject_nmi(struct kvm_vcpu *vcpu) {}
526
527#endif
diff --git a/arch/ia64/include/asm/kvm_para.h b/arch/ia64/include/asm/kvm_para.h
new file mode 100644
index 000000000000..0d6d8ca07b8c
--- /dev/null
+++ b/arch/ia64/include/asm/kvm_para.h
@@ -0,0 +1,27 @@
1#ifndef __IA64_KVM_PARA_H
2#define __IA64_KVM_PARA_H
3
4/*
5 * Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 *
20 */
21
22static inline unsigned int kvm_arch_para_features(void)
23{
24 return 0;
25}
26
27#endif
diff --git a/arch/ia64/include/asm/libata-portmap.h b/arch/ia64/include/asm/libata-portmap.h
new file mode 100644
index 000000000000..0e00c9a9f410
--- /dev/null
+++ b/arch/ia64/include/asm/libata-portmap.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_IA64_LIBATA_PORTMAP_H
2#define __ASM_IA64_LIBATA_PORTMAP_H
3
4#define ATA_PRIMARY_CMD 0x1F0
5#define ATA_PRIMARY_CTL 0x3F6
6#define ATA_PRIMARY_IRQ(dev) isa_irq_to_vector(14)
7
8#define ATA_SECONDARY_CMD 0x170
9#define ATA_SECONDARY_CTL 0x376
10#define ATA_SECONDARY_IRQ(dev) isa_irq_to_vector(15)
11
12#endif
diff --git a/arch/ia64/include/asm/linkage.h b/arch/ia64/include/asm/linkage.h
new file mode 100644
index 000000000000..ef22a45c1890
--- /dev/null
+++ b/arch/ia64/include/asm/linkage.h
@@ -0,0 +1,14 @@
1#ifndef __ASM_LINKAGE_H
2#define __ASM_LINKAGE_H
3
4#ifndef __ASSEMBLY__
5
6#define asmlinkage CPP_ASMLINKAGE __attribute__((syscall_linkage))
7
8#else
9
10#include <asm/asmmacro.h>
11
12#endif
13
14#endif
diff --git a/arch/ia64/include/asm/local.h b/arch/ia64/include/asm/local.h
new file mode 100644
index 000000000000..c11c530f74d0
--- /dev/null
+++ b/arch/ia64/include/asm/local.h
@@ -0,0 +1 @@
#include <asm-generic/local.h>
diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h
new file mode 100644
index 000000000000..2b850ccafef5
--- /dev/null
+++ b/arch/ia64/include/asm/machvec.h
@@ -0,0 +1,460 @@
1/*
2 * Machine vector for IA-64.
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) 1999-2001, 2003-2004 Hewlett-Packard Co.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10#ifndef _ASM_IA64_MACHVEC_H
11#define _ASM_IA64_MACHVEC_H
12
13#include <linux/types.h>
14
15/* forward declarations: */
16struct device;
17struct pt_regs;
18struct scatterlist;
19struct page;
20struct mm_struct;
21struct pci_bus;
22struct task_struct;
23struct pci_dev;
24struct msi_desc;
25struct dma_attrs;
26
27typedef void ia64_mv_setup_t (char **);
28typedef void ia64_mv_cpu_init_t (void);
29typedef void ia64_mv_irq_init_t (void);
30typedef void ia64_mv_send_ipi_t (int, int, int, int);
31typedef void ia64_mv_timer_interrupt_t (int, void *);
32typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
33typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
34typedef u8 ia64_mv_irq_to_vector (int);
35typedef unsigned int ia64_mv_local_vector_to_irq (u8);
36typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
37typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
38 u8 size);
39typedef int ia64_mv_pci_legacy_write_t (struct pci_bus *, u16 port, u32 val,
40 u8 size);
41typedef void ia64_mv_migrate_t(struct task_struct * task);
42typedef void ia64_mv_pci_fixup_bus_t (struct pci_bus *);
43typedef void ia64_mv_kernel_launch_event_t(void);
44
45/* DMA-mapping interface: */
46typedef void ia64_mv_dma_init (void);
47typedef void *ia64_mv_dma_alloc_coherent (struct device *, size_t, dma_addr_t *, gfp_t);
48typedef void ia64_mv_dma_free_coherent (struct device *, size_t, void *, dma_addr_t);
49typedef dma_addr_t ia64_mv_dma_map_single (struct device *, void *, size_t, int);
50typedef void ia64_mv_dma_unmap_single (struct device *, dma_addr_t, size_t, int);
51typedef int ia64_mv_dma_map_sg (struct device *, struct scatterlist *, int, int);
52typedef void ia64_mv_dma_unmap_sg (struct device *, struct scatterlist *, int, int);
53typedef void ia64_mv_dma_sync_single_for_cpu (struct device *, dma_addr_t, size_t, int);
54typedef void ia64_mv_dma_sync_sg_for_cpu (struct device *, struct scatterlist *, int, int);
55typedef void ia64_mv_dma_sync_single_for_device (struct device *, dma_addr_t, size_t, int);
56typedef void ia64_mv_dma_sync_sg_for_device (struct device *, struct scatterlist *, int, int);
57typedef int ia64_mv_dma_mapping_error(struct device *, dma_addr_t dma_addr);
58typedef int ia64_mv_dma_supported (struct device *, u64);
59
60typedef dma_addr_t ia64_mv_dma_map_single_attrs (struct device *, void *, size_t, int, struct dma_attrs *);
61typedef void ia64_mv_dma_unmap_single_attrs (struct device *, dma_addr_t, size_t, int, struct dma_attrs *);
62typedef int ia64_mv_dma_map_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
63typedef void ia64_mv_dma_unmap_sg_attrs (struct device *, struct scatterlist *, int, int, struct dma_attrs *);
64
65/*
66 * WARNING: The legacy I/O space is _architected_. Platforms are
67 * expected to follow this architected model (see Section 10.7 in the
68 * IA-64 Architecture Software Developer's Manual). Unfortunately,
69 * some broken machines do not follow that model, which is why we have
70 * to make the inX/outX operations part of the machine vector.
71 * Platform designers should follow the architected model whenever
72 * possible.
73 */
74typedef unsigned int ia64_mv_inb_t (unsigned long);
75typedef unsigned int ia64_mv_inw_t (unsigned long);
76typedef unsigned int ia64_mv_inl_t (unsigned long);
77typedef void ia64_mv_outb_t (unsigned char, unsigned long);
78typedef void ia64_mv_outw_t (unsigned short, unsigned long);
79typedef void ia64_mv_outl_t (unsigned int, unsigned long);
80typedef void ia64_mv_mmiowb_t (void);
81typedef unsigned char ia64_mv_readb_t (const volatile void __iomem *);
82typedef unsigned short ia64_mv_readw_t (const volatile void __iomem *);
83typedef unsigned int ia64_mv_readl_t (const volatile void __iomem *);
84typedef unsigned long ia64_mv_readq_t (const volatile void __iomem *);
85typedef unsigned char ia64_mv_readb_relaxed_t (const volatile void __iomem *);
86typedef unsigned short ia64_mv_readw_relaxed_t (const volatile void __iomem *);
87typedef unsigned int ia64_mv_readl_relaxed_t (const volatile void __iomem *);
88typedef unsigned long ia64_mv_readq_relaxed_t (const volatile void __iomem *);
89
90typedef int ia64_mv_setup_msi_irq_t (struct pci_dev *pdev, struct msi_desc *);
91typedef void ia64_mv_teardown_msi_irq_t (unsigned int irq);
92
93static inline void
94machvec_noop (void)
95{
96}
97
98static inline void
99machvec_noop_mm (struct mm_struct *mm)
100{
101}
102
103static inline void
104machvec_noop_task (struct task_struct *task)
105{
106}
107
108static inline void
109machvec_noop_bus (struct pci_bus *bus)
110{
111}
112
113extern void machvec_setup (char **);
114extern void machvec_timer_interrupt (int, void *);
115extern void machvec_dma_sync_single (struct device *, dma_addr_t, size_t, int);
116extern void machvec_dma_sync_sg (struct device *, struct scatterlist *, int, int);
117extern void machvec_tlb_migrate_finish (struct mm_struct *);
118
119# if defined (CONFIG_IA64_HP_SIM)
120# include <asm/machvec_hpsim.h>
121# elif defined (CONFIG_IA64_DIG)
122# include <asm/machvec_dig.h>
123# elif defined (CONFIG_IA64_HP_ZX1)
124# include <asm/machvec_hpzx1.h>
125# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
126# include <asm/machvec_hpzx1_swiotlb.h>
127# elif defined (CONFIG_IA64_SGI_SN2)
128# include <asm/machvec_sn2.h>
129# elif defined (CONFIG_IA64_SGI_UV)
130# include <asm/machvec_uv.h>
131# elif defined (CONFIG_IA64_GENERIC)
132
133# ifdef MACHVEC_PLATFORM_HEADER
134# include MACHVEC_PLATFORM_HEADER
135# else
136# define platform_name ia64_mv.name
137# define platform_setup ia64_mv.setup
138# define platform_cpu_init ia64_mv.cpu_init
139# define platform_irq_init ia64_mv.irq_init
140# define platform_send_ipi ia64_mv.send_ipi
141# define platform_timer_interrupt ia64_mv.timer_interrupt
142# define platform_global_tlb_purge ia64_mv.global_tlb_purge
143# define platform_tlb_migrate_finish ia64_mv.tlb_migrate_finish
144# define platform_dma_init ia64_mv.dma_init
145# define platform_dma_alloc_coherent ia64_mv.dma_alloc_coherent
146# define platform_dma_free_coherent ia64_mv.dma_free_coherent
147# define platform_dma_map_single_attrs ia64_mv.dma_map_single_attrs
148# define platform_dma_unmap_single_attrs ia64_mv.dma_unmap_single_attrs
149# define platform_dma_map_sg_attrs ia64_mv.dma_map_sg_attrs
150# define platform_dma_unmap_sg_attrs ia64_mv.dma_unmap_sg_attrs
151# define platform_dma_sync_single_for_cpu ia64_mv.dma_sync_single_for_cpu
152# define platform_dma_sync_sg_for_cpu ia64_mv.dma_sync_sg_for_cpu
153# define platform_dma_sync_single_for_device ia64_mv.dma_sync_single_for_device
154# define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device
155# define platform_dma_mapping_error ia64_mv.dma_mapping_error
156# define platform_dma_supported ia64_mv.dma_supported
157# define platform_irq_to_vector ia64_mv.irq_to_vector
158# define platform_local_vector_to_irq ia64_mv.local_vector_to_irq
159# define platform_pci_get_legacy_mem ia64_mv.pci_get_legacy_mem
160# define platform_pci_legacy_read ia64_mv.pci_legacy_read
161# define platform_pci_legacy_write ia64_mv.pci_legacy_write
162# define platform_inb ia64_mv.inb
163# define platform_inw ia64_mv.inw
164# define platform_inl ia64_mv.inl
165# define platform_outb ia64_mv.outb
166# define platform_outw ia64_mv.outw
167# define platform_outl ia64_mv.outl
168# define platform_mmiowb ia64_mv.mmiowb
169# define platform_readb ia64_mv.readb
170# define platform_readw ia64_mv.readw
171# define platform_readl ia64_mv.readl
172# define platform_readq ia64_mv.readq
173# define platform_readb_relaxed ia64_mv.readb_relaxed
174# define platform_readw_relaxed ia64_mv.readw_relaxed
175# define platform_readl_relaxed ia64_mv.readl_relaxed
176# define platform_readq_relaxed ia64_mv.readq_relaxed
177# define platform_migrate ia64_mv.migrate
178# define platform_setup_msi_irq ia64_mv.setup_msi_irq
179# define platform_teardown_msi_irq ia64_mv.teardown_msi_irq
180# define platform_pci_fixup_bus ia64_mv.pci_fixup_bus
181# define platform_kernel_launch_event ia64_mv.kernel_launch_event
182# endif
183
184/* __attribute__((__aligned__(16))) is required to make size of the
185 * structure multiple of 16 bytes.
186 * This will fillup the holes created because of section 3.3.1 in
187 * Software Conventions guide.
188 */
189struct ia64_machine_vector {
190 const char *name;
191 ia64_mv_setup_t *setup;
192 ia64_mv_cpu_init_t *cpu_init;
193 ia64_mv_irq_init_t *irq_init;
194 ia64_mv_send_ipi_t *send_ipi;
195 ia64_mv_timer_interrupt_t *timer_interrupt;
196 ia64_mv_global_tlb_purge_t *global_tlb_purge;
197 ia64_mv_tlb_migrate_finish_t *tlb_migrate_finish;
198 ia64_mv_dma_init *dma_init;
199 ia64_mv_dma_alloc_coherent *dma_alloc_coherent;
200 ia64_mv_dma_free_coherent *dma_free_coherent;
201 ia64_mv_dma_map_single_attrs *dma_map_single_attrs;
202 ia64_mv_dma_unmap_single_attrs *dma_unmap_single_attrs;
203 ia64_mv_dma_map_sg_attrs *dma_map_sg_attrs;
204 ia64_mv_dma_unmap_sg_attrs *dma_unmap_sg_attrs;
205 ia64_mv_dma_sync_single_for_cpu *dma_sync_single_for_cpu;
206 ia64_mv_dma_sync_sg_for_cpu *dma_sync_sg_for_cpu;
207 ia64_mv_dma_sync_single_for_device *dma_sync_single_for_device;
208 ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device;
209 ia64_mv_dma_mapping_error *dma_mapping_error;
210 ia64_mv_dma_supported *dma_supported;
211 ia64_mv_irq_to_vector *irq_to_vector;
212 ia64_mv_local_vector_to_irq *local_vector_to_irq;
213 ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem;
214 ia64_mv_pci_legacy_read_t *pci_legacy_read;
215 ia64_mv_pci_legacy_write_t *pci_legacy_write;
216 ia64_mv_inb_t *inb;
217 ia64_mv_inw_t *inw;
218 ia64_mv_inl_t *inl;
219 ia64_mv_outb_t *outb;
220 ia64_mv_outw_t *outw;
221 ia64_mv_outl_t *outl;
222 ia64_mv_mmiowb_t *mmiowb;
223 ia64_mv_readb_t *readb;
224 ia64_mv_readw_t *readw;
225 ia64_mv_readl_t *readl;
226 ia64_mv_readq_t *readq;
227 ia64_mv_readb_relaxed_t *readb_relaxed;
228 ia64_mv_readw_relaxed_t *readw_relaxed;
229 ia64_mv_readl_relaxed_t *readl_relaxed;
230 ia64_mv_readq_relaxed_t *readq_relaxed;
231 ia64_mv_migrate_t *migrate;
232 ia64_mv_setup_msi_irq_t *setup_msi_irq;
233 ia64_mv_teardown_msi_irq_t *teardown_msi_irq;
234 ia64_mv_pci_fixup_bus_t *pci_fixup_bus;
235 ia64_mv_kernel_launch_event_t *kernel_launch_event;
236} __attribute__((__aligned__(16))); /* align attrib? see above comment */
237
238#define MACHVEC_INIT(name) \
239{ \
240 #name, \
241 platform_setup, \
242 platform_cpu_init, \
243 platform_irq_init, \
244 platform_send_ipi, \
245 platform_timer_interrupt, \
246 platform_global_tlb_purge, \
247 platform_tlb_migrate_finish, \
248 platform_dma_init, \
249 platform_dma_alloc_coherent, \
250 platform_dma_free_coherent, \
251 platform_dma_map_single_attrs, \
252 platform_dma_unmap_single_attrs, \
253 platform_dma_map_sg_attrs, \
254 platform_dma_unmap_sg_attrs, \
255 platform_dma_sync_single_for_cpu, \
256 platform_dma_sync_sg_for_cpu, \
257 platform_dma_sync_single_for_device, \
258 platform_dma_sync_sg_for_device, \
259 platform_dma_mapping_error, \
260 platform_dma_supported, \
261 platform_irq_to_vector, \
262 platform_local_vector_to_irq, \
263 platform_pci_get_legacy_mem, \
264 platform_pci_legacy_read, \
265 platform_pci_legacy_write, \
266 platform_inb, \
267 platform_inw, \
268 platform_inl, \
269 platform_outb, \
270 platform_outw, \
271 platform_outl, \
272 platform_mmiowb, \
273 platform_readb, \
274 platform_readw, \
275 platform_readl, \
276 platform_readq, \
277 platform_readb_relaxed, \
278 platform_readw_relaxed, \
279 platform_readl_relaxed, \
280 platform_readq_relaxed, \
281 platform_migrate, \
282 platform_setup_msi_irq, \
283 platform_teardown_msi_irq, \
284 platform_pci_fixup_bus, \
285 platform_kernel_launch_event \
286}
287
288extern struct ia64_machine_vector ia64_mv;
289extern void machvec_init (const char *name);
290extern void machvec_init_from_cmdline(const char *cmdline);
291
292# else
293# error Unknown configuration. Update arch/ia64/include/asm/machvec.h.
294# endif /* CONFIG_IA64_GENERIC */
295
296/*
297 * Declare default routines which aren't declared anywhere else:
298 */
299extern ia64_mv_dma_init swiotlb_init;
300extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent;
301extern ia64_mv_dma_free_coherent swiotlb_free_coherent;
302extern ia64_mv_dma_map_single swiotlb_map_single;
303extern ia64_mv_dma_map_single_attrs swiotlb_map_single_attrs;
304extern ia64_mv_dma_unmap_single swiotlb_unmap_single;
305extern ia64_mv_dma_unmap_single_attrs swiotlb_unmap_single_attrs;
306extern ia64_mv_dma_map_sg swiotlb_map_sg;
307extern ia64_mv_dma_map_sg_attrs swiotlb_map_sg_attrs;
308extern ia64_mv_dma_unmap_sg swiotlb_unmap_sg;
309extern ia64_mv_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs;
310extern ia64_mv_dma_sync_single_for_cpu swiotlb_sync_single_for_cpu;
311extern ia64_mv_dma_sync_sg_for_cpu swiotlb_sync_sg_for_cpu;
312extern ia64_mv_dma_sync_single_for_device swiotlb_sync_single_for_device;
313extern ia64_mv_dma_sync_sg_for_device swiotlb_sync_sg_for_device;
314extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error;
315extern ia64_mv_dma_supported swiotlb_dma_supported;
316
317/*
318 * Define default versions so we can extend machvec for new platforms without having
319 * to update the machvec files for all existing platforms.
320 */
321#ifndef platform_setup
322# define platform_setup machvec_setup
323#endif
324#ifndef platform_cpu_init
325# define platform_cpu_init machvec_noop
326#endif
327#ifndef platform_irq_init
328# define platform_irq_init machvec_noop
329#endif
330
331#ifndef platform_send_ipi
332# define platform_send_ipi ia64_send_ipi /* default to architected version */
333#endif
334#ifndef platform_timer_interrupt
335# define platform_timer_interrupt machvec_timer_interrupt
336#endif
337#ifndef platform_global_tlb_purge
338# define platform_global_tlb_purge ia64_global_tlb_purge /* default to architected version */
339#endif
340#ifndef platform_tlb_migrate_finish
341# define platform_tlb_migrate_finish machvec_noop_mm
342#endif
343#ifndef platform_kernel_launch_event
344# define platform_kernel_launch_event machvec_noop
345#endif
346#ifndef platform_dma_init
347# define platform_dma_init swiotlb_init
348#endif
349#ifndef platform_dma_alloc_coherent
350# define platform_dma_alloc_coherent swiotlb_alloc_coherent
351#endif
352#ifndef platform_dma_free_coherent
353# define platform_dma_free_coherent swiotlb_free_coherent
354#endif
355#ifndef platform_dma_map_single_attrs
356# define platform_dma_map_single_attrs swiotlb_map_single_attrs
357#endif
358#ifndef platform_dma_unmap_single_attrs
359# define platform_dma_unmap_single_attrs swiotlb_unmap_single_attrs
360#endif
361#ifndef platform_dma_map_sg_attrs
362# define platform_dma_map_sg_attrs swiotlb_map_sg_attrs
363#endif
364#ifndef platform_dma_unmap_sg_attrs
365# define platform_dma_unmap_sg_attrs swiotlb_unmap_sg_attrs
366#endif
367#ifndef platform_dma_sync_single_for_cpu
368# define platform_dma_sync_single_for_cpu swiotlb_sync_single_for_cpu
369#endif
370#ifndef platform_dma_sync_sg_for_cpu
371# define platform_dma_sync_sg_for_cpu swiotlb_sync_sg_for_cpu
372#endif
373#ifndef platform_dma_sync_single_for_device
374# define platform_dma_sync_single_for_device swiotlb_sync_single_for_device
375#endif
376#ifndef platform_dma_sync_sg_for_device
377# define platform_dma_sync_sg_for_device swiotlb_sync_sg_for_device
378#endif
379#ifndef platform_dma_mapping_error
380# define platform_dma_mapping_error swiotlb_dma_mapping_error
381#endif
382#ifndef platform_dma_supported
383# define platform_dma_supported swiotlb_dma_supported
384#endif
385#ifndef platform_irq_to_vector
386# define platform_irq_to_vector __ia64_irq_to_vector
387#endif
388#ifndef platform_local_vector_to_irq
389# define platform_local_vector_to_irq __ia64_local_vector_to_irq
390#endif
391#ifndef platform_pci_get_legacy_mem
392# define platform_pci_get_legacy_mem ia64_pci_get_legacy_mem
393#endif
394#ifndef platform_pci_legacy_read
395# define platform_pci_legacy_read ia64_pci_legacy_read
396extern int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
397#endif
398#ifndef platform_pci_legacy_write
399# define platform_pci_legacy_write ia64_pci_legacy_write
400extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
401#endif
402#ifndef platform_inb
403# define platform_inb __ia64_inb
404#endif
405#ifndef platform_inw
406# define platform_inw __ia64_inw
407#endif
408#ifndef platform_inl
409# define platform_inl __ia64_inl
410#endif
411#ifndef platform_outb
412# define platform_outb __ia64_outb
413#endif
414#ifndef platform_outw
415# define platform_outw __ia64_outw
416#endif
417#ifndef platform_outl
418# define platform_outl __ia64_outl
419#endif
420#ifndef platform_mmiowb
421# define platform_mmiowb __ia64_mmiowb
422#endif
423#ifndef platform_readb
424# define platform_readb __ia64_readb
425#endif
426#ifndef platform_readw
427# define platform_readw __ia64_readw
428#endif
429#ifndef platform_readl
430# define platform_readl __ia64_readl
431#endif
432#ifndef platform_readq
433# define platform_readq __ia64_readq
434#endif
435#ifndef platform_readb_relaxed
436# define platform_readb_relaxed __ia64_readb_relaxed
437#endif
438#ifndef platform_readw_relaxed
439# define platform_readw_relaxed __ia64_readw_relaxed
440#endif
441#ifndef platform_readl_relaxed
442# define platform_readl_relaxed __ia64_readl_relaxed
443#endif
444#ifndef platform_readq_relaxed
445# define platform_readq_relaxed __ia64_readq_relaxed
446#endif
447#ifndef platform_migrate
448# define platform_migrate machvec_noop_task
449#endif
450#ifndef platform_setup_msi_irq
451# define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
452#endif
453#ifndef platform_teardown_msi_irq
454# define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
455#endif
456#ifndef platform_pci_fixup_bus
457# define platform_pci_fixup_bus machvec_noop_bus
458#endif
459
460#endif /* _ASM_IA64_MACHVEC_H */
diff --git a/arch/ia64/include/asm/machvec_dig.h b/arch/ia64/include/asm/machvec_dig.h
new file mode 100644
index 000000000000..8a0752f40987
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_dig.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_IA64_MACHVEC_DIG_h
2#define _ASM_IA64_MACHVEC_DIG_h
3
4extern ia64_mv_setup_t dig_setup;
5
6/*
7 * This stuff has dual use!
8 *
9 * For a generic kernel, the macros are used to initialize the
10 * platform's machvec structure. When compiling a non-generic kernel,
11 * the macros are used directly.
12 */
13#define platform_name "dig"
14#define platform_setup dig_setup
15
16#endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/arch/ia64/include/asm/machvec_hpsim.h b/arch/ia64/include/asm/machvec_hpsim.h
new file mode 100644
index 000000000000..cf72fc87fdfe
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpsim.h
@@ -0,0 +1,18 @@
1#ifndef _ASM_IA64_MACHVEC_HPSIM_h
2#define _ASM_IA64_MACHVEC_HPSIM_h
3
4extern ia64_mv_setup_t hpsim_setup;
5extern ia64_mv_irq_init_t hpsim_irq_init;
6
7/*
8 * This stuff has dual use!
9 *
10 * For a generic kernel, the macros are used to initialize the
11 * platform's machvec structure. When compiling a non-generic kernel,
12 * the macros are used directly.
13 */
14#define platform_name "hpsim"
15#define platform_setup hpsim_setup
16#define platform_irq_init hpsim_irq_init
17
18#endif /* _ASM_IA64_MACHVEC_HPSIM_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1.h b/arch/ia64/include/asm/machvec_hpzx1.h
new file mode 100644
index 000000000000..2f57f5144b9f
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpzx1.h
@@ -0,0 +1,37 @@
1#ifndef _ASM_IA64_MACHVEC_HPZX1_h
2#define _ASM_IA64_MACHVEC_HPZX1_h
3
4extern ia64_mv_setup_t dig_setup;
5extern ia64_mv_dma_alloc_coherent sba_alloc_coherent;
6extern ia64_mv_dma_free_coherent sba_free_coherent;
7extern ia64_mv_dma_map_single_attrs sba_map_single_attrs;
8extern ia64_mv_dma_unmap_single_attrs sba_unmap_single_attrs;
9extern ia64_mv_dma_map_sg_attrs sba_map_sg_attrs;
10extern ia64_mv_dma_unmap_sg_attrs sba_unmap_sg_attrs;
11extern ia64_mv_dma_supported sba_dma_supported;
12extern ia64_mv_dma_mapping_error sba_dma_mapping_error;
13
14/*
15 * This stuff has dual use!
16 *
17 * For a generic kernel, the macros are used to initialize the
18 * platform's machvec structure. When compiling a non-generic kernel,
19 * the macros are used directly.
20 */
21#define platform_name "hpzx1"
22#define platform_setup dig_setup
23#define platform_dma_init machvec_noop
24#define platform_dma_alloc_coherent sba_alloc_coherent
25#define platform_dma_free_coherent sba_free_coherent
26#define platform_dma_map_single_attrs sba_map_single_attrs
27#define platform_dma_unmap_single_attrs sba_unmap_single_attrs
28#define platform_dma_map_sg_attrs sba_map_sg_attrs
29#define platform_dma_unmap_sg_attrs sba_unmap_sg_attrs
30#define platform_dma_sync_single_for_cpu machvec_dma_sync_single
31#define platform_dma_sync_sg_for_cpu machvec_dma_sync_sg
32#define platform_dma_sync_single_for_device machvec_dma_sync_single
33#define platform_dma_sync_sg_for_device machvec_dma_sync_sg
34#define platform_dma_supported sba_dma_supported
35#define platform_dma_mapping_error sba_dma_mapping_error
36
37#endif /* _ASM_IA64_MACHVEC_HPZX1_h */
diff --git a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
new file mode 100644
index 000000000000..a842cdda827b
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
2#define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
3
4extern ia64_mv_setup_t dig_setup;
5extern ia64_mv_dma_alloc_coherent hwsw_alloc_coherent;
6extern ia64_mv_dma_free_coherent hwsw_free_coherent;
7extern ia64_mv_dma_map_single_attrs hwsw_map_single_attrs;
8extern ia64_mv_dma_unmap_single_attrs hwsw_unmap_single_attrs;
9extern ia64_mv_dma_map_sg_attrs hwsw_map_sg_attrs;
10extern ia64_mv_dma_unmap_sg_attrs hwsw_unmap_sg_attrs;
11extern ia64_mv_dma_supported hwsw_dma_supported;
12extern ia64_mv_dma_mapping_error hwsw_dma_mapping_error;
13extern ia64_mv_dma_sync_single_for_cpu hwsw_sync_single_for_cpu;
14extern ia64_mv_dma_sync_sg_for_cpu hwsw_sync_sg_for_cpu;
15extern ia64_mv_dma_sync_single_for_device hwsw_sync_single_for_device;
16extern ia64_mv_dma_sync_sg_for_device hwsw_sync_sg_for_device;
17
18/*
19 * This stuff has dual use!
20 *
21 * For a generic kernel, the macros are used to initialize the
22 * platform's machvec structure. When compiling a non-generic kernel,
23 * the macros are used directly.
24 */
25#define platform_name "hpzx1_swiotlb"
26
27#define platform_setup dig_setup
28#define platform_dma_init machvec_noop
29#define platform_dma_alloc_coherent hwsw_alloc_coherent
30#define platform_dma_free_coherent hwsw_free_coherent
31#define platform_dma_map_single_attrs hwsw_map_single_attrs
32#define platform_dma_unmap_single_attrs hwsw_unmap_single_attrs
33#define platform_dma_map_sg_attrs hwsw_map_sg_attrs
34#define platform_dma_unmap_sg_attrs hwsw_unmap_sg_attrs
35#define platform_dma_supported hwsw_dma_supported
36#define platform_dma_mapping_error hwsw_dma_mapping_error
37#define platform_dma_sync_single_for_cpu hwsw_sync_single_for_cpu
38#define platform_dma_sync_sg_for_cpu hwsw_sync_sg_for_cpu
39#define platform_dma_sync_single_for_device hwsw_sync_single_for_device
40#define platform_dma_sync_sg_for_device hwsw_sync_sg_for_device
41
42#endif /* _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h */
diff --git a/arch/ia64/include/asm/machvec_init.h b/arch/ia64/include/asm/machvec_init.h
new file mode 100644
index 000000000000..7f21249fba3f
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_init.h
@@ -0,0 +1,33 @@
1#include <asm/machvec.h>
2
3extern ia64_mv_send_ipi_t ia64_send_ipi;
4extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
5extern ia64_mv_irq_to_vector __ia64_irq_to_vector;
6extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
7extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
8extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
9extern ia64_mv_pci_legacy_write_t ia64_pci_legacy_write;
10
11extern ia64_mv_inb_t __ia64_inb;
12extern ia64_mv_inw_t __ia64_inw;
13extern ia64_mv_inl_t __ia64_inl;
14extern ia64_mv_outb_t __ia64_outb;
15extern ia64_mv_outw_t __ia64_outw;
16extern ia64_mv_outl_t __ia64_outl;
17extern ia64_mv_mmiowb_t __ia64_mmiowb;
18extern ia64_mv_readb_t __ia64_readb;
19extern ia64_mv_readw_t __ia64_readw;
20extern ia64_mv_readl_t __ia64_readl;
21extern ia64_mv_readq_t __ia64_readq;
22extern ia64_mv_readb_t __ia64_readb_relaxed;
23extern ia64_mv_readw_t __ia64_readw_relaxed;
24extern ia64_mv_readl_t __ia64_readl_relaxed;
25extern ia64_mv_readq_t __ia64_readq_relaxed;
26
27#define MACHVEC_HELPER(name) \
28 struct ia64_machine_vector machvec_##name __attribute__ ((unused, __section__ (".machvec"))) \
29 = MACHVEC_INIT(name);
30
31#define MACHVEC_DEFINE(name) MACHVEC_HELPER(name)
32
33MACHVEC_DEFINE(MACHVEC_PLATFORM_NAME)
diff --git a/arch/ia64/include/asm/machvec_sn2.h b/arch/ia64/include/asm/machvec_sn2.h
new file mode 100644
index 000000000000..781308ea7b88
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_sn2.h
@@ -0,0 +1,139 @@
1/*
2 * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * Further, this software is distributed without any warranty that it is
13 * free of the rightful claim of any third person regarding infringement
14 * or the like. Any license provided herein, whether implied or
15 * otherwise, applies only to this software file. Patent licenses, if
16 * any, provided herein do not apply to combinations of this program with
17 * other software, or any other product whatsoever.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this program; if not, write the Free Software
21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * For further information regarding this notice, see:
24 *
25 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
26 */
27
28#ifndef _ASM_IA64_MACHVEC_SN2_H
29#define _ASM_IA64_MACHVEC_SN2_H
30
31extern ia64_mv_setup_t sn_setup;
32extern ia64_mv_cpu_init_t sn_cpu_init;
33extern ia64_mv_irq_init_t sn_irq_init;
34extern ia64_mv_send_ipi_t sn2_send_IPI;
35extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
36extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
37extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish;
38extern ia64_mv_irq_to_vector sn_irq_to_vector;
39extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
40extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
41extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
42extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
43extern ia64_mv_inb_t __sn_inb;
44extern ia64_mv_inw_t __sn_inw;
45extern ia64_mv_inl_t __sn_inl;
46extern ia64_mv_outb_t __sn_outb;
47extern ia64_mv_outw_t __sn_outw;
48extern ia64_mv_outl_t __sn_outl;
49extern ia64_mv_mmiowb_t __sn_mmiowb;
50extern ia64_mv_readb_t __sn_readb;
51extern ia64_mv_readw_t __sn_readw;
52extern ia64_mv_readl_t __sn_readl;
53extern ia64_mv_readq_t __sn_readq;
54extern ia64_mv_readb_t __sn_readb_relaxed;
55extern ia64_mv_readw_t __sn_readw_relaxed;
56extern ia64_mv_readl_t __sn_readl_relaxed;
57extern ia64_mv_readq_t __sn_readq_relaxed;
58extern ia64_mv_dma_alloc_coherent sn_dma_alloc_coherent;
59extern ia64_mv_dma_free_coherent sn_dma_free_coherent;
60extern ia64_mv_dma_map_single_attrs sn_dma_map_single_attrs;
61extern ia64_mv_dma_unmap_single_attrs sn_dma_unmap_single_attrs;
62extern ia64_mv_dma_map_sg_attrs sn_dma_map_sg_attrs;
63extern ia64_mv_dma_unmap_sg_attrs sn_dma_unmap_sg_attrs;
64extern ia64_mv_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu;
65extern ia64_mv_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu;
66extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
67extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
68extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
69extern ia64_mv_dma_supported sn_dma_supported;
70extern ia64_mv_migrate_t sn_migrate;
71extern ia64_mv_kernel_launch_event_t sn_kernel_launch_event;
72extern ia64_mv_setup_msi_irq_t sn_setup_msi_irq;
73extern ia64_mv_teardown_msi_irq_t sn_teardown_msi_irq;
74extern ia64_mv_pci_fixup_bus_t sn_pci_fixup_bus;
75
76
77/*
78 * This stuff has dual use!
79 *
80 * For a generic kernel, the macros are used to initialize the
81 * platform's machvec structure. When compiling a non-generic kernel,
82 * the macros are used directly.
83 */
84#define platform_name "sn2"
85#define platform_setup sn_setup
86#define platform_cpu_init sn_cpu_init
87#define platform_irq_init sn_irq_init
88#define platform_send_ipi sn2_send_IPI
89#define platform_timer_interrupt sn_timer_interrupt
90#define platform_global_tlb_purge sn2_global_tlb_purge
91#define platform_tlb_migrate_finish sn_tlb_migrate_finish
92#define platform_pci_fixup sn_pci_fixup
93#define platform_inb __sn_inb
94#define platform_inw __sn_inw
95#define platform_inl __sn_inl
96#define platform_outb __sn_outb
97#define platform_outw __sn_outw
98#define platform_outl __sn_outl
99#define platform_mmiowb __sn_mmiowb
100#define platform_readb __sn_readb
101#define platform_readw __sn_readw
102#define platform_readl __sn_readl
103#define platform_readq __sn_readq
104#define platform_readb_relaxed __sn_readb_relaxed
105#define platform_readw_relaxed __sn_readw_relaxed
106#define platform_readl_relaxed __sn_readl_relaxed
107#define platform_readq_relaxed __sn_readq_relaxed
108#define platform_irq_to_vector sn_irq_to_vector
109#define platform_local_vector_to_irq sn_local_vector_to_irq
110#define platform_pci_get_legacy_mem sn_pci_get_legacy_mem
111#define platform_pci_legacy_read sn_pci_legacy_read
112#define platform_pci_legacy_write sn_pci_legacy_write
113#define platform_dma_init machvec_noop
114#define platform_dma_alloc_coherent sn_dma_alloc_coherent
115#define platform_dma_free_coherent sn_dma_free_coherent
116#define platform_dma_map_single_attrs sn_dma_map_single_attrs
117#define platform_dma_unmap_single_attrs sn_dma_unmap_single_attrs
118#define platform_dma_map_sg_attrs sn_dma_map_sg_attrs
119#define platform_dma_unmap_sg_attrs sn_dma_unmap_sg_attrs
120#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
121#define platform_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu
122#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
123#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
124#define platform_dma_mapping_error sn_dma_mapping_error
125#define platform_dma_supported sn_dma_supported
126#define platform_migrate sn_migrate
127#define platform_kernel_launch_event sn_kernel_launch_event
128#ifdef CONFIG_PCI_MSI
129#define platform_setup_msi_irq sn_setup_msi_irq
130#define platform_teardown_msi_irq sn_teardown_msi_irq
131#else
132#define platform_setup_msi_irq ((ia64_mv_setup_msi_irq_t*)NULL)
133#define platform_teardown_msi_irq ((ia64_mv_teardown_msi_irq_t*)NULL)
134#endif
135#define platform_pci_fixup_bus sn_pci_fixup_bus
136
137#include <asm/sn/io.h>
138
139#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff --git a/arch/ia64/include/asm/machvec_uv.h b/arch/ia64/include/asm/machvec_uv.h
new file mode 100644
index 000000000000..2931447f3813
--- /dev/null
+++ b/arch/ia64/include/asm/machvec_uv.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Core Functions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef _ASM_IA64_MACHVEC_UV_H
12#define _ASM_IA64_MACHVEC_UV_H
13
14extern ia64_mv_setup_t uv_setup;
15
16/*
17 * This stuff has dual use!
18 *
19 * For a generic kernel, the macros are used to initialize the
20 * platform's machvec structure. When compiling a non-generic kernel,
21 * the macros are used directly.
22 */
23#define platform_name "uv"
24#define platform_setup uv_setup
25
26#endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/arch/ia64/include/asm/mc146818rtc.h b/arch/ia64/include/asm/mc146818rtc.h
new file mode 100644
index 000000000000..407787a237ba
--- /dev/null
+++ b/arch/ia64/include/asm/mc146818rtc.h
@@ -0,0 +1,10 @@
1#ifndef _ASM_IA64_MC146818RTC_H
2#define _ASM_IA64_MC146818RTC_H
3
4/*
5 * Machine dependent access functions for RTC registers.
6 */
7
8/* empty include file to satisfy the include in genrtc.c */
9
10#endif /* _ASM_IA64_MC146818RTC_H */
diff --git a/arch/ia64/include/asm/mca.h b/arch/ia64/include/asm/mca.h
new file mode 100644
index 000000000000..18a4321349a3
--- /dev/null
+++ b/arch/ia64/include/asm/mca.h
@@ -0,0 +1,179 @@
1/*
2 * File: mca.h
3 * Purpose: Machine check handling specific defines
4 *
5 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
8 * Copyright (C) Russ Anderson <rja@sgi.com>
9 */
10
11#ifndef _ASM_IA64_MCA_H
12#define _ASM_IA64_MCA_H
13
14#if !defined(__ASSEMBLY__)
15
16#include <linux/interrupt.h>
17#include <linux/types.h>
18
19#include <asm/param.h>
20#include <asm/sal.h>
21#include <asm/processor.h>
22#include <asm/mca_asm.h>
23
24#define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */
25
26typedef struct ia64_fptr {
27 unsigned long fp;
28 unsigned long gp;
29} ia64_fptr_t;
30
31typedef union cmcv_reg_u {
32 u64 cmcv_regval;
33 struct {
34 u64 cmcr_vector : 8;
35 u64 cmcr_reserved1 : 4;
36 u64 cmcr_ignored1 : 1;
37 u64 cmcr_reserved2 : 3;
38 u64 cmcr_mask : 1;
39 u64 cmcr_ignored2 : 47;
40 } cmcv_reg_s;
41
42} cmcv_reg_t;
43
44#define cmcv_mask cmcv_reg_s.cmcr_mask
45#define cmcv_vector cmcv_reg_s.cmcr_vector
46
47enum {
48 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0,
49 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1,
50 IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2,
51 IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA = 0x3,
52};
53
54/* Information maintained by the MC infrastructure */
55typedef struct ia64_mc_info_s {
56 u64 imi_mca_handler;
57 size_t imi_mca_handler_size;
58 u64 imi_monarch_init_handler;
59 size_t imi_monarch_init_handler_size;
60 u64 imi_slave_init_handler;
61 size_t imi_slave_init_handler_size;
62 u8 imi_rendez_checkin[NR_CPUS];
63
64} ia64_mc_info_t;
65
66/* Handover state from SAL to OS and vice versa, for both MCA and INIT events.
67 * Besides the handover state, it also contains some saved registers from the
68 * time of the event.
69 * Note: mca_asm.S depends on the precise layout of this structure.
70 */
71
72struct ia64_sal_os_state {
73
74 /* SAL to OS */
75 u64 os_gp; /* GP of the os registered with the SAL, physical */
76 u64 pal_proc; /* PAL_PROC entry point, physical */
77 u64 sal_proc; /* SAL_PROC entry point, physical */
78 u64 rv_rc; /* MCA - Rendezvous state, INIT - reason code */
79 u64 proc_state_param; /* from R18 */
80 u64 monarch; /* 1 for a monarch event, 0 for a slave */
81
82 /* common */
83 u64 sal_ra; /* Return address in SAL, physical */
84 u64 sal_gp; /* GP of the SAL - physical */
85 pal_min_state_area_t *pal_min_state; /* from R17. physical in asm, virtual in C */
86 /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK).
87 * Note: if the MCA/INIT recovery code wants to resume to a new context
88 * then it must change these values to reflect the new kernel stack.
89 */
90 u64 prev_IA64_KR_CURRENT; /* previous value of IA64_KR(CURRENT) */
91 u64 prev_IA64_KR_CURRENT_STACK;
92 struct task_struct *prev_task; /* previous task, NULL if it is not useful */
93 /* Some interrupt registers are not saved in minstate, pt_regs or
94 * switch_stack. Because MCA/INIT can occur when interrupts are
95 * disabled, we need to save the additional interrupt registers over
96 * MCA/INIT and resume.
97 */
98 u64 isr;
99 u64 ifa;
100 u64 itir;
101 u64 iipa;
102 u64 iim;
103 u64 iha;
104
105 /* OS to SAL */
106 u64 os_status; /* OS status to SAL, enum below */
107 u64 context; /* 0 if return to same context
108 1 if return to new context */
109};
110
111enum {
112 IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */
113 IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */
114 IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */
115 IA64_MCA_HALT = -3 /* System to be halted by SAL */
116};
117
118enum {
119 IA64_INIT_RESUME = 0x0, /* Resume after return from INIT */
120 IA64_INIT_WARM_BOOT = -1, /* Warm boot of the system need from SAL */
121};
122
123enum {
124 IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */
125 IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */
126};
127
128/* Per-CPU MCA state that is too big for normal per-CPU variables. */
129
130struct ia64_mca_cpu {
131 u64 mca_stack[KERNEL_STACK_SIZE/8];
132 u64 init_stack[KERNEL_STACK_SIZE/8];
133};
134
135/* Array of physical addresses of each CPU's MCA area. */
136extern unsigned long __per_cpu_mca[NR_CPUS];
137
138extern int cpe_vector;
139extern int ia64_cpe_irq;
140extern void ia64_mca_init(void);
141extern void ia64_mca_cpu_init(void *);
142extern void ia64_os_mca_dispatch(void);
143extern void ia64_os_mca_dispatch_end(void);
144extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *);
145extern void ia64_init_handler(struct pt_regs *,
146 struct switch_stack *,
147 struct ia64_sal_os_state *);
148extern void ia64_monarch_init_handler(void);
149extern void ia64_slave_init_handler(void);
150extern void ia64_mca_cmc_vector_setup(void);
151extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *));
152extern void ia64_unreg_MCA_extension(void);
153extern u64 ia64_get_rnat(u64 *);
154extern void ia64_mca_printk(const char * fmt, ...)
155 __attribute__ ((format (printf, 1, 2)));
156
157struct ia64_mca_notify_die {
158 struct ia64_sal_os_state *sos;
159 int *monarch_cpu;
160 int *data;
161};
162
163DECLARE_PER_CPU(u64, ia64_mca_pal_base);
164
165#else /* __ASSEMBLY__ */
166
167#define IA64_MCA_CORRECTED 0x0 /* Error has been corrected by OS_MCA */
168#define IA64_MCA_WARM_BOOT -1 /* Warm boot of the system need from SAL */
169#define IA64_MCA_COLD_BOOT -2 /* Cold boot of the system need from SAL */
170#define IA64_MCA_HALT -3 /* System to be halted by SAL */
171
172#define IA64_INIT_RESUME 0x0 /* Resume after return from INIT */
173#define IA64_INIT_WARM_BOOT -1 /* Warm boot of the system need from SAL */
174
175#define IA64_MCA_SAME_CONTEXT 0x0 /* SAL to return to same context */
176#define IA64_MCA_NEW_CONTEXT -1 /* SAL to return to new context */
177
178#endif /* !__ASSEMBLY__ */
179#endif /* _ASM_IA64_MCA_H */
diff --git a/arch/ia64/include/asm/mca_asm.h b/arch/ia64/include/asm/mca_asm.h
new file mode 100644
index 000000000000..dd2a5b134390
--- /dev/null
+++ b/arch/ia64/include/asm/mca_asm.h
@@ -0,0 +1,242 @@
1/*
2 * File: mca_asm.h
3 * Purpose: Machine check handling specific defines
4 *
5 * Copyright (C) 1999 Silicon Graphics, Inc.
6 * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
7 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
8 * Copyright (C) 2000 Hewlett-Packard Co.
9 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Copyright (C) 2002 Intel Corp.
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2005 Silicon Graphics, Inc
13 * Copyright (C) 2005 Keith Owens <kaos@sgi.com>
14 */
15#ifndef _ASM_IA64_MCA_ASM_H
16#define _ASM_IA64_MCA_ASM_H
17
18#define PSR_IC 13
19#define PSR_I 14
20#define PSR_DT 17
21#define PSR_RT 27
22#define PSR_MC 35
23#define PSR_IT 36
24#define PSR_BN 44
25
26/*
27 * This macro converts a instruction virtual address to a physical address
28 * Right now for simulation purposes the virtual addresses are
29 * direct mapped to physical addresses.
30 * 1. Lop off bits 61 thru 63 in the virtual address
31 */
32#define INST_VA_TO_PA(addr) \
33 dep addr = 0, addr, 61, 3
34/*
35 * This macro converts a data virtual address to a physical address
36 * Right now for simulation purposes the virtual addresses are
37 * direct mapped to physical addresses.
38 * 1. Lop off bits 61 thru 63 in the virtual address
39 */
40#define DATA_VA_TO_PA(addr) \
41 tpa addr = addr
42/*
43 * This macro converts a data physical address to a virtual address
44 * Right now for simulation purposes the virtual addresses are
45 * direct mapped to physical addresses.
46 * 1. Put 0x7 in bits 61 thru 63.
47 */
48#define DATA_PA_TO_VA(addr,temp) \
49 mov temp = 0x7 ;; \
50 dep addr = temp, addr, 61, 3
51
52#define GET_THIS_PADDR(reg, var) \
53 mov reg = IA64_KR(PER_CPU_DATA);; \
54 addl reg = THIS_CPU(var), reg
55
56/*
57 * This macro jumps to the instruction at the given virtual address
58 * and starts execution in physical mode with all the address
59 * translations turned off.
60 * 1. Save the current psr
61 * 2. Make sure that all the upper 32 bits are off
62 *
63 * 3. Clear the interrupt enable and interrupt state collection bits
64 * in the psr before updating the ipsr and iip.
65 *
66 * 4. Turn off the instruction, data and rse translation bits of the psr
67 * and store the new value into ipsr
68 * Also make sure that the interrupts are disabled.
69 * Ensure that we are in little endian mode.
70 * [psr.{rt, it, dt, i, be} = 0]
71 *
72 * 5. Get the physical address corresponding to the virtual address
73 * of the next instruction bundle and put it in iip.
74 * (Using magic numbers 24 and 40 in the deposint instruction since
75 * the IA64_SDK code directly maps to lower 24bits as physical address
76 * from a virtual address).
77 *
78 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
79 */
80#define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
81 mov old_psr = psr; \
82 ;; \
83 dep old_psr = 0, old_psr, 32, 32; \
84 \
85 mov ar.rsc = 0 ; \
86 ;; \
87 srlz.d; \
88 mov temp2 = ar.bspstore; \
89 ;; \
90 DATA_VA_TO_PA(temp2); \
91 ;; \
92 mov temp1 = ar.rnat; \
93 ;; \
94 mov ar.bspstore = temp2; \
95 ;; \
96 mov ar.rnat = temp1; \
97 mov temp1 = psr; \
98 mov temp2 = psr; \
99 ;; \
100 \
101 dep temp2 = 0, temp2, PSR_IC, 2; \
102 ;; \
103 mov psr.l = temp2; \
104 ;; \
105 srlz.d; \
106 dep temp1 = 0, temp1, 32, 32; \
107 ;; \
108 dep temp1 = 0, temp1, PSR_IT, 1; \
109 ;; \
110 dep temp1 = 0, temp1, PSR_DT, 1; \
111 ;; \
112 dep temp1 = 0, temp1, PSR_RT, 1; \
113 ;; \
114 dep temp1 = 0, temp1, PSR_I, 1; \
115 ;; \
116 dep temp1 = 0, temp1, PSR_IC, 1; \
117 ;; \
118 dep temp1 = -1, temp1, PSR_MC, 1; \
119 ;; \
120 mov cr.ipsr = temp1; \
121 ;; \
122 LOAD_PHYSICAL(p0, temp2, start_addr); \
123 ;; \
124 mov cr.iip = temp2; \
125 mov cr.ifs = r0; \
126 DATA_VA_TO_PA(sp); \
127 DATA_VA_TO_PA(gp); \
128 ;; \
129 srlz.i; \
130 ;; \
131 nop 1; \
132 nop 2; \
133 nop 1; \
134 nop 2; \
135 rfi; \
136 ;;
137
138/*
139 * This macro jumps to the instruction at the given virtual address
140 * and starts execution in virtual mode with all the address
141 * translations turned on.
142 * 1. Get the old saved psr
143 *
144 * 2. Clear the interrupt state collection bit in the current psr.
145 *
146 * 3. Set the instruction translation bit back in the old psr
147 * Note we have to do this since we are right now saving only the
148 * lower 32-bits of old psr.(Also the old psr has the data and
149 * rse translation bits on)
150 *
151 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
152 *
153 * 5. Reset the current thread pointer (r13).
154 *
155 * 6. Set iip to the virtual address of the next instruction bundle.
156 *
157 * 7. Do an rfi to move ipsr to psr and iip to ip.
158 */
159
160#define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
161 mov temp2 = psr; \
162 ;; \
163 mov old_psr = temp2; \
164 ;; \
165 dep temp2 = 0, temp2, PSR_IC, 2; \
166 ;; \
167 mov psr.l = temp2; \
168 mov ar.rsc = 0; \
169 ;; \
170 srlz.d; \
171 mov r13 = ar.k6; \
172 mov temp2 = ar.bspstore; \
173 ;; \
174 DATA_PA_TO_VA(temp2,temp1); \
175 ;; \
176 mov temp1 = ar.rnat; \
177 ;; \
178 mov ar.bspstore = temp2; \
179 ;; \
180 mov ar.rnat = temp1; \
181 ;; \
182 mov temp1 = old_psr; \
183 ;; \
184 mov temp2 = 1; \
185 ;; \
186 dep temp1 = temp2, temp1, PSR_IC, 1; \
187 ;; \
188 dep temp1 = temp2, temp1, PSR_IT, 1; \
189 ;; \
190 dep temp1 = temp2, temp1, PSR_DT, 1; \
191 ;; \
192 dep temp1 = temp2, temp1, PSR_RT, 1; \
193 ;; \
194 dep temp1 = temp2, temp1, PSR_BN, 1; \
195 ;; \
196 \
197 mov cr.ipsr = temp1; \
198 movl temp2 = start_addr; \
199 ;; \
200 mov cr.iip = temp2; \
201 movl gp = __gp \
202 ;; \
203 DATA_PA_TO_VA(sp, temp1); \
204 srlz.i; \
205 ;; \
206 nop 1; \
207 nop 2; \
208 nop 1; \
209 rfi \
210 ;;
211
212/*
213 * The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
214 * stacks, except that the SAL/OS state and a switch_stack are stored near the
215 * top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as
216 * well as MCA over INIT, each event needs its own SAL/OS state. All entries
217 * are 16 byte aligned.
218 *
219 * +---------------------------+
220 * | pt_regs |
221 * +---------------------------+
222 * | switch_stack |
223 * +---------------------------+
224 * | SAL/OS state |
225 * +---------------------------+
226 * | 16 byte scratch area |
227 * +---------------------------+ <-------- SP at start of C MCA handler
228 * | ..... |
229 * +---------------------------+
230 * | RBS for MCA/INIT handler |
231 * +---------------------------+
232 * | struct task for MCA/INIT |
233 * +---------------------------+ <-------- Bottom of MCA/INIT stack
234 */
235
236#define ALIGN16(x) ((x)&~15)
237#define MCA_PT_REGS_OFFSET ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
238#define MCA_SWITCH_STACK_OFFSET ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
239#define MCA_SOS_OFFSET ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
240#define MCA_SP_OFFSET ALIGN16(MCA_SOS_OFFSET-16)
241
242#endif /* _ASM_IA64_MCA_ASM_H */
diff --git a/arch/ia64/include/asm/meminit.h b/arch/ia64/include/asm/meminit.h
new file mode 100644
index 000000000000..7245a5781594
--- /dev/null
+++ b/arch/ia64/include/asm/meminit.h
@@ -0,0 +1,75 @@
1#ifndef meminit_h
2#define meminit_h
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9
10
11/*
12 * Entries defined so far:
13 * - boot param structure itself
14 * - memory map
15 * - initrd (optional)
16 * - command line string
17 * - kernel code & data
18 * - crash dumping code reserved region
19 * - Kernel memory map built from EFI memory map
20 * - ELF core header
21 *
22 * More could be added if necessary
23 */
24#define IA64_MAX_RSVD_REGIONS 8
25
26struct rsvd_region {
27 unsigned long start; /* virtual address of beginning of element */
28 unsigned long end; /* virtual address of end of element + 1 */
29};
30
31extern struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
32extern int num_rsvd_regions;
33
34extern void find_memory (void);
35extern void reserve_memory (void);
36extern void find_initrd (void);
37extern int filter_rsvd_memory (unsigned long start, unsigned long end, void *arg);
38extern int filter_memory (unsigned long start, unsigned long end, void *arg);
39extern unsigned long efi_memmap_init(unsigned long *s, unsigned long *e);
40extern int find_max_min_low_pfn (unsigned long , unsigned long, void *);
41
42extern unsigned long vmcore_find_descriptor_size(unsigned long address);
43extern int reserve_elfcorehdr(unsigned long *start, unsigned long *end);
44
45/*
46 * For rounding an address to the next IA64_GRANULE_SIZE or order
47 */
48#define GRANULEROUNDDOWN(n) ((n) & ~(IA64_GRANULE_SIZE-1))
49#define GRANULEROUNDUP(n) (((n)+IA64_GRANULE_SIZE-1) & ~(IA64_GRANULE_SIZE-1))
50#define ORDERROUNDDOWN(n) ((n) & ~((PAGE_SIZE<<MAX_ORDER)-1))
51
52#ifdef CONFIG_NUMA
53 extern void call_pernode_memory (unsigned long start, unsigned long len, void *func);
54#else
55# define call_pernode_memory(start, len, func) (*func)(start, len, 0)
56#endif
57
58#define IGNORE_PFN0 1 /* XXX fix me: ignore pfn 0 until TLB miss handler is updated... */
59
60extern int register_active_ranges(u64 start, u64 len, int nid);
61
62#ifdef CONFIG_VIRTUAL_MEM_MAP
63# define LARGE_GAP 0x40000000 /* Use virtual mem map if hole is > than this */
64 extern unsigned long vmalloc_end;
65 extern struct page *vmem_map;
66 extern int find_largest_hole (u64 start, u64 end, void *arg);
67 extern int create_mem_map_page_table (u64 start, u64 end, void *arg);
68 extern int vmemmap_find_next_valid_pfn(int, int);
69#else
70static inline int vmemmap_find_next_valid_pfn(int node, int i)
71{
72 return i + 1;
73}
74#endif
75#endif /* meminit_h */
diff --git a/arch/ia64/include/asm/mman.h b/arch/ia64/include/asm/mman.h
new file mode 100644
index 000000000000..c73b87832a1e
--- /dev/null
+++ b/arch/ia64/include/asm/mman.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_IA64_MMAN_H
2#define _ASM_IA64_MMAN_H
3
4/*
5 * Based on <asm-i386/mman.h>.
6 *
7 * Modified 1998-2000, 2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#include <asm-generic/mman.h>
12
13#define MAP_GROWSDOWN 0x00100 /* stack-like segment */
14#define MAP_GROWSUP 0x00200 /* register stack-like segment */
15#define MAP_DENYWRITE 0x00800 /* ETXTBSY */
16#define MAP_EXECUTABLE 0x01000 /* mark it as an executable */
17#define MAP_LOCKED 0x02000 /* pages are locked */
18#define MAP_NORESERVE 0x04000 /* don't check for reservations */
19#define MAP_POPULATE 0x08000 /* populate (prefault) pagetables */
20#define MAP_NONBLOCK 0x10000 /* do not block on IO */
21
22#define MCL_CURRENT 1 /* lock all current mappings */
23#define MCL_FUTURE 2 /* lock all future mappings */
24
25#ifdef __KERNEL__
26#ifndef __ASSEMBLY__
27#define arch_mmap_check ia64_mmap_check
28int ia64_mmap_check(unsigned long addr, unsigned long len,
29 unsigned long flags);
30#endif
31#endif
32
33#endif /* _ASM_IA64_MMAN_H */
diff --git a/arch/ia64/include/asm/mmu.h b/arch/ia64/include/asm/mmu.h
new file mode 100644
index 000000000000..611432ba579c
--- /dev/null
+++ b/arch/ia64/include/asm/mmu.h
@@ -0,0 +1,13 @@
1#ifndef __MMU_H
2#define __MMU_H
3
4/*
5 * Type for a context number. We declare it volatile to ensure proper
6 * ordering when it's accessed outside of spinlock'd critical sections
7 * (e.g., as done in activate_mm() and init_new_context()).
8 */
9typedef volatile unsigned long mm_context_t;
10
11typedef unsigned long nv_mm_context_t;
12
13#endif
diff --git a/arch/ia64/include/asm/mmu_context.h b/arch/ia64/include/asm/mmu_context.h
new file mode 100644
index 000000000000..040bc87db930
--- /dev/null
+++ b/arch/ia64/include/asm/mmu_context.h
@@ -0,0 +1,198 @@
1#ifndef _ASM_IA64_MMU_CONTEXT_H
2#define _ASM_IA64_MMU_CONTEXT_H
3
4/*
5 * Copyright (C) 1998-2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9/*
10 * Routines to manage the allocation of task context numbers. Task context
11 * numbers are used to reduce or eliminate the need to perform TLB flushes
12 * due to context switches. Context numbers are implemented using ia-64
13 * region ids. Since the IA-64 TLB does not consider the region number when
14 * performing a TLB lookup, we need to assign a unique region id to each
15 * region in a process. We use the least significant three bits in aregion
16 * id for this purpose.
17 */
18
19#define IA64_REGION_ID_KERNEL 0 /* the kernel's region id (tlb.c depends on this being 0) */
20
21#define ia64_rid(ctx,addr) (((ctx) << 3) | (addr >> 61))
22
23# include <asm/page.h>
24# ifndef __ASSEMBLY__
25
26#include <linux/compiler.h>
27#include <linux/percpu.h>
28#include <linux/sched.h>
29#include <linux/spinlock.h>
30
31#include <asm/processor.h>
32#include <asm-generic/mm_hooks.h>
33
34struct ia64_ctx {
35 spinlock_t lock;
36 unsigned int next; /* next context number to use */
37 unsigned int limit; /* available free range */
38 unsigned int max_ctx; /* max. context value supported by all CPUs */
39 /* call wrap_mmu_context when next >= max */
40 unsigned long *bitmap; /* bitmap size is max_ctx+1 */
41 unsigned long *flushmap;/* pending rid to be flushed */
42};
43
44extern struct ia64_ctx ia64_ctx;
45DECLARE_PER_CPU(u8, ia64_need_tlb_flush);
46
47extern void mmu_context_init (void);
48extern void wrap_mmu_context (struct mm_struct *mm);
49
50static inline void
51enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk)
52{
53}
54
55/*
56 * When the context counter wraps around all TLBs need to be flushed because
57 * an old context number might have been reused. This is signalled by the
58 * ia64_need_tlb_flush per-CPU variable, which is checked in the routine
59 * below. Called by activate_mm(). <efocht@ess.nec.de>
60 */
61static inline void
62delayed_tlb_flush (void)
63{
64 extern void local_flush_tlb_all (void);
65 unsigned long flags;
66
67 if (unlikely(__ia64_per_cpu_var(ia64_need_tlb_flush))) {
68 spin_lock_irqsave(&ia64_ctx.lock, flags);
69 if (__ia64_per_cpu_var(ia64_need_tlb_flush)) {
70 local_flush_tlb_all();
71 __ia64_per_cpu_var(ia64_need_tlb_flush) = 0;
72 }
73 spin_unlock_irqrestore(&ia64_ctx.lock, flags);
74 }
75}
76
77static inline nv_mm_context_t
78get_mmu_context (struct mm_struct *mm)
79{
80 unsigned long flags;
81 nv_mm_context_t context = mm->context;
82
83 if (likely(context))
84 goto out;
85
86 spin_lock_irqsave(&ia64_ctx.lock, flags);
87 /* re-check, now that we've got the lock: */
88 context = mm->context;
89 if (context == 0) {
90 cpus_clear(mm->cpu_vm_mask);
91 if (ia64_ctx.next >= ia64_ctx.limit) {
92 ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
93 ia64_ctx.max_ctx, ia64_ctx.next);
94 ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
95 ia64_ctx.max_ctx, ia64_ctx.next);
96 if (ia64_ctx.next >= ia64_ctx.max_ctx)
97 wrap_mmu_context(mm);
98 }
99 mm->context = context = ia64_ctx.next++;
100 __set_bit(context, ia64_ctx.bitmap);
101 }
102 spin_unlock_irqrestore(&ia64_ctx.lock, flags);
103out:
104 /*
105 * Ensure we're not starting to use "context" before any old
106 * uses of it are gone from our TLB.
107 */
108 delayed_tlb_flush();
109
110 return context;
111}
112
113/*
114 * Initialize context number to some sane value. MM is guaranteed to be a
115 * brand-new address-space, so no TLB flushing is needed, ever.
116 */
117static inline int
118init_new_context (struct task_struct *p, struct mm_struct *mm)
119{
120 mm->context = 0;
121 return 0;
122}
123
124static inline void
125destroy_context (struct mm_struct *mm)
126{
127 /* Nothing to do. */
128}
129
130static inline void
131reload_context (nv_mm_context_t context)
132{
133 unsigned long rid;
134 unsigned long rid_incr = 0;
135 unsigned long rr0, rr1, rr2, rr3, rr4, old_rr4;
136
137 old_rr4 = ia64_get_rr(RGN_BASE(RGN_HPAGE));
138 rid = context << 3; /* make space for encoding the region number */
139 rid_incr = 1 << 8;
140
141 /* encode the region id, preferred page size, and VHPT enable bit: */
142 rr0 = (rid << 8) | (PAGE_SHIFT << 2) | 1;
143 rr1 = rr0 + 1*rid_incr;
144 rr2 = rr0 + 2*rid_incr;
145 rr3 = rr0 + 3*rid_incr;
146 rr4 = rr0 + 4*rid_incr;
147#ifdef CONFIG_HUGETLB_PAGE
148 rr4 = (rr4 & (~(0xfcUL))) | (old_rr4 & 0xfc);
149
150# if RGN_HPAGE != 4
151# error "reload_context assumes RGN_HPAGE is 4"
152# endif
153#endif
154
155 ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
156 ia64_srlz_i(); /* srlz.i implies srlz.d */
157}
158
159/*
160 * Must be called with preemption off
161 */
162static inline void
163activate_context (struct mm_struct *mm)
164{
165 nv_mm_context_t context;
166
167 do {
168 context = get_mmu_context(mm);
169 if (!cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
170 cpu_set(smp_processor_id(), mm->cpu_vm_mask);
171 reload_context(context);
172 /*
173 * in the unlikely event of a TLB-flush by another thread,
174 * redo the load.
175 */
176 } while (unlikely(context != mm->context));
177}
178
179#define deactivate_mm(tsk,mm) do { } while (0)
180
181/*
182 * Switch from address space PREV to address space NEXT.
183 */
184static inline void
185activate_mm (struct mm_struct *prev, struct mm_struct *next)
186{
187 /*
188 * We may get interrupts here, but that's OK because interrupt
189 * handlers cannot touch user-space.
190 */
191 ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd));
192 activate_context(next);
193}
194
195#define switch_mm(prev_mm,next_mm,next_task) activate_mm(prev_mm, next_mm)
196
197# endif /* ! __ASSEMBLY__ */
198#endif /* _ASM_IA64_MMU_CONTEXT_H */
diff --git a/arch/ia64/include/asm/mmzone.h b/arch/ia64/include/asm/mmzone.h
new file mode 100644
index 000000000000..34efe88eb849
--- /dev/null
+++ b/arch/ia64/include/asm/mmzone.h
@@ -0,0 +1,50 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000,2003 Silicon Graphics, Inc. All rights reserved.
7 * Copyright (c) 2002 NEC Corp.
8 * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
9 * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
10 */
11#ifndef _ASM_IA64_MMZONE_H
12#define _ASM_IA64_MMZONE_H
13
14#include <linux/numa.h>
15#include <asm/page.h>
16#include <asm/meminit.h>
17
18#ifdef CONFIG_NUMA
19
20static inline int pfn_to_nid(unsigned long pfn)
21{
22#ifdef CONFIG_NUMA
23 extern int paddr_to_nid(unsigned long);
24 int nid = paddr_to_nid(pfn << PAGE_SHIFT);
25 if (nid < 0)
26 return 0;
27 else
28 return nid;
29#else
30 return 0;
31#endif
32}
33
34#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
35extern int early_pfn_to_nid(unsigned long pfn);
36#endif
37
38#ifdef CONFIG_IA64_DIG /* DIG systems are small */
39# define MAX_PHYSNODE_ID 8
40# define NR_NODE_MEMBLKS (MAX_NUMNODES * 8)
41#else /* sn2 is the biggest case, so we use that if !DIG */
42# define MAX_PHYSNODE_ID 2048
43# define NR_NODE_MEMBLKS (MAX_NUMNODES * 4)
44#endif
45
46#else /* CONFIG_NUMA */
47# define NR_NODE_MEMBLKS (MAX_NUMNODES * 4)
48#endif /* CONFIG_NUMA */
49
50#endif /* _ASM_IA64_MMZONE_H */
diff --git a/arch/ia64/include/asm/module.h b/arch/ia64/include/asm/module.h
new file mode 100644
index 000000000000..d2da61e4c49b
--- /dev/null
+++ b/arch/ia64/include/asm/module.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_IA64_MODULE_H
2#define _ASM_IA64_MODULE_H
3
4/*
5 * IA-64-specific support for kernel module loader.
6 *
7 * Copyright (C) 2003 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11struct elf64_shdr; /* forward declration */
12
13struct mod_arch_specific {
14 struct elf64_shdr *core_plt; /* core PLT section */
15 struct elf64_shdr *init_plt; /* init PLT section */
16 struct elf64_shdr *got; /* global offset table */
17 struct elf64_shdr *opd; /* official procedure descriptors */
18 struct elf64_shdr *unwind; /* unwind-table section */
19 unsigned long gp; /* global-pointer for module */
20
21 void *core_unw_table; /* core unwind-table cookie returned by unwinder */
22 void *init_unw_table; /* init unwind-table cookie returned by unwinder */
23 unsigned int next_got_entry; /* index of next available got entry */
24};
25
26#define Elf_Shdr Elf64_Shdr
27#define Elf_Sym Elf64_Sym
28#define Elf_Ehdr Elf64_Ehdr
29
30#define MODULE_PROC_FAMILY "ia64"
31#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY \
32 "gcc-" __stringify(__GNUC__) "." __stringify(__GNUC_MINOR__)
33
34#define ARCH_SHF_SMALL SHF_IA_64_SHORT
35
36#endif /* _ASM_IA64_MODULE_H */
diff --git a/arch/ia64/include/asm/msgbuf.h b/arch/ia64/include/asm/msgbuf.h
new file mode 100644
index 000000000000..6c64c0d2aae1
--- /dev/null
+++ b/arch/ia64/include/asm/msgbuf.h
@@ -0,0 +1,27 @@
1#ifndef _ASM_IA64_MSGBUF_H
2#define _ASM_IA64_MSGBUF_H
3
4/*
5 * The msqid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct msqid64_ds {
14 struct ipc64_perm msg_perm;
15 __kernel_time_t msg_stime; /* last msgsnd time */
16 __kernel_time_t msg_rtime; /* last msgrcv time */
17 __kernel_time_t msg_ctime; /* last change time */
18 unsigned long msg_cbytes; /* current number of bytes on queue */
19 unsigned long msg_qnum; /* number of messages in queue */
20 unsigned long msg_qbytes; /* max number of bytes on queue */
21 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
22 __kernel_pid_t msg_lrpid; /* last receive pid */
23 unsigned long __unused1;
24 unsigned long __unused2;
25};
26
27#endif /* _ASM_IA64_MSGBUF_H */
diff --git a/arch/ia64/include/asm/mutex.h b/arch/ia64/include/asm/mutex.h
new file mode 100644
index 000000000000..bed73a643a56
--- /dev/null
+++ b/arch/ia64/include/asm/mutex.h
@@ -0,0 +1,92 @@
1/*
2 * ia64 implementation of the mutex fastpath.
3 *
4 * Copyright (C) 2006 Ken Chen <kenneth.w.chen@intel.com>
5 *
6 */
7
8#ifndef _ASM_MUTEX_H
9#define _ASM_MUTEX_H
10
11/**
12 * __mutex_fastpath_lock - try to take the lock by moving the count
13 * from 1 to a 0 value
14 * @count: pointer of type atomic_t
15 * @fail_fn: function to call if the original value was not 1
16 *
17 * Change the count from 1 to a value lower than 1, and call <fail_fn> if
18 * it wasn't 1 originally. This function MUST leave the value lower than
19 * 1 even when the "1" assertion wasn't true.
20 */
21static inline void
22__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
23{
24 if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
25 fail_fn(count);
26}
27
28/**
29 * __mutex_fastpath_lock_retval - try to take the lock by moving the count
30 * from 1 to a 0 value
31 * @count: pointer of type atomic_t
32 * @fail_fn: function to call if the original value was not 1
33 *
34 * Change the count from 1 to a value lower than 1, and call <fail_fn> if
35 * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
36 * or anything the slow path function returns.
37 */
38static inline int
39__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
40{
41 if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
42 return fail_fn(count);
43 return 0;
44}
45
46/**
47 * __mutex_fastpath_unlock - try to promote the count from 0 to 1
48 * @count: pointer of type atomic_t
49 * @fail_fn: function to call if the original value was not 0
50 *
51 * Try to promote the count from 0 to 1. If it wasn't 0, call <fail_fn>.
52 * In the failure case, this function is allowed to either set the value to
53 * 1, or to set it to a value lower than 1.
54 *
55 * If the implementation sets it to a value of lower than 1, then the
56 * __mutex_slowpath_needs_to_unlock() macro needs to return 1, it needs
57 * to return 0 otherwise.
58 */
59static inline void
60__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
61{
62 int ret = ia64_fetchadd4_rel(count, 1);
63 if (unlikely(ret < 0))
64 fail_fn(count);
65}
66
67#define __mutex_slowpath_needs_to_unlock() 1
68
69/**
70 * __mutex_fastpath_trylock - try to acquire the mutex, without waiting
71 *
72 * @count: pointer of type atomic_t
73 * @fail_fn: fallback function
74 *
75 * Change the count from 1 to a value lower than 1, and return 0 (failure)
76 * if it wasn't 1 originally, or return 1 (success) otherwise. This function
77 * MUST leave the value lower than 1 even when the "1" assertion wasn't true.
78 * Additionally, if the value was < 0 originally, this function must not leave
79 * it to 0 on failure.
80 *
81 * If the architecture has no effective trylock variant, it should call the
82 * <fail_fn> spinlock-based trylock variant unconditionally.
83 */
84static inline int
85__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
86{
87 if (cmpxchg_acq(count, 1, 0) == 1)
88 return 1;
89 return 0;
90}
91
92#endif
diff --git a/arch/ia64/include/asm/native/inst.h b/arch/ia64/include/asm/native/inst.h
new file mode 100644
index 000000000000..c8efbf7b849e
--- /dev/null
+++ b/arch/ia64/include/asm/native/inst.h
@@ -0,0 +1,175 @@
1/******************************************************************************
2 * arch/ia64/include/asm/native/inst.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23#define DO_SAVE_MIN IA64_NATIVE_DO_SAVE_MIN
24
25#define __paravirt_switch_to ia64_native_switch_to
26#define __paravirt_leave_syscall ia64_native_leave_syscall
27#define __paravirt_work_processed_syscall ia64_native_work_processed_syscall
28#define __paravirt_leave_kernel ia64_native_leave_kernel
29#define __paravirt_pending_syscall_end ia64_work_pending_syscall_end
30#define __paravirt_work_processed_syscall_target \
31 ia64_work_processed_syscall
32
33#ifdef CONFIG_PARAVIRT_GUEST_ASM_CLOBBER_CHECK
34# define PARAVIRT_POISON 0xdeadbeefbaadf00d
35# define CLOBBER(clob) \
36 ;; \
37 movl clob = PARAVIRT_POISON; \
38 ;;
39#else
40# define CLOBBER(clob) /* nothing */
41#endif
42
43#define MOV_FROM_IFA(reg) \
44 mov reg = cr.ifa
45
46#define MOV_FROM_ITIR(reg) \
47 mov reg = cr.itir
48
49#define MOV_FROM_ISR(reg) \
50 mov reg = cr.isr
51
52#define MOV_FROM_IHA(reg) \
53 mov reg = cr.iha
54
55#define MOV_FROM_IPSR(pred, reg) \
56(pred) mov reg = cr.ipsr
57
58#define MOV_FROM_IIM(reg) \
59 mov reg = cr.iim
60
61#define MOV_FROM_IIP(reg) \
62 mov reg = cr.iip
63
64#define MOV_FROM_IVR(reg, clob) \
65 mov reg = cr.ivr \
66 CLOBBER(clob)
67
68#define MOV_FROM_PSR(pred, reg, clob) \
69(pred) mov reg = psr \
70 CLOBBER(clob)
71
72#define MOV_TO_IFA(reg, clob) \
73 mov cr.ifa = reg \
74 CLOBBER(clob)
75
76#define MOV_TO_ITIR(pred, reg, clob) \
77(pred) mov cr.itir = reg \
78 CLOBBER(clob)
79
80#define MOV_TO_IHA(pred, reg, clob) \
81(pred) mov cr.iha = reg \
82 CLOBBER(clob)
83
84#define MOV_TO_IPSR(pred, reg, clob) \
85(pred) mov cr.ipsr = reg \
86 CLOBBER(clob)
87
88#define MOV_TO_IFS(pred, reg, clob) \
89(pred) mov cr.ifs = reg \
90 CLOBBER(clob)
91
92#define MOV_TO_IIP(reg, clob) \
93 mov cr.iip = reg \
94 CLOBBER(clob)
95
96#define MOV_TO_KR(kr, reg, clob0, clob1) \
97 mov IA64_KR(kr) = reg \
98 CLOBBER(clob0) \
99 CLOBBER(clob1)
100
101#define ITC_I(pred, reg, clob) \
102(pred) itc.i reg \
103 CLOBBER(clob)
104
105#define ITC_D(pred, reg, clob) \
106(pred) itc.d reg \
107 CLOBBER(clob)
108
109#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
110(pred_i) itc.i reg; \
111(pred_d) itc.d reg \
112 CLOBBER(clob)
113
114#define THASH(pred, reg0, reg1, clob) \
115(pred) thash reg0 = reg1 \
116 CLOBBER(clob)
117
118#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
119 ssm psr.ic | PSR_DEFAULT_BITS \
120 CLOBBER(clob0) \
121 CLOBBER(clob1) \
122 ;; \
123 srlz.i /* guarantee that interruption collectin is on */ \
124 ;;
125
126#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
127 ssm psr.ic \
128 CLOBBER(clob0) \
129 CLOBBER(clob1) \
130 ;; \
131 srlz.d
132
133#define RSM_PSR_IC(clob) \
134 rsm psr.ic \
135 CLOBBER(clob)
136
137#define SSM_PSR_I(pred, pred_clob, clob) \
138(pred) ssm psr.i \
139 CLOBBER(clob)
140
141#define RSM_PSR_I(pred, clob0, clob1) \
142(pred) rsm psr.i \
143 CLOBBER(clob0) \
144 CLOBBER(clob1)
145
146#define RSM_PSR_I_IC(clob0, clob1, clob2) \
147 rsm psr.i | psr.ic \
148 CLOBBER(clob0) \
149 CLOBBER(clob1) \
150 CLOBBER(clob2)
151
152#define RSM_PSR_DT \
153 rsm psr.dt
154
155#define SSM_PSR_DT_AND_SRLZ_I \
156 ssm psr.dt \
157 ;; \
158 srlz.i
159
160#define BSW_0(clob0, clob1, clob2) \
161 bsw.0 \
162 CLOBBER(clob0) \
163 CLOBBER(clob1) \
164 CLOBBER(clob2)
165
166#define BSW_1(clob0, clob1) \
167 bsw.1 \
168 CLOBBER(clob0) \
169 CLOBBER(clob1)
170
171#define COVER \
172 cover
173
174#define RFI \
175 rfi
diff --git a/arch/ia64/include/asm/native/irq.h b/arch/ia64/include/asm/native/irq.h
new file mode 100644
index 000000000000..887a228e2edb
--- /dev/null
+++ b/arch/ia64/include/asm/native/irq.h
@@ -0,0 +1,33 @@
1/******************************************************************************
2 * arch/ia64/include/asm/native/irq.h
3 *
4 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef _ASM_IA64_NATIVE_IRQ_H
23#define _ASM_IA64_NATIVE_IRQ_H
24
25#define NR_VECTORS 256
26
27#if (NR_VECTORS + 32 * NR_CPUS) < 1024
28#define IA64_NATIVE_NR_IRQS (NR_VECTORS + 32 * NR_CPUS)
29#else
30#define IA64_NATIVE_NR_IRQS 1024
31#endif
32
33#endif /* _ASM_IA64_NATIVE_IRQ_H */
diff --git a/arch/ia64/include/asm/nodedata.h b/arch/ia64/include/asm/nodedata.h
new file mode 100644
index 000000000000..2fb337b0e9b7
--- /dev/null
+++ b/arch/ia64/include/asm/nodedata.h
@@ -0,0 +1,63 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000 Silicon Graphics, Inc. All rights reserved.
7 * Copyright (c) 2002 NEC Corp.
8 * Copyright (c) 2002 Erich Focht <efocht@ess.nec.de>
9 * Copyright (c) 2002 Kimio Suganuma <k-suganuma@da.jp.nec.com>
10 */
11#ifndef _ASM_IA64_NODEDATA_H
12#define _ASM_IA64_NODEDATA_H
13
14#include <linux/numa.h>
15
16#include <asm/percpu.h>
17#include <asm/mmzone.h>
18
19#ifdef CONFIG_NUMA
20
21/*
22 * Node Data. One of these structures is located on each node of a NUMA system.
23 */
24
25struct pglist_data;
26struct ia64_node_data {
27 short active_cpu_count;
28 short node;
29 struct pglist_data *pg_data_ptrs[MAX_NUMNODES];
30};
31
32
33/*
34 * Return a pointer to the node_data structure for the executing cpu.
35 */
36#define local_node_data (local_cpu_data->node_data)
37
38/*
39 * Given a node id, return a pointer to the pg_data_t for the node.
40 *
41 * NODE_DATA - should be used in all code not related to system
42 * initialization. It uses pernode data structures to minimize
43 * offnode memory references. However, these structure are not
44 * present during boot. This macro can be used once cpu_init
45 * completes.
46 */
47#define NODE_DATA(nid) (local_node_data->pg_data_ptrs[nid])
48
49/*
50 * LOCAL_DATA_ADDR - This is to calculate the address of other node's
51 * "local_node_data" at hot-plug phase. The local_node_data
52 * is pointed by per_cpu_page. Kernel usually use it for
53 * just executing cpu. However, when new node is hot-added,
54 * the addresses of local data for other nodes are necessary
55 * to update all of them.
56 */
57#define LOCAL_DATA_ADDR(pgdat) \
58 ((struct ia64_node_data *)((u64)(pgdat) + \
59 L1_CACHE_ALIGN(sizeof(struct pglist_data))))
60
61#endif /* CONFIG_NUMA */
62
63#endif /* _ASM_IA64_NODEDATA_H */
diff --git a/arch/ia64/include/asm/numa.h b/arch/ia64/include/asm/numa.h
new file mode 100644
index 000000000000..3499ff57bf42
--- /dev/null
+++ b/arch/ia64/include/asm/numa.h
@@ -0,0 +1,82 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * This file contains NUMA specific prototypes and definitions.
7 *
8 * 2002/08/05 Erich Focht <efocht@ess.nec.de>
9 *
10 */
11#ifndef _ASM_IA64_NUMA_H
12#define _ASM_IA64_NUMA_H
13
14
15#ifdef CONFIG_NUMA
16
17#include <linux/cache.h>
18#include <linux/cpumask.h>
19#include <linux/numa.h>
20#include <linux/smp.h>
21#include <linux/threads.h>
22
23#include <asm/mmzone.h>
24
25#define NUMA_NO_NODE -1
26
27extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
28extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
29extern pg_data_t *pgdat_list[MAX_NUMNODES];
30
31/* Stuff below this line could be architecture independent */
32
33extern int num_node_memblks; /* total number of memory chunks */
34
35/*
36 * List of node memory chunks. Filled when parsing SRAT table to
37 * obtain information about memory nodes.
38*/
39
40struct node_memblk_s {
41 unsigned long start_paddr;
42 unsigned long size;
43 int nid; /* which logical node contains this chunk? */
44 int bank; /* which mem bank on this node */
45};
46
47struct node_cpuid_s {
48 u16 phys_id; /* id << 8 | eid */
49 int nid; /* logical node containing this CPU */
50};
51
52extern struct node_memblk_s node_memblk[NR_NODE_MEMBLKS];
53extern struct node_cpuid_s node_cpuid[NR_CPUS];
54
55/*
56 * ACPI 2.0 SLIT (System Locality Information Table)
57 * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf
58 *
59 * This is a matrix with "distances" between nodes, they should be
60 * proportional to the memory access latency ratios.
61 */
62
63extern u8 numa_slit[MAX_NUMNODES * MAX_NUMNODES];
64#define node_distance(from,to) (numa_slit[(from) * num_online_nodes() + (to)])
65
66extern int paddr_to_nid(unsigned long paddr);
67
68#define local_nodeid (cpu_to_node_map[smp_processor_id()])
69
70extern void map_cpu_to_node(int cpu, int nid);
71extern void unmap_cpu_from_node(int cpu, int nid);
72
73
74#else /* !CONFIG_NUMA */
75#define map_cpu_to_node(cpu, nid) do{}while(0)
76#define unmap_cpu_from_node(cpu, nid) do{}while(0)
77
78#define paddr_to_nid(addr) 0
79
80#endif /* CONFIG_NUMA */
81
82#endif /* _ASM_IA64_NUMA_H */
diff --git a/arch/ia64/include/asm/page.h b/arch/ia64/include/asm/page.h
new file mode 100644
index 000000000000..5f271bc712ee
--- /dev/null
+++ b/arch/ia64/include/asm/page.h
@@ -0,0 +1,223 @@
1#ifndef _ASM_IA64_PAGE_H
2#define _ASM_IA64_PAGE_H
3/*
4 * Pagetable related stuff.
5 *
6 * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9
10#include <asm/intrinsics.h>
11#include <asm/types.h>
12
13/*
14 * The top three bits of an IA64 address are its Region Number.
15 * Different regions are assigned to different purposes.
16 */
17#define RGN_SHIFT (61)
18#define RGN_BASE(r) (__IA64_UL_CONST(r)<<RGN_SHIFT)
19#define RGN_BITS (RGN_BASE(-1))
20
21#define RGN_KERNEL 7 /* Identity mapped region */
22#define RGN_UNCACHED 6 /* Identity mapped I/O region */
23#define RGN_GATE 5 /* Gate page, Kernel text, etc */
24#define RGN_HPAGE 4 /* For Huge TLB pages */
25
26/*
27 * PAGE_SHIFT determines the actual kernel page size.
28 */
29#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
30# define PAGE_SHIFT 12
31#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
32# define PAGE_SHIFT 13
33#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
34# define PAGE_SHIFT 14
35#elif defined(CONFIG_IA64_PAGE_SIZE_64KB)
36# define PAGE_SHIFT 16
37#else
38# error Unsupported page size!
39#endif
40
41#define PAGE_SIZE (__IA64_UL_CONST(1) << PAGE_SHIFT)
42#define PAGE_MASK (~(PAGE_SIZE - 1))
43
44#define PERCPU_PAGE_SHIFT 16 /* log2() of max. size of per-CPU area */
45#define PERCPU_PAGE_SIZE (__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
46
47
48#ifdef CONFIG_HUGETLB_PAGE
49# define HPAGE_REGION_BASE RGN_BASE(RGN_HPAGE)
50# define HPAGE_SHIFT hpage_shift
51# define HPAGE_SHIFT_DEFAULT 28 /* check ia64 SDM for architecture supported size */
52# define HPAGE_SIZE (__IA64_UL_CONST(1) << HPAGE_SHIFT)
53# define HPAGE_MASK (~(HPAGE_SIZE - 1))
54
55# define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
56#endif /* CONFIG_HUGETLB_PAGE */
57
58#ifdef __ASSEMBLY__
59# define __pa(x) ((x) - PAGE_OFFSET)
60# define __va(x) ((x) + PAGE_OFFSET)
61#else /* !__ASSEMBLY */
62# define STRICT_MM_TYPECHECKS
63
64extern void clear_page (void *page);
65extern void copy_page (void *to, void *from);
66
67/*
68 * clear_user_page() and copy_user_page() can't be inline functions because
69 * flush_dcache_page() can't be defined until later...
70 */
71#define clear_user_page(addr, vaddr, page) \
72do { \
73 clear_page(addr); \
74 flush_dcache_page(page); \
75} while (0)
76
77#define copy_user_page(to, from, vaddr, page) \
78do { \
79 copy_page((to), (from)); \
80 flush_dcache_page(page); \
81} while (0)
82
83
84#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
85({ \
86 struct page *page = alloc_page_vma( \
87 GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr); \
88 if (page) \
89 flush_dcache_page(page); \
90 page; \
91})
92
93#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
94
95#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
96
97#ifdef CONFIG_VIRTUAL_MEM_MAP
98extern int ia64_pfn_valid (unsigned long pfn);
99#else
100# define ia64_pfn_valid(pfn) 1
101#endif
102
103#ifdef CONFIG_VIRTUAL_MEM_MAP
104extern struct page *vmem_map;
105#ifdef CONFIG_DISCONTIGMEM
106# define page_to_pfn(page) ((unsigned long) (page - vmem_map))
107# define pfn_to_page(pfn) (vmem_map + (pfn))
108#else
109# include <asm-generic/memory_model.h>
110#endif
111#else
112# include <asm-generic/memory_model.h>
113#endif
114
115#ifdef CONFIG_FLATMEM
116# define pfn_valid(pfn) (((pfn) < max_mapnr) && ia64_pfn_valid(pfn))
117#elif defined(CONFIG_DISCONTIGMEM)
118extern unsigned long min_low_pfn;
119extern unsigned long max_low_pfn;
120# define pfn_valid(pfn) (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn) && ia64_pfn_valid(pfn))
121#endif
122
123#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
124#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
125#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
126
127typedef union ia64_va {
128 struct {
129 unsigned long off : 61; /* intra-region offset */
130 unsigned long reg : 3; /* region number */
131 } f;
132 unsigned long l;
133 void *p;
134} ia64_va;
135
136/*
137 * Note: These macros depend on the fact that PAGE_OFFSET has all
138 * region bits set to 1 and all other bits set to zero. They are
139 * expressed in this way to ensure they result in a single "dep"
140 * instruction.
141 */
142#define __pa(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = 0; _v.l;})
143#define __va(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg = -1; _v.p;})
144
145#define REGION_NUMBER(x) ({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
146#define REGION_OFFSET(x) ({ia64_va _v; _v.l = (long) (x); _v.f.off;})
147
148#ifdef CONFIG_HUGETLB_PAGE
149# define htlbpage_to_page(x) (((unsigned long) REGION_NUMBER(x) << 61) \
150 | (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
151# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
152extern unsigned int hpage_shift;
153#endif
154
155static __inline__ int
156get_order (unsigned long size)
157{
158 long double d = size - 1;
159 long order;
160
161 order = ia64_getf_exp(d);
162 order = order - PAGE_SHIFT - 0xffff + 1;
163 if (order < 0)
164 order = 0;
165 return order;
166}
167
168#endif /* !__ASSEMBLY__ */
169
170#ifdef STRICT_MM_TYPECHECKS
171 /*
172 * These are used to make use of C type-checking..
173 */
174 typedef struct { unsigned long pte; } pte_t;
175 typedef struct { unsigned long pmd; } pmd_t;
176#ifdef CONFIG_PGTABLE_4
177 typedef struct { unsigned long pud; } pud_t;
178#endif
179 typedef struct { unsigned long pgd; } pgd_t;
180 typedef struct { unsigned long pgprot; } pgprot_t;
181 typedef struct page *pgtable_t;
182
183# define pte_val(x) ((x).pte)
184# define pmd_val(x) ((x).pmd)
185#ifdef CONFIG_PGTABLE_4
186# define pud_val(x) ((x).pud)
187#endif
188# define pgd_val(x) ((x).pgd)
189# define pgprot_val(x) ((x).pgprot)
190
191# define __pte(x) ((pte_t) { (x) } )
192# define __pgprot(x) ((pgprot_t) { (x) } )
193
194#else /* !STRICT_MM_TYPECHECKS */
195 /*
196 * .. while these make it easier on the compiler
197 */
198# ifndef __ASSEMBLY__
199 typedef unsigned long pte_t;
200 typedef unsigned long pmd_t;
201 typedef unsigned long pgd_t;
202 typedef unsigned long pgprot_t;
203 typedef struct page *pgtable_t;
204# endif
205
206# define pte_val(x) (x)
207# define pmd_val(x) (x)
208# define pgd_val(x) (x)
209# define pgprot_val(x) (x)
210
211# define __pte(x) (x)
212# define __pgd(x) (x)
213# define __pgprot(x) (x)
214#endif /* !STRICT_MM_TYPECHECKS */
215
216#define PAGE_OFFSET RGN_BASE(RGN_KERNEL)
217
218#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | \
219 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC | \
220 (((current->personality & READ_IMPLIES_EXEC) != 0) \
221 ? VM_EXEC : 0))
222
223#endif /* _ASM_IA64_PAGE_H */
diff --git a/arch/ia64/include/asm/pal.h b/arch/ia64/include/asm/pal.h
new file mode 100644
index 000000000000..67b02901ead4
--- /dev/null
+++ b/arch/ia64/include/asm/pal.h
@@ -0,0 +1,1827 @@
1#ifndef _ASM_IA64_PAL_H
2#define _ASM_IA64_PAL_H
3
4/*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
17 *
18 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
19 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
20 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
21 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
22 * 00/05/25 eranian Support for stack calls, and static physical calls
23 * 00/06/18 eranian Support for stacked physical calls
24 * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
25 * Manual Rev 2.2 (Jan 2006)
26 */
27
28/*
29 * Note that some of these calls use a static-register only calling
30 * convention which has nothing to do with the regular calling
31 * convention.
32 */
33#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
34#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
35#define PAL_CACHE_INIT 3 /* initialize i/d cache */
36#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */
37#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
38#define PAL_PTCE_INFO 6 /* purge TLB info */
39#define PAL_VM_INFO 7 /* return supported virtual memory features */
40#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
41#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
42#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
43#define PAL_DEBUG_INFO 11 /* get number of debug registers */
44#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
45#define PAL_FREQ_BASE 13 /* base frequency of the platform */
46#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
47#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
48#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
49#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
50#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
51#define PAL_RSE_INFO 19 /* return rse information */
52#define PAL_VERSION 20 /* return version of PAL code */
53#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
54#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
55#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
56#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
57#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
58#define PAL_MC_RESUME 26 /* Return to interrupted process */
59#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
60#define PAL_HALT 28 /* enter the low power HALT state */
61#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
62#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
63#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
64#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
65#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
66#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
67
68#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
69#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
70#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
71#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
72#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
73#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
74#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
75#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
76#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
77#define PAL_VP_INFO 50 /* Information about virtual processor features */
78#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
79
80#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
81#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
82#define PAL_TEST_PROC 258 /* perform late processor self-test */
83#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
84#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
85#define PAL_VM_TR_READ 261 /* read contents of translation register */
86#define PAL_GET_PSTATE 262 /* get the current P-state */
87#define PAL_SET_PSTATE 263 /* set the P-state */
88#define PAL_BRAND_INFO 274 /* Processor branding information */
89
90#define PAL_GET_PSTATE_TYPE_LASTSET 0
91#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
92#define PAL_GET_PSTATE_TYPE_AVGNORESET 2
93#define PAL_GET_PSTATE_TYPE_INSTANT 3
94
95#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
96
97#ifndef __ASSEMBLY__
98
99#include <linux/types.h>
100#include <asm/fpu.h>
101
102/*
103 * Data types needed to pass information into PAL procedures and
104 * interpret information returned by them.
105 */
106
107/* Return status from the PAL procedure */
108typedef s64 pal_status_t;
109
110#define PAL_STATUS_SUCCESS 0 /* No error */
111#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
112#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
113#define PAL_STATUS_ERROR (-3) /* Error */
114#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
115 * specified level and type of
116 * cache without sideeffects
117 * and "restrict" was 1
118 */
119#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
120
121/* Processor cache level in the hierarchy */
122typedef u64 pal_cache_level_t;
123#define PAL_CACHE_LEVEL_L0 0 /* L0 */
124#define PAL_CACHE_LEVEL_L1 1 /* L1 */
125#define PAL_CACHE_LEVEL_L2 2 /* L2 */
126
127
128/* Processor cache type at a particular level in the hierarchy */
129
130typedef u64 pal_cache_type_t;
131#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
132#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
133#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
134
135
136#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
137#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
138
139/* Processor cache line size in bytes */
140typedef int pal_cache_line_size_t;
141
142/* Processor cache line state */
143typedef u64 pal_cache_line_state_t;
144#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
145#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
146#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
147#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
148
149typedef struct pal_freq_ratio {
150 u32 den, num; /* numerator & denominator */
151} itc_ratio, proc_ratio;
152
153typedef union pal_cache_config_info_1_s {
154 struct {
155 u64 u : 1, /* 0 Unified cache ? */
156 at : 2, /* 2-1 Cache mem attr*/
157 reserved : 5, /* 7-3 Reserved */
158 associativity : 8, /* 16-8 Associativity*/
159 line_size : 8, /* 23-17 Line size */
160 stride : 8, /* 31-24 Stride */
161 store_latency : 8, /*39-32 Store latency*/
162 load_latency : 8, /* 47-40 Load latency*/
163 store_hints : 8, /* 55-48 Store hints*/
164 load_hints : 8; /* 63-56 Load hints */
165 } pcci1_bits;
166 u64 pcci1_data;
167} pal_cache_config_info_1_t;
168
169typedef union pal_cache_config_info_2_s {
170 struct {
171 u32 cache_size; /*cache size in bytes*/
172
173
174 u32 alias_boundary : 8, /* 39-32 aliased addr
175 * separation for max
176 * performance.
177 */
178 tag_ls_bit : 8, /* 47-40 LSb of addr*/
179 tag_ms_bit : 8, /* 55-48 MSb of addr*/
180 reserved : 8; /* 63-56 Reserved */
181 } pcci2_bits;
182 u64 pcci2_data;
183} pal_cache_config_info_2_t;
184
185
186typedef struct pal_cache_config_info_s {
187 pal_status_t pcci_status;
188 pal_cache_config_info_1_t pcci_info_1;
189 pal_cache_config_info_2_t pcci_info_2;
190 u64 pcci_reserved;
191} pal_cache_config_info_t;
192
193#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
194#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
195#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
196#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
197#define pcci_stride pcci_info_1.pcci1_bits.stride
198#define pcci_line_size pcci_info_1.pcci1_bits.line_size
199#define pcci_assoc pcci_info_1.pcci1_bits.associativity
200#define pcci_cache_attr pcci_info_1.pcci1_bits.at
201#define pcci_unified pcci_info_1.pcci1_bits.u
202#define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
203#define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
204#define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
205#define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
206
207
208
209/* Possible values for cache attributes */
210
211#define PAL_CACHE_ATTR_WT 0 /* Write through cache */
212#define PAL_CACHE_ATTR_WB 1 /* Write back cache */
213#define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
214 * back depending on TLB
215 * memory attributes
216 */
217
218
219/* Possible values for cache hints */
220
221#define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
222#define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
223#define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
224
225/* Processor cache protection information */
226typedef union pal_cache_protection_element_u {
227 u32 pcpi_data;
228 struct {
229 u32 data_bits : 8, /* # data bits covered by
230 * each unit of protection
231 */
232
233 tagprot_lsb : 6, /* Least -do- */
234 tagprot_msb : 6, /* Most Sig. tag address
235 * bit that this
236 * protection covers.
237 */
238 prot_bits : 6, /* # of protection bits */
239 method : 4, /* Protection method */
240 t_d : 2; /* Indicates which part
241 * of the cache this
242 * protection encoding
243 * applies.
244 */
245 } pcp_info;
246} pal_cache_protection_element_t;
247
248#define pcpi_cache_prot_part pcp_info.t_d
249#define pcpi_prot_method pcp_info.method
250#define pcpi_prot_bits pcp_info.prot_bits
251#define pcpi_tagprot_msb pcp_info.tagprot_msb
252#define pcpi_tagprot_lsb pcp_info.tagprot_lsb
253#define pcpi_data_bits pcp_info.data_bits
254
255/* Processor cache part encodings */
256#define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
257#define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
258#define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
259 * more significant )
260 */
261#define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
262 * more significant )
263 */
264#define PAL_CACHE_PROT_PART_MAX 6
265
266
267typedef struct pal_cache_protection_info_s {
268 pal_status_t pcpi_status;
269 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
270} pal_cache_protection_info_t;
271
272
273/* Processor cache protection method encodings */
274#define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
275#define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
276#define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
277#define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
278
279
280/* Processor cache line identification in the hierarchy */
281typedef union pal_cache_line_id_u {
282 u64 pclid_data;
283 struct {
284 u64 cache_type : 8, /* 7-0 cache type */
285 level : 8, /* 15-8 level of the
286 * cache in the
287 * hierarchy.
288 */
289 way : 8, /* 23-16 way in the set
290 */
291 part : 8, /* 31-24 part of the
292 * cache
293 */
294 reserved : 32; /* 63-32 is reserved*/
295 } pclid_info_read;
296 struct {
297 u64 cache_type : 8, /* 7-0 cache type */
298 level : 8, /* 15-8 level of the
299 * cache in the
300 * hierarchy.
301 */
302 way : 8, /* 23-16 way in the set
303 */
304 part : 8, /* 31-24 part of the
305 * cache
306 */
307 mesi : 8, /* 39-32 cache line
308 * state
309 */
310 start : 8, /* 47-40 lsb of data to
311 * invert
312 */
313 length : 8, /* 55-48 #bits to
314 * invert
315 */
316 trigger : 8; /* 63-56 Trigger error
317 * by doing a load
318 * after the write
319 */
320
321 } pclid_info_write;
322} pal_cache_line_id_u_t;
323
324#define pclid_read_part pclid_info_read.part
325#define pclid_read_way pclid_info_read.way
326#define pclid_read_level pclid_info_read.level
327#define pclid_read_cache_type pclid_info_read.cache_type
328
329#define pclid_write_trigger pclid_info_write.trigger
330#define pclid_write_length pclid_info_write.length
331#define pclid_write_start pclid_info_write.start
332#define pclid_write_mesi pclid_info_write.mesi
333#define pclid_write_part pclid_info_write.part
334#define pclid_write_way pclid_info_write.way
335#define pclid_write_level pclid_info_write.level
336#define pclid_write_cache_type pclid_info_write.cache_type
337
338/* Processor cache line part encodings */
339#define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
340#define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
341#define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
342#define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
343#define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
344 * protection
345 */
346typedef struct pal_cache_line_info_s {
347 pal_status_t pcli_status; /* Return status of the read cache line
348 * info call.
349 */
350 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
351 u64 pcli_data_len; /* data length in bits */
352 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
353
354} pal_cache_line_info_t;
355
356
357/* Machine Check related crap */
358
359/* Pending event status bits */
360typedef u64 pal_mc_pending_events_t;
361
362#define PAL_MC_PENDING_MCA (1 << 0)
363#define PAL_MC_PENDING_INIT (1 << 1)
364
365/* Error information type */
366typedef u64 pal_mc_info_index_t;
367
368#define PAL_MC_INFO_PROCESSOR 0 /* Processor */
369#define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
370#define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
371#define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
372#define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
373#define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
374#define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
375#define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
376 * dependent
377 */
378
379#define PAL_TLB_CHECK_OP_PURGE 8
380
381typedef struct pal_process_state_info_s {
382 u64 reserved1 : 2,
383 rz : 1, /* PAL_CHECK processor
384 * rendezvous
385 * successful.
386 */
387
388 ra : 1, /* PAL_CHECK attempted
389 * a rendezvous.
390 */
391 me : 1, /* Distinct multiple
392 * errors occurred
393 */
394
395 mn : 1, /* Min. state save
396 * area has been
397 * registered with PAL
398 */
399
400 sy : 1, /* Storage integrity
401 * synched
402 */
403
404
405 co : 1, /* Continuable */
406 ci : 1, /* MC isolated */
407 us : 1, /* Uncontained storage
408 * damage.
409 */
410
411
412 hd : 1, /* Non-essential hw
413 * lost (no loss of
414 * functionality)
415 * causing the
416 * processor to run in
417 * degraded mode.
418 */
419
420 tl : 1, /* 1 => MC occurred
421 * after an instr was
422 * executed but before
423 * the trap that
424 * resulted from instr
425 * execution was
426 * generated.
427 * (Trap Lost )
428 */
429 mi : 1, /* More information available
430 * call PAL_MC_ERROR_INFO
431 */
432 pi : 1, /* Precise instruction pointer */
433 pm : 1, /* Precise min-state save area */
434
435 dy : 1, /* Processor dynamic
436 * state valid
437 */
438
439
440 in : 1, /* 0 = MC, 1 = INIT */
441 rs : 1, /* RSE valid */
442 cm : 1, /* MC corrected */
443 ex : 1, /* MC is expected */
444 cr : 1, /* Control regs valid*/
445 pc : 1, /* Perf cntrs valid */
446 dr : 1, /* Debug regs valid */
447 tr : 1, /* Translation regs
448 * valid
449 */
450 rr : 1, /* Region regs valid */
451 ar : 1, /* App regs valid */
452 br : 1, /* Branch regs valid */
453 pr : 1, /* Predicate registers
454 * valid
455 */
456
457 fp : 1, /* fp registers valid*/
458 b1 : 1, /* Preserved bank one
459 * general registers
460 * are valid
461 */
462 b0 : 1, /* Preserved bank zero
463 * general registers
464 * are valid
465 */
466 gr : 1, /* General registers
467 * are valid
468 * (excl. banked regs)
469 */
470 dsize : 16, /* size of dynamic
471 * state returned
472 * by the processor
473 */
474
475 se : 1, /* Shared error. MCA in a
476 shared structure */
477 reserved2 : 10,
478 cc : 1, /* Cache check */
479 tc : 1, /* TLB check */
480 bc : 1, /* Bus check */
481 rc : 1, /* Register file check */
482 uc : 1; /* Uarch check */
483
484} pal_processor_state_info_t;
485
486typedef struct pal_cache_check_info_s {
487 u64 op : 4, /* Type of cache
488 * operation that
489 * caused the machine
490 * check.
491 */
492 level : 2, /* Cache level */
493 reserved1 : 2,
494 dl : 1, /* Failure in data part
495 * of cache line
496 */
497 tl : 1, /* Failure in tag part
498 * of cache line
499 */
500 dc : 1, /* Failure in dcache */
501 ic : 1, /* Failure in icache */
502 mesi : 3, /* Cache line state */
503 mv : 1, /* mesi valid */
504 way : 5, /* Way in which the
505 * error occurred
506 */
507 wiv : 1, /* Way field valid */
508 reserved2 : 1,
509 dp : 1, /* Data poisoned on MBE */
510 reserved3 : 6,
511 hlth : 2, /* Health indicator */
512
513 index : 20, /* Cache line index */
514 reserved4 : 2,
515
516 is : 1, /* instruction set (1 == ia32) */
517 iv : 1, /* instruction set field valid */
518 pl : 2, /* privilege level */
519 pv : 1, /* privilege level field valid */
520 mcc : 1, /* Machine check corrected */
521 tv : 1, /* Target address
522 * structure is valid
523 */
524 rq : 1, /* Requester identifier
525 * structure is valid
526 */
527 rp : 1, /* Responder identifier
528 * structure is valid
529 */
530 pi : 1; /* Precise instruction pointer
531 * structure is valid
532 */
533} pal_cache_check_info_t;
534
535typedef struct pal_tlb_check_info_s {
536
537 u64 tr_slot : 8, /* Slot# of TR where
538 * error occurred
539 */
540 trv : 1, /* tr_slot field is valid */
541 reserved1 : 1,
542 level : 2, /* TLB level where failure occurred */
543 reserved2 : 4,
544 dtr : 1, /* Fail in data TR */
545 itr : 1, /* Fail in inst TR */
546 dtc : 1, /* Fail in data TC */
547 itc : 1, /* Fail in inst. TC */
548 op : 4, /* Cache operation */
549 reserved3 : 6,
550 hlth : 2, /* Health indicator */
551 reserved4 : 22,
552
553 is : 1, /* instruction set (1 == ia32) */
554 iv : 1, /* instruction set field valid */
555 pl : 2, /* privilege level */
556 pv : 1, /* privilege level field valid */
557 mcc : 1, /* Machine check corrected */
558 tv : 1, /* Target address
559 * structure is valid
560 */
561 rq : 1, /* Requester identifier
562 * structure is valid
563 */
564 rp : 1, /* Responder identifier
565 * structure is valid
566 */
567 pi : 1; /* Precise instruction pointer
568 * structure is valid
569 */
570} pal_tlb_check_info_t;
571
572typedef struct pal_bus_check_info_s {
573 u64 size : 5, /* Xaction size */
574 ib : 1, /* Internal bus error */
575 eb : 1, /* External bus error */
576 cc : 1, /* Error occurred
577 * during cache-cache
578 * transfer.
579 */
580 type : 8, /* Bus xaction type*/
581 sev : 5, /* Bus error severity*/
582 hier : 2, /* Bus hierarchy level */
583 dp : 1, /* Data poisoned on MBE */
584 bsi : 8, /* Bus error status
585 * info
586 */
587 reserved2 : 22,
588
589 is : 1, /* instruction set (1 == ia32) */
590 iv : 1, /* instruction set field valid */
591 pl : 2, /* privilege level */
592 pv : 1, /* privilege level field valid */
593 mcc : 1, /* Machine check corrected */
594 tv : 1, /* Target address
595 * structure is valid
596 */
597 rq : 1, /* Requester identifier
598 * structure is valid
599 */
600 rp : 1, /* Responder identifier
601 * structure is valid
602 */
603 pi : 1; /* Precise instruction pointer
604 * structure is valid
605 */
606} pal_bus_check_info_t;
607
608typedef struct pal_reg_file_check_info_s {
609 u64 id : 4, /* Register file identifier */
610 op : 4, /* Type of register
611 * operation that
612 * caused the machine
613 * check.
614 */
615 reg_num : 7, /* Register number */
616 rnv : 1, /* reg_num valid */
617 reserved2 : 38,
618
619 is : 1, /* instruction set (1 == ia32) */
620 iv : 1, /* instruction set field valid */
621 pl : 2, /* privilege level */
622 pv : 1, /* privilege level field valid */
623 mcc : 1, /* Machine check corrected */
624 reserved3 : 3,
625 pi : 1; /* Precise instruction pointer
626 * structure is valid
627 */
628} pal_reg_file_check_info_t;
629
630typedef struct pal_uarch_check_info_s {
631 u64 sid : 5, /* Structure identification */
632 level : 3, /* Level of failure */
633 array_id : 4, /* Array identification */
634 op : 4, /* Type of
635 * operation that
636 * caused the machine
637 * check.
638 */
639 way : 6, /* Way of structure */
640 wv : 1, /* way valid */
641 xv : 1, /* index valid */
642 reserved1 : 6,
643 hlth : 2, /* Health indicator */
644 index : 8, /* Index or set of the uarch
645 * structure that failed.
646 */
647 reserved2 : 24,
648
649 is : 1, /* instruction set (1 == ia32) */
650 iv : 1, /* instruction set field valid */
651 pl : 2, /* privilege level */
652 pv : 1, /* privilege level field valid */
653 mcc : 1, /* Machine check corrected */
654 tv : 1, /* Target address
655 * structure is valid
656 */
657 rq : 1, /* Requester identifier
658 * structure is valid
659 */
660 rp : 1, /* Responder identifier
661 * structure is valid
662 */
663 pi : 1; /* Precise instruction pointer
664 * structure is valid
665 */
666} pal_uarch_check_info_t;
667
668typedef union pal_mc_error_info_u {
669 u64 pmei_data;
670 pal_processor_state_info_t pme_processor;
671 pal_cache_check_info_t pme_cache;
672 pal_tlb_check_info_t pme_tlb;
673 pal_bus_check_info_t pme_bus;
674 pal_reg_file_check_info_t pme_reg_file;
675 pal_uarch_check_info_t pme_uarch;
676} pal_mc_error_info_t;
677
678#define pmci_proc_unknown_check pme_processor.uc
679#define pmci_proc_bus_check pme_processor.bc
680#define pmci_proc_tlb_check pme_processor.tc
681#define pmci_proc_cache_check pme_processor.cc
682#define pmci_proc_dynamic_state_size pme_processor.dsize
683#define pmci_proc_gpr_valid pme_processor.gr
684#define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
685#define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
686#define pmci_proc_fp_valid pme_processor.fp
687#define pmci_proc_predicate_regs_valid pme_processor.pr
688#define pmci_proc_branch_regs_valid pme_processor.br
689#define pmci_proc_app_regs_valid pme_processor.ar
690#define pmci_proc_region_regs_valid pme_processor.rr
691#define pmci_proc_translation_regs_valid pme_processor.tr
692#define pmci_proc_debug_regs_valid pme_processor.dr
693#define pmci_proc_perf_counters_valid pme_processor.pc
694#define pmci_proc_control_regs_valid pme_processor.cr
695#define pmci_proc_machine_check_expected pme_processor.ex
696#define pmci_proc_machine_check_corrected pme_processor.cm
697#define pmci_proc_rse_valid pme_processor.rs
698#define pmci_proc_machine_check_or_init pme_processor.in
699#define pmci_proc_dynamic_state_valid pme_processor.dy
700#define pmci_proc_operation pme_processor.op
701#define pmci_proc_trap_lost pme_processor.tl
702#define pmci_proc_hardware_damage pme_processor.hd
703#define pmci_proc_uncontained_storage_damage pme_processor.us
704#define pmci_proc_machine_check_isolated pme_processor.ci
705#define pmci_proc_continuable pme_processor.co
706#define pmci_proc_storage_intergrity_synced pme_processor.sy
707#define pmci_proc_min_state_save_area_regd pme_processor.mn
708#define pmci_proc_distinct_multiple_errors pme_processor.me
709#define pmci_proc_pal_attempted_rendezvous pme_processor.ra
710#define pmci_proc_pal_rendezvous_complete pme_processor.rz
711
712
713#define pmci_cache_level pme_cache.level
714#define pmci_cache_line_state pme_cache.mesi
715#define pmci_cache_line_state_valid pme_cache.mv
716#define pmci_cache_line_index pme_cache.index
717#define pmci_cache_instr_cache_fail pme_cache.ic
718#define pmci_cache_data_cache_fail pme_cache.dc
719#define pmci_cache_line_tag_fail pme_cache.tl
720#define pmci_cache_line_data_fail pme_cache.dl
721#define pmci_cache_operation pme_cache.op
722#define pmci_cache_way_valid pme_cache.wv
723#define pmci_cache_target_address_valid pme_cache.tv
724#define pmci_cache_way pme_cache.way
725#define pmci_cache_mc pme_cache.mc
726
727#define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
728#define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
729#define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
730#define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
731#define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
732#define pmci_tlb_mc pme_tlb.mc
733
734#define pmci_bus_status_info pme_bus.bsi
735#define pmci_bus_req_address_valid pme_bus.rq
736#define pmci_bus_resp_address_valid pme_bus.rp
737#define pmci_bus_target_address_valid pme_bus.tv
738#define pmci_bus_error_severity pme_bus.sev
739#define pmci_bus_transaction_type pme_bus.type
740#define pmci_bus_cache_cache_transfer pme_bus.cc
741#define pmci_bus_transaction_size pme_bus.size
742#define pmci_bus_internal_error pme_bus.ib
743#define pmci_bus_external_error pme_bus.eb
744#define pmci_bus_mc pme_bus.mc
745
746/*
747 * NOTE: this min_state_save area struct only includes the 1KB
748 * architectural state save area. The other 3 KB is scratch space
749 * for PAL.
750 */
751
752typedef struct pal_min_state_area_s {
753 u64 pmsa_nat_bits; /* nat bits for saved GRs */
754 u64 pmsa_gr[15]; /* GR1 - GR15 */
755 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
756 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
757 u64 pmsa_pr; /* predicate registers */
758 u64 pmsa_br0; /* branch register 0 */
759 u64 pmsa_rsc; /* ar.rsc */
760 u64 pmsa_iip; /* cr.iip */
761 u64 pmsa_ipsr; /* cr.ipsr */
762 u64 pmsa_ifs; /* cr.ifs */
763 u64 pmsa_xip; /* previous iip */
764 u64 pmsa_xpsr; /* previous psr */
765 u64 pmsa_xfs; /* previous ifs */
766 u64 pmsa_br1; /* branch register 1 */
767 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
768} pal_min_state_area_t;
769
770
771struct ia64_pal_retval {
772 /*
773 * A zero status value indicates call completed without error.
774 * A negative status value indicates reason of call failure.
775 * A positive status value indicates success but an
776 * informational value should be printed (e.g., "reboot for
777 * change to take effect").
778 */
779 s64 status;
780 u64 v0;
781 u64 v1;
782 u64 v2;
783};
784
785/*
786 * Note: Currently unused PAL arguments are generally labeled
787 * "reserved" so the value specified in the PAL documentation
788 * (generally 0) MUST be passed. Reserved parameters are not optional
789 * parameters.
790 */
791extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
792extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
793extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
794extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
795extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
796extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
797
798#define PAL_CALL(iprv,a0,a1,a2,a3) do { \
799 struct ia64_fpreg fr[6]; \
800 ia64_save_scratch_fpregs(fr); \
801 iprv = ia64_pal_call_static(a0, a1, a2, a3); \
802 ia64_load_scratch_fpregs(fr); \
803} while (0)
804
805#define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
806 struct ia64_fpreg fr[6]; \
807 ia64_save_scratch_fpregs(fr); \
808 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
809 ia64_load_scratch_fpregs(fr); \
810} while (0)
811
812#define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
813 struct ia64_fpreg fr[6]; \
814 ia64_save_scratch_fpregs(fr); \
815 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
816 ia64_load_scratch_fpregs(fr); \
817} while (0)
818
819#define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
820 struct ia64_fpreg fr[6]; \
821 ia64_save_scratch_fpregs(fr); \
822 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
823 ia64_load_scratch_fpregs(fr); \
824} while (0)
825
826typedef int (*ia64_pal_handler) (u64, ...);
827extern ia64_pal_handler ia64_pal;
828extern void ia64_pal_handler_init (void *);
829
830extern ia64_pal_handler ia64_pal;
831
832extern pal_cache_config_info_t l0d_cache_config_info;
833extern pal_cache_config_info_t l0i_cache_config_info;
834extern pal_cache_config_info_t l1_cache_config_info;
835extern pal_cache_config_info_t l2_cache_config_info;
836
837extern pal_cache_protection_info_t l0d_cache_protection_info;
838extern pal_cache_protection_info_t l0i_cache_protection_info;
839extern pal_cache_protection_info_t l1_cache_protection_info;
840extern pal_cache_protection_info_t l2_cache_protection_info;
841
842extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
843 pal_cache_type_t);
844
845extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
846 pal_cache_type_t);
847
848
849extern void pal_error(int);
850
851
852/* Useful wrappers for the current list of pal procedures */
853
854typedef union pal_bus_features_u {
855 u64 pal_bus_features_val;
856 struct {
857 u64 pbf_reserved1 : 29;
858 u64 pbf_req_bus_parking : 1;
859 u64 pbf_bus_lock_mask : 1;
860 u64 pbf_enable_half_xfer_rate : 1;
861 u64 pbf_reserved2 : 20;
862 u64 pbf_enable_shared_line_replace : 1;
863 u64 pbf_enable_exclusive_line_replace : 1;
864 u64 pbf_disable_xaction_queueing : 1;
865 u64 pbf_disable_resp_err_check : 1;
866 u64 pbf_disable_berr_check : 1;
867 u64 pbf_disable_bus_req_internal_err_signal : 1;
868 u64 pbf_disable_bus_req_berr_signal : 1;
869 u64 pbf_disable_bus_init_event_check : 1;
870 u64 pbf_disable_bus_init_event_signal : 1;
871 u64 pbf_disable_bus_addr_err_check : 1;
872 u64 pbf_disable_bus_addr_err_signal : 1;
873 u64 pbf_disable_bus_data_err_check : 1;
874 } pal_bus_features_s;
875} pal_bus_features_u_t;
876
877extern void pal_bus_features_print (u64);
878
879/* Provide information about configurable processor bus features */
880static inline s64
881ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
882 pal_bus_features_u_t *features_status,
883 pal_bus_features_u_t *features_control)
884{
885 struct ia64_pal_retval iprv;
886 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
887 if (features_avail)
888 features_avail->pal_bus_features_val = iprv.v0;
889 if (features_status)
890 features_status->pal_bus_features_val = iprv.v1;
891 if (features_control)
892 features_control->pal_bus_features_val = iprv.v2;
893 return iprv.status;
894}
895
896/* Enables/disables specific processor bus features */
897static inline s64
898ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
899{
900 struct ia64_pal_retval iprv;
901 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
902 return iprv.status;
903}
904
905/* Get detailed cache information */
906static inline s64
907ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
908{
909 struct ia64_pal_retval iprv;
910
911 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
912
913 if (iprv.status == 0) {
914 conf->pcci_status = iprv.status;
915 conf->pcci_info_1.pcci1_data = iprv.v0;
916 conf->pcci_info_2.pcci2_data = iprv.v1;
917 conf->pcci_reserved = iprv.v2;
918 }
919 return iprv.status;
920
921}
922
923/* Get detailed cche protection information */
924static inline s64
925ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
926{
927 struct ia64_pal_retval iprv;
928
929 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
930
931 if (iprv.status == 0) {
932 prot->pcpi_status = iprv.status;
933 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
934 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
935 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
936 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
937 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
938 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
939 }
940 return iprv.status;
941}
942
943/*
944 * Flush the processor instruction or data caches. *PROGRESS must be
945 * initialized to zero before calling this for the first time..
946 */
947static inline s64
948ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
949{
950 struct ia64_pal_retval iprv;
951 PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
952 if (vector)
953 *vector = iprv.v0;
954 *progress = iprv.v1;
955 return iprv.status;
956}
957
958
959/* Initialize the processor controlled caches */
960static inline s64
961ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
962{
963 struct ia64_pal_retval iprv;
964 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
965 return iprv.status;
966}
967
968/* Initialize the tags and data of a data or unified cache line of
969 * processor controlled cache to known values without the availability
970 * of backing memory.
971 */
972static inline s64
973ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
974{
975 struct ia64_pal_retval iprv;
976 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
977 return iprv.status;
978}
979
980
981/* Read the data and tag of a processor controlled cache line for diags */
982static inline s64
983ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
984{
985 struct ia64_pal_retval iprv;
986 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
987 physical_addr, 0);
988 return iprv.status;
989}
990
991/* Return summary information about the hierarchy of caches controlled by the processor */
992static inline s64
993ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
994{
995 struct ia64_pal_retval iprv;
996 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
997 if (cache_levels)
998 *cache_levels = iprv.v0;
999 if (unique_caches)
1000 *unique_caches = iprv.v1;
1001 return iprv.status;
1002}
1003
1004/* Write the data and tag of a processor-controlled cache line for diags */
1005static inline s64
1006ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
1007{
1008 struct ia64_pal_retval iprv;
1009 PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
1010 physical_addr, data);
1011 return iprv.status;
1012}
1013
1014
1015/* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
1016static inline s64
1017ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
1018 u64 *buffer_size, u64 *buffer_align)
1019{
1020 struct ia64_pal_retval iprv;
1021 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
1022 if (buffer_size)
1023 *buffer_size = iprv.v0;
1024 if (buffer_align)
1025 *buffer_align = iprv.v1;
1026 return iprv.status;
1027}
1028
1029/* Copy relocatable PAL procedures from ROM to memory */
1030static inline s64
1031ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1032{
1033 struct ia64_pal_retval iprv;
1034 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1035 if (pal_proc_offset)
1036 *pal_proc_offset = iprv.v0;
1037 return iprv.status;
1038}
1039
1040/* Return the number of instruction and data debug register pairs */
1041static inline s64
1042ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1043{
1044 struct ia64_pal_retval iprv;
1045 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1046 if (inst_regs)
1047 *inst_regs = iprv.v0;
1048 if (data_regs)
1049 *data_regs = iprv.v1;
1050
1051 return iprv.status;
1052}
1053
1054#ifdef TBD
1055/* Switch from IA64-system environment to IA-32 system environment */
1056static inline s64
1057ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1058{
1059 struct ia64_pal_retval iprv;
1060 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1061 return iprv.status;
1062}
1063#endif
1064
1065/* Get unique geographical address of this processor on its bus */
1066static inline s64
1067ia64_pal_fixed_addr (u64 *global_unique_addr)
1068{
1069 struct ia64_pal_retval iprv;
1070 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1071 if (global_unique_addr)
1072 *global_unique_addr = iprv.v0;
1073 return iprv.status;
1074}
1075
1076/* Get base frequency of the platform if generated by the processor */
1077static inline s64
1078ia64_pal_freq_base (u64 *platform_base_freq)
1079{
1080 struct ia64_pal_retval iprv;
1081 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1082 if (platform_base_freq)
1083 *platform_base_freq = iprv.v0;
1084 return iprv.status;
1085}
1086
1087/*
1088 * Get the ratios for processor frequency, bus frequency and interval timer to
1089 * to base frequency of the platform
1090 */
1091static inline s64
1092ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1093 struct pal_freq_ratio *itc_ratio)
1094{
1095 struct ia64_pal_retval iprv;
1096 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1097 if (proc_ratio)
1098 *(u64 *)proc_ratio = iprv.v0;
1099 if (bus_ratio)
1100 *(u64 *)bus_ratio = iprv.v1;
1101 if (itc_ratio)
1102 *(u64 *)itc_ratio = iprv.v2;
1103 return iprv.status;
1104}
1105
1106/*
1107 * Get the current hardware resource sharing policy of the processor
1108 */
1109static inline s64
1110ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
1111 u64 *la)
1112{
1113 struct ia64_pal_retval iprv;
1114 PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
1115 if (cur_policy)
1116 *cur_policy = iprv.v0;
1117 if (num_impacted)
1118 *num_impacted = iprv.v1;
1119 if (la)
1120 *la = iprv.v2;
1121 return iprv.status;
1122}
1123
1124/* Make the processor enter HALT or one of the implementation dependent low
1125 * power states where prefetching and execution are suspended and cache and
1126 * TLB coherency is not maintained.
1127 */
1128static inline s64
1129ia64_pal_halt (u64 halt_state)
1130{
1131 struct ia64_pal_retval iprv;
1132 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1133 return iprv.status;
1134}
1135
1136typedef union pal_power_mgmt_info_u {
1137 u64 ppmi_data;
1138 struct {
1139 u64 exit_latency : 16,
1140 entry_latency : 16,
1141 power_consumption : 28,
1142 im : 1,
1143 co : 1,
1144 reserved : 2;
1145 } pal_power_mgmt_info_s;
1146} pal_power_mgmt_info_u_t;
1147
1148/* Return information about processor's optional power management capabilities. */
1149static inline s64
1150ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1151{
1152 struct ia64_pal_retval iprv;
1153 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1154 return iprv.status;
1155}
1156
1157/* Get the current P-state information */
1158static inline s64
1159ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
1160{
1161 struct ia64_pal_retval iprv;
1162 PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
1163 *pstate_index = iprv.v0;
1164 return iprv.status;
1165}
1166
1167/* Set the P-state */
1168static inline s64
1169ia64_pal_set_pstate (u64 pstate_index)
1170{
1171 struct ia64_pal_retval iprv;
1172 PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
1173 return iprv.status;
1174}
1175
1176/* Processor branding information*/
1177static inline s64
1178ia64_pal_get_brand_info (char *brand_info)
1179{
1180 struct ia64_pal_retval iprv;
1181 PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
1182 return iprv.status;
1183}
1184
1185/* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1186 * suspended, but cache and TLB coherency is maintained.
1187 */
1188static inline s64
1189ia64_pal_halt_light (void)
1190{
1191 struct ia64_pal_retval iprv;
1192 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1193 return iprv.status;
1194}
1195
1196/* Clear all the processor error logging registers and reset the indicator that allows
1197 * the error logging registers to be written. This procedure also checks the pending
1198 * machine check bit and pending INIT bit and reports their states.
1199 */
1200static inline s64
1201ia64_pal_mc_clear_log (u64 *pending_vector)
1202{
1203 struct ia64_pal_retval iprv;
1204 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1205 if (pending_vector)
1206 *pending_vector = iprv.v0;
1207 return iprv.status;
1208}
1209
1210/* Ensure that all outstanding transactions in a processor are completed or that any
1211 * MCA due to thes outstanding transaction is taken.
1212 */
1213static inline s64
1214ia64_pal_mc_drain (void)
1215{
1216 struct ia64_pal_retval iprv;
1217 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1218 return iprv.status;
1219}
1220
1221/* Return the machine check dynamic processor state */
1222static inline s64
1223ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
1224{
1225 struct ia64_pal_retval iprv;
1226 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
1227 if (size)
1228 *size = iprv.v0;
1229 return iprv.status;
1230}
1231
1232/* Return processor machine check information */
1233static inline s64
1234ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1235{
1236 struct ia64_pal_retval iprv;
1237 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1238 if (size)
1239 *size = iprv.v0;
1240 if (error_info)
1241 *error_info = iprv.v1;
1242 return iprv.status;
1243}
1244
1245/* Injects the requested processor error or returns info on
1246 * supported injection capabilities for current processor implementation
1247 */
1248static inline s64
1249ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
1250 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1251{
1252 struct ia64_pal_retval iprv;
1253 PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1254 err_struct_info, err_data_buffer);
1255 if (capabilities)
1256 *capabilities= iprv.v0;
1257 if (resources)
1258 *resources= iprv.v1;
1259 return iprv.status;
1260}
1261
1262static inline s64
1263ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
1264 u64 err_data_buffer, u64 *capabilities, u64 *resources)
1265{
1266 struct ia64_pal_retval iprv;
1267 PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
1268 err_struct_info, err_data_buffer);
1269 if (capabilities)
1270 *capabilities= iprv.v0;
1271 if (resources)
1272 *resources= iprv.v1;
1273 return iprv.status;
1274}
1275
1276/* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1277 * attempt to correct any expected machine checks.
1278 */
1279static inline s64
1280ia64_pal_mc_expected (u64 expected, u64 *previous)
1281{
1282 struct ia64_pal_retval iprv;
1283 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1284 if (previous)
1285 *previous = iprv.v0;
1286 return iprv.status;
1287}
1288
1289typedef union pal_hw_tracking_u {
1290 u64 pht_data;
1291 struct {
1292 u64 itc :4, /* Instruction cache tracking */
1293 dct :4, /* Date cache tracking */
1294 itt :4, /* Instruction TLB tracking */
1295 ddt :4, /* Data TLB tracking */
1296 reserved:48;
1297 } pal_hw_tracking_s;
1298} pal_hw_tracking_u_t;
1299
1300/*
1301 * Hardware tracking status.
1302 */
1303static inline s64
1304ia64_pal_mc_hw_tracking (u64 *status)
1305{
1306 struct ia64_pal_retval iprv;
1307 PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
1308 if (status)
1309 *status = iprv.v0;
1310 return iprv.status;
1311}
1312
1313/* Register a platform dependent location with PAL to which it can save
1314 * minimal processor state in the event of a machine check or initialization
1315 * event.
1316 */
1317static inline s64
1318ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
1319{
1320 struct ia64_pal_retval iprv;
1321 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
1322 if (req_size)
1323 *req_size = iprv.v0;
1324 return iprv.status;
1325}
1326
1327/* Restore minimal architectural processor state, set CMC interrupt if necessary
1328 * and resume execution
1329 */
1330static inline s64
1331ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1332{
1333 struct ia64_pal_retval iprv;
1334 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1335 return iprv.status;
1336}
1337
1338/* Return the memory attributes implemented by the processor */
1339static inline s64
1340ia64_pal_mem_attrib (u64 *mem_attrib)
1341{
1342 struct ia64_pal_retval iprv;
1343 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1344 if (mem_attrib)
1345 *mem_attrib = iprv.v0 & 0xff;
1346 return iprv.status;
1347}
1348
1349/* Return the amount of memory needed for second phase of processor
1350 * self-test and the required alignment of memory.
1351 */
1352static inline s64
1353ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1354{
1355 struct ia64_pal_retval iprv;
1356 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1357 if (bytes_needed)
1358 *bytes_needed = iprv.v0;
1359 if (alignment)
1360 *alignment = iprv.v1;
1361 return iprv.status;
1362}
1363
1364typedef union pal_perf_mon_info_u {
1365 u64 ppmi_data;
1366 struct {
1367 u64 generic : 8,
1368 width : 8,
1369 cycles : 8,
1370 retired : 8,
1371 reserved : 32;
1372 } pal_perf_mon_info_s;
1373} pal_perf_mon_info_u_t;
1374
1375/* Return the performance monitor information about what can be counted
1376 * and how to configure the monitors to count the desired events.
1377 */
1378static inline s64
1379ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1380{
1381 struct ia64_pal_retval iprv;
1382 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1383 if (pm_info)
1384 pm_info->ppmi_data = iprv.v0;
1385 return iprv.status;
1386}
1387
1388/* Specifies the physical address of the processor interrupt block
1389 * and I/O port space.
1390 */
1391static inline s64
1392ia64_pal_platform_addr (u64 type, u64 physical_addr)
1393{
1394 struct ia64_pal_retval iprv;
1395 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1396 return iprv.status;
1397}
1398
1399/* Set the SAL PMI entrypoint in memory */
1400static inline s64
1401ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1402{
1403 struct ia64_pal_retval iprv;
1404 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1405 return iprv.status;
1406}
1407
1408struct pal_features_s;
1409/* Provide information about configurable processor features */
1410static inline s64
1411ia64_pal_proc_get_features (u64 *features_avail,
1412 u64 *features_status,
1413 u64 *features_control,
1414 u64 features_set)
1415{
1416 struct ia64_pal_retval iprv;
1417 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
1418 if (iprv.status == 0) {
1419 *features_avail = iprv.v0;
1420 *features_status = iprv.v1;
1421 *features_control = iprv.v2;
1422 }
1423 return iprv.status;
1424}
1425
1426/* Enable/disable processor dependent features */
1427static inline s64
1428ia64_pal_proc_set_features (u64 feature_select)
1429{
1430 struct ia64_pal_retval iprv;
1431 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1432 return iprv.status;
1433}
1434
1435/*
1436 * Put everything in a struct so we avoid the global offset table whenever
1437 * possible.
1438 */
1439typedef struct ia64_ptce_info_s {
1440 u64 base;
1441 u32 count[2];
1442 u32 stride[2];
1443} ia64_ptce_info_t;
1444
1445/* Return the information required for the architected loop used to purge
1446 * (initialize) the entire TC
1447 */
1448static inline s64
1449ia64_get_ptce (ia64_ptce_info_t *ptce)
1450{
1451 struct ia64_pal_retval iprv;
1452
1453 if (!ptce)
1454 return -1;
1455
1456 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1457 if (iprv.status == 0) {
1458 ptce->base = iprv.v0;
1459 ptce->count[0] = iprv.v1 >> 32;
1460 ptce->count[1] = iprv.v1 & 0xffffffff;
1461 ptce->stride[0] = iprv.v2 >> 32;
1462 ptce->stride[1] = iprv.v2 & 0xffffffff;
1463 }
1464 return iprv.status;
1465}
1466
1467/* Return info about implemented application and control registers. */
1468static inline s64
1469ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1470{
1471 struct ia64_pal_retval iprv;
1472 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1473 if (reg_info_1)
1474 *reg_info_1 = iprv.v0;
1475 if (reg_info_2)
1476 *reg_info_2 = iprv.v1;
1477 return iprv.status;
1478}
1479
1480typedef union pal_hints_u {
1481 u64 ph_data;
1482 struct {
1483 u64 si : 1,
1484 li : 1,
1485 reserved : 62;
1486 } pal_hints_s;
1487} pal_hints_u_t;
1488
1489/* Return information about the register stack and RSE for this processor
1490 * implementation.
1491 */
1492static inline s64
1493ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1494{
1495 struct ia64_pal_retval iprv;
1496 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1497 if (num_phys_stacked)
1498 *num_phys_stacked = iprv.v0;
1499 if (hints)
1500 hints->ph_data = iprv.v1;
1501 return iprv.status;
1502}
1503
1504/*
1505 * Set the current hardware resource sharing policy of the processor
1506 */
1507static inline s64
1508ia64_pal_set_hw_policy (u64 policy)
1509{
1510 struct ia64_pal_retval iprv;
1511 PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
1512 return iprv.status;
1513}
1514
1515/* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1516 * suspended, but cause cache and TLB coherency to be maintained.
1517 * This is usually called in IA-32 mode.
1518 */
1519static inline s64
1520ia64_pal_shutdown (void)
1521{
1522 struct ia64_pal_retval iprv;
1523 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1524 return iprv.status;
1525}
1526
1527/* Perform the second phase of processor self-test. */
1528static inline s64
1529ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1530{
1531 struct ia64_pal_retval iprv;
1532 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1533 if (self_test_state)
1534 *self_test_state = iprv.v0;
1535 return iprv.status;
1536}
1537
1538typedef union pal_version_u {
1539 u64 pal_version_val;
1540 struct {
1541 u64 pv_pal_b_rev : 8;
1542 u64 pv_pal_b_model : 8;
1543 u64 pv_reserved1 : 8;
1544 u64 pv_pal_vendor : 8;
1545 u64 pv_pal_a_rev : 8;
1546 u64 pv_pal_a_model : 8;
1547 u64 pv_reserved2 : 16;
1548 } pal_version_s;
1549} pal_version_u_t;
1550
1551
1552/*
1553 * Return PAL version information. While the documentation states that
1554 * PAL_VERSION can be called in either physical or virtual mode, some
1555 * implementations only allow physical calls. We don't call it very often,
1556 * so the overhead isn't worth eliminating.
1557 */
1558static inline s64
1559ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1560{
1561 struct ia64_pal_retval iprv;
1562 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1563 if (pal_min_version)
1564 pal_min_version->pal_version_val = iprv.v0;
1565
1566 if (pal_cur_version)
1567 pal_cur_version->pal_version_val = iprv.v1;
1568
1569 return iprv.status;
1570}
1571
1572typedef union pal_tc_info_u {
1573 u64 pti_val;
1574 struct {
1575 u64 num_sets : 8,
1576 associativity : 8,
1577 num_entries : 16,
1578 pf : 1,
1579 unified : 1,
1580 reduce_tr : 1,
1581 reserved : 29;
1582 } pal_tc_info_s;
1583} pal_tc_info_u_t;
1584
1585#define tc_reduce_tr pal_tc_info_s.reduce_tr
1586#define tc_unified pal_tc_info_s.unified
1587#define tc_pf pal_tc_info_s.pf
1588#define tc_num_entries pal_tc_info_s.num_entries
1589#define tc_associativity pal_tc_info_s.associativity
1590#define tc_num_sets pal_tc_info_s.num_sets
1591
1592
1593/* Return information about the virtual memory characteristics of the processor
1594 * implementation.
1595 */
1596static inline s64
1597ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1598{
1599 struct ia64_pal_retval iprv;
1600 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1601 if (tc_info)
1602 tc_info->pti_val = iprv.v0;
1603 if (tc_pages)
1604 *tc_pages = iprv.v1;
1605 return iprv.status;
1606}
1607
1608/* Get page size information about the virtual memory characteristics of the processor
1609 * implementation.
1610 */
1611static inline s64
1612ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1613{
1614 struct ia64_pal_retval iprv;
1615 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1616 if (tr_pages)
1617 *tr_pages = iprv.v0;
1618 if (vw_pages)
1619 *vw_pages = iprv.v1;
1620 return iprv.status;
1621}
1622
1623typedef union pal_vm_info_1_u {
1624 u64 pvi1_val;
1625 struct {
1626 u64 vw : 1,
1627 phys_add_size : 7,
1628 key_size : 8,
1629 max_pkr : 8,
1630 hash_tag_id : 8,
1631 max_dtr_entry : 8,
1632 max_itr_entry : 8,
1633 max_unique_tcs : 8,
1634 num_tc_levels : 8;
1635 } pal_vm_info_1_s;
1636} pal_vm_info_1_u_t;
1637
1638#define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */
1639
1640typedef union pal_vm_info_2_u {
1641 u64 pvi2_val;
1642 struct {
1643 u64 impl_va_msb : 8,
1644 rid_size : 8,
1645 max_purges : 16,
1646 reserved : 32;
1647 } pal_vm_info_2_s;
1648} pal_vm_info_2_u_t;
1649
1650/* Get summary information about the virtual memory characteristics of the processor
1651 * implementation.
1652 */
1653static inline s64
1654ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1655{
1656 struct ia64_pal_retval iprv;
1657 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1658 if (vm_info_1)
1659 vm_info_1->pvi1_val = iprv.v0;
1660 if (vm_info_2)
1661 vm_info_2->pvi2_val = iprv.v1;
1662 return iprv.status;
1663}
1664
1665typedef union pal_vp_info_u {
1666 u64 pvi_val;
1667 struct {
1668 u64 index: 48, /* virtual feature set info */
1669 vmm_id: 16; /* feature set id */
1670 } pal_vp_info_s;
1671} pal_vp_info_u_t;
1672
1673/*
1674 * Returns infomation about virtual processor features
1675 */
1676static inline s64
1677ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
1678{
1679 struct ia64_pal_retval iprv;
1680 PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
1681 if (vp_info)
1682 *vp_info = iprv.v0;
1683 if (vmm_id)
1684 *vmm_id = iprv.v1;
1685 return iprv.status;
1686}
1687
1688typedef union pal_itr_valid_u {
1689 u64 piv_val;
1690 struct {
1691 u64 access_rights_valid : 1,
1692 priv_level_valid : 1,
1693 dirty_bit_valid : 1,
1694 mem_attr_valid : 1,
1695 reserved : 60;
1696 } pal_tr_valid_s;
1697} pal_tr_valid_u_t;
1698
1699/* Read a translation register */
1700static inline s64
1701ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1702{
1703 struct ia64_pal_retval iprv;
1704 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1705 if (tr_valid)
1706 tr_valid->piv_val = iprv.v0;
1707 return iprv.status;
1708}
1709
1710/*
1711 * PAL_PREFETCH_VISIBILITY transaction types
1712 */
1713#define PAL_VISIBILITY_VIRTUAL 0
1714#define PAL_VISIBILITY_PHYSICAL 1
1715
1716/*
1717 * PAL_PREFETCH_VISIBILITY return codes
1718 */
1719#define PAL_VISIBILITY_OK 1
1720#define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1721#define PAL_VISIBILITY_INVAL_ARG -2
1722#define PAL_VISIBILITY_ERROR -3
1723
1724static inline s64
1725ia64_pal_prefetch_visibility (s64 trans_type)
1726{
1727 struct ia64_pal_retval iprv;
1728 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1729 return iprv.status;
1730}
1731
1732/* data structure for getting information on logical to physical mappings */
1733typedef union pal_log_overview_u {
1734 struct {
1735 u64 num_log :16, /* Total number of logical
1736 * processors on this die
1737 */
1738 tpc :8, /* Threads per core */
1739 reserved3 :8, /* Reserved */
1740 cpp :8, /* Cores per processor */
1741 reserved2 :8, /* Reserved */
1742 ppid :8, /* Physical processor ID */
1743 reserved1 :8; /* Reserved */
1744 } overview_bits;
1745 u64 overview_data;
1746} pal_log_overview_t;
1747
1748typedef union pal_proc_n_log_info1_u{
1749 struct {
1750 u64 tid :16, /* Thread id */
1751 reserved2 :16, /* Reserved */
1752 cid :16, /* Core id */
1753 reserved1 :16; /* Reserved */
1754 } ppli1_bits;
1755 u64 ppli1_data;
1756} pal_proc_n_log_info1_t;
1757
1758typedef union pal_proc_n_log_info2_u {
1759 struct {
1760 u64 la :16, /* Logical address */
1761 reserved :48; /* Reserved */
1762 } ppli2_bits;
1763 u64 ppli2_data;
1764} pal_proc_n_log_info2_t;
1765
1766typedef struct pal_logical_to_physical_s
1767{
1768 pal_log_overview_t overview;
1769 pal_proc_n_log_info1_t ppli1;
1770 pal_proc_n_log_info2_t ppli2;
1771} pal_logical_to_physical_t;
1772
1773#define overview_num_log overview.overview_bits.num_log
1774#define overview_tpc overview.overview_bits.tpc
1775#define overview_cpp overview.overview_bits.cpp
1776#define overview_ppid overview.overview_bits.ppid
1777#define log1_tid ppli1.ppli1_bits.tid
1778#define log1_cid ppli1.ppli1_bits.cid
1779#define log2_la ppli2.ppli2_bits.la
1780
1781/* Get information on logical to physical processor mappings. */
1782static inline s64
1783ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1784{
1785 struct ia64_pal_retval iprv;
1786
1787 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1788
1789 if (iprv.status == PAL_STATUS_SUCCESS)
1790 {
1791 mapping->overview.overview_data = iprv.v0;
1792 mapping->ppli1.ppli1_data = iprv.v1;
1793 mapping->ppli2.ppli2_data = iprv.v2;
1794 }
1795
1796 return iprv.status;
1797}
1798
1799typedef struct pal_cache_shared_info_s
1800{
1801 u64 num_shared;
1802 pal_proc_n_log_info1_t ppli1;
1803 pal_proc_n_log_info2_t ppli2;
1804} pal_cache_shared_info_t;
1805
1806/* Get information on logical to physical processor mappings. */
1807static inline s64
1808ia64_pal_cache_shared_info(u64 level,
1809 u64 type,
1810 u64 proc_number,
1811 pal_cache_shared_info_t *info)
1812{
1813 struct ia64_pal_retval iprv;
1814
1815 PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
1816
1817 if (iprv.status == PAL_STATUS_SUCCESS) {
1818 info->num_shared = iprv.v0;
1819 info->ppli1.ppli1_data = iprv.v1;
1820 info->ppli2.ppli2_data = iprv.v2;
1821 }
1822
1823 return iprv.status;
1824}
1825#endif /* __ASSEMBLY__ */
1826
1827#endif /* _ASM_IA64_PAL_H */
diff --git a/arch/ia64/include/asm/param.h b/arch/ia64/include/asm/param.h
new file mode 100644
index 000000000000..0964c32c1358
--- /dev/null
+++ b/arch/ia64/include/asm/param.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_IA64_PARAM_H
2#define _ASM_IA64_PARAM_H
3
4/*
5 * Fundamental kernel parameters.
6 *
7 * Based on <asm-i386/param.h>.
8 *
9 * Modified 1998, 1999, 2002-2003
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12
13#define EXEC_PAGESIZE 65536
14
15#ifndef NOGROUP
16# define NOGROUP (-1)
17#endif
18
19#define MAXHOSTNAMELEN 64 /* max length of hostname */
20
21#ifdef __KERNEL__
22# define HZ CONFIG_HZ
23# define USER_HZ HZ
24# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */
25#else
26 /*
27 * Technically, this is wrong, but some old apps still refer to it. The proper way to
28 * get the HZ value is via sysconf(_SC_CLK_TCK).
29 */
30# define HZ 1024
31#endif
32
33#endif /* _ASM_IA64_PARAM_H */
diff --git a/arch/ia64/include/asm/paravirt.h b/arch/ia64/include/asm/paravirt.h
new file mode 100644
index 000000000000..660cab044834
--- /dev/null
+++ b/arch/ia64/include/asm/paravirt.h
@@ -0,0 +1,253 @@
1/******************************************************************************
2 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
3 * VA Linux Systems Japan K.K.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21
22#ifndef __ASM_PARAVIRT_H
23#define __ASM_PARAVIRT_H
24
25#ifdef CONFIG_PARAVIRT_GUEST
26
27#define PARAVIRT_HYPERVISOR_TYPE_DEFAULT 0
28#define PARAVIRT_HYPERVISOR_TYPE_XEN 1
29
30#ifndef __ASSEMBLY__
31
32#include <asm/hw_irq.h>
33#include <asm/meminit.h>
34
35/******************************************************************************
36 * general info
37 */
38struct pv_info {
39 unsigned int kernel_rpl;
40 int paravirt_enabled;
41 const char *name;
42};
43
44extern struct pv_info pv_info;
45
46static inline int paravirt_enabled(void)
47{
48 return pv_info.paravirt_enabled;
49}
50
51static inline unsigned int get_kernel_rpl(void)
52{
53 return pv_info.kernel_rpl;
54}
55
56/******************************************************************************
57 * initialization hooks.
58 */
59struct rsvd_region;
60
61struct pv_init_ops {
62 void (*banner)(void);
63
64 int (*reserve_memory)(struct rsvd_region *region);
65
66 void (*arch_setup_early)(void);
67 void (*arch_setup_console)(char **cmdline_p);
68 int (*arch_setup_nomca)(void);
69
70 void (*post_smp_prepare_boot_cpu)(void);
71};
72
73extern struct pv_init_ops pv_init_ops;
74
75static inline void paravirt_banner(void)
76{
77 if (pv_init_ops.banner)
78 pv_init_ops.banner();
79}
80
81static inline int paravirt_reserve_memory(struct rsvd_region *region)
82{
83 if (pv_init_ops.reserve_memory)
84 return pv_init_ops.reserve_memory(region);
85 return 0;
86}
87
88static inline void paravirt_arch_setup_early(void)
89{
90 if (pv_init_ops.arch_setup_early)
91 pv_init_ops.arch_setup_early();
92}
93
94static inline void paravirt_arch_setup_console(char **cmdline_p)
95{
96 if (pv_init_ops.arch_setup_console)
97 pv_init_ops.arch_setup_console(cmdline_p);
98}
99
100static inline int paravirt_arch_setup_nomca(void)
101{
102 if (pv_init_ops.arch_setup_nomca)
103 return pv_init_ops.arch_setup_nomca();
104 return 0;
105}
106
107static inline void paravirt_post_smp_prepare_boot_cpu(void)
108{
109 if (pv_init_ops.post_smp_prepare_boot_cpu)
110 pv_init_ops.post_smp_prepare_boot_cpu();
111}
112
113/******************************************************************************
114 * replacement of iosapic operations.
115 */
116
117struct pv_iosapic_ops {
118 void (*pcat_compat_init)(void);
119
120 struct irq_chip *(*get_irq_chip)(unsigned long trigger);
121
122 unsigned int (*__read)(char __iomem *iosapic, unsigned int reg);
123 void (*__write)(char __iomem *iosapic, unsigned int reg, u32 val);
124};
125
126extern struct pv_iosapic_ops pv_iosapic_ops;
127
128static inline void
129iosapic_pcat_compat_init(void)
130{
131 if (pv_iosapic_ops.pcat_compat_init)
132 pv_iosapic_ops.pcat_compat_init();
133}
134
135static inline struct irq_chip*
136iosapic_get_irq_chip(unsigned long trigger)
137{
138 return pv_iosapic_ops.get_irq_chip(trigger);
139}
140
141static inline unsigned int
142__iosapic_read(char __iomem *iosapic, unsigned int reg)
143{
144 return pv_iosapic_ops.__read(iosapic, reg);
145}
146
147static inline void
148__iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
149{
150 return pv_iosapic_ops.__write(iosapic, reg, val);
151}
152
153/******************************************************************************
154 * replacement of irq operations.
155 */
156
157struct pv_irq_ops {
158 void (*register_ipi)(void);
159
160 int (*assign_irq_vector)(int irq);
161 void (*free_irq_vector)(int vector);
162
163 void (*register_percpu_irq)(ia64_vector vec,
164 struct irqaction *action);
165
166 void (*resend_irq)(unsigned int vector);
167};
168
169extern struct pv_irq_ops pv_irq_ops;
170
171static inline void
172ia64_register_ipi(void)
173{
174 pv_irq_ops.register_ipi();
175}
176
177static inline int
178assign_irq_vector(int irq)
179{
180 return pv_irq_ops.assign_irq_vector(irq);
181}
182
183static inline void
184free_irq_vector(int vector)
185{
186 return pv_irq_ops.free_irq_vector(vector);
187}
188
189static inline void
190register_percpu_irq(ia64_vector vec, struct irqaction *action)
191{
192 pv_irq_ops.register_percpu_irq(vec, action);
193}
194
195static inline void
196ia64_resend_irq(unsigned int vector)
197{
198 pv_irq_ops.resend_irq(vector);
199}
200
201/******************************************************************************
202 * replacement of time operations.
203 */
204
205extern struct itc_jitter_data_t itc_jitter_data;
206extern volatile int time_keeper_id;
207
208struct pv_time_ops {
209 void (*init_missing_ticks_accounting)(int cpu);
210 int (*do_steal_accounting)(unsigned long *new_itm);
211
212 void (*clocksource_resume)(void);
213};
214
215extern struct pv_time_ops pv_time_ops;
216
217static inline void
218paravirt_init_missing_ticks_accounting(int cpu)
219{
220 if (pv_time_ops.init_missing_ticks_accounting)
221 pv_time_ops.init_missing_ticks_accounting(cpu);
222}
223
224static inline int
225paravirt_do_steal_accounting(unsigned long *new_itm)
226{
227 return pv_time_ops.do_steal_accounting(new_itm);
228}
229
230#endif /* !__ASSEMBLY__ */
231
232#else
233/* fallback for native case */
234
235#ifndef __ASSEMBLY__
236
237#define paravirt_banner() do { } while (0)
238#define paravirt_reserve_memory(region) 0
239
240#define paravirt_arch_setup_early() do { } while (0)
241#define paravirt_arch_setup_console(cmdline_p) do { } while (0)
242#define paravirt_arch_setup_nomca() 0
243#define paravirt_post_smp_prepare_boot_cpu() do { } while (0)
244
245#define paravirt_init_missing_ticks_accounting(cpu) do { } while (0)
246#define paravirt_do_steal_accounting(new_itm) 0
247
248#endif /* __ASSEMBLY__ */
249
250
251#endif /* CONFIG_PARAVIRT_GUEST */
252
253#endif /* __ASM_PARAVIRT_H */
diff --git a/arch/ia64/include/asm/paravirt_privop.h b/arch/ia64/include/asm/paravirt_privop.h
new file mode 100644
index 000000000000..d577aac11835
--- /dev/null
+++ b/arch/ia64/include/asm/paravirt_privop.h
@@ -0,0 +1,112 @@
1/******************************************************************************
2 * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
3 * VA Linux Systems Japan K.K.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#ifndef _ASM_IA64_PARAVIRT_PRIVOP_H
22#define _ASM_IA64_PARAVIRT_PRIVOP_H
23
24#ifdef CONFIG_PARAVIRT
25
26#ifndef __ASSEMBLY__
27
28#include <linux/types.h>
29#include <asm/kregs.h> /* for IA64_PSR_I */
30
31/******************************************************************************
32 * replacement of intrinsics operations.
33 */
34
35struct pv_cpu_ops {
36 void (*fc)(unsigned long addr);
37 unsigned long (*thash)(unsigned long addr);
38 unsigned long (*get_cpuid)(int index);
39 unsigned long (*get_pmd)(int index);
40 unsigned long (*getreg)(int reg);
41 void (*setreg)(int reg, unsigned long val);
42 void (*ptcga)(unsigned long addr, unsigned long size);
43 unsigned long (*get_rr)(unsigned long index);
44 void (*set_rr)(unsigned long index, unsigned long val);
45 void (*set_rr0_to_rr4)(unsigned long val0, unsigned long val1,
46 unsigned long val2, unsigned long val3,
47 unsigned long val4);
48 void (*ssm_i)(void);
49 void (*rsm_i)(void);
50 unsigned long (*get_psr_i)(void);
51 void (*intrin_local_irq_restore)(unsigned long flags);
52};
53
54extern struct pv_cpu_ops pv_cpu_ops;
55
56extern void ia64_native_setreg_func(int regnum, unsigned long val);
57extern unsigned long ia64_native_getreg_func(int regnum);
58
59/************************************************/
60/* Instructions paravirtualized for performance */
61/************************************************/
62
63/* mask for ia64_native_ssm/rsm() must be constant.("i" constraing).
64 * static inline function doesn't satisfy it. */
65#define paravirt_ssm(mask) \
66 do { \
67 if ((mask) == IA64_PSR_I) \
68 pv_cpu_ops.ssm_i(); \
69 else \
70 ia64_native_ssm(mask); \
71 } while (0)
72
73#define paravirt_rsm(mask) \
74 do { \
75 if ((mask) == IA64_PSR_I) \
76 pv_cpu_ops.rsm_i(); \
77 else \
78 ia64_native_rsm(mask); \
79 } while (0)
80
81/******************************************************************************
82 * replacement of hand written assembly codes.
83 */
84struct pv_cpu_asm_switch {
85 unsigned long switch_to;
86 unsigned long leave_syscall;
87 unsigned long work_processed_syscall;
88 unsigned long leave_kernel;
89};
90void paravirt_cpu_asm_init(const struct pv_cpu_asm_switch *cpu_asm_switch);
91
92#endif /* __ASSEMBLY__ */
93
94#define IA64_PARAVIRT_ASM_FUNC(name) paravirt_ ## name
95
96#else
97
98/* fallback for native case */
99#define IA64_PARAVIRT_ASM_FUNC(name) ia64_native_ ## name
100
101#endif /* CONFIG_PARAVIRT */
102
103/* these routines utilize privilege-sensitive or performance-sensitive
104 * privileged instructions so the code must be replaced with
105 * paravirtualized versions */
106#define ia64_switch_to IA64_PARAVIRT_ASM_FUNC(switch_to)
107#define ia64_leave_syscall IA64_PARAVIRT_ASM_FUNC(leave_syscall)
108#define ia64_work_processed_syscall \
109 IA64_PARAVIRT_ASM_FUNC(work_processed_syscall)
110#define ia64_leave_kernel IA64_PARAVIRT_ASM_FUNC(leave_kernel)
111
112#endif /* _ASM_IA64_PARAVIRT_PRIVOP_H */
diff --git a/arch/ia64/include/asm/parport.h b/arch/ia64/include/asm/parport.h
new file mode 100644
index 000000000000..67e16adfcd25
--- /dev/null
+++ b/arch/ia64/include/asm/parport.h
@@ -0,0 +1,20 @@
1/*
2 * parport.h: platform-specific PC-style parport initialisation
3 *
4 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
5 *
6 * This file should only be included by drivers/parport/parport_pc.c.
7 */
8
9#ifndef _ASM_IA64_PARPORT_H
10#define _ASM_IA64_PARPORT_H 1
11
12static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
13
14static int __devinit
15parport_pc_find_nonpci_ports (int autoirq, int autodma)
16{
17 return parport_pc_find_isa_ports(autoirq, autodma);
18}
19
20#endif /* _ASM_IA64_PARPORT_H */
diff --git a/arch/ia64/include/asm/patch.h b/arch/ia64/include/asm/patch.h
new file mode 100644
index 000000000000..295fe6ab4584
--- /dev/null
+++ b/arch/ia64/include/asm/patch.h
@@ -0,0 +1,27 @@
1#ifndef _ASM_IA64_PATCH_H
2#define _ASM_IA64_PATCH_H
3
4/*
5 * Copyright (C) 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * There are a number of reasons for patching instructions. Rather than duplicating code
9 * all over the place, we put the common stuff here. Reasons for patching: in-kernel
10 * module-loader, virtual-to-physical patch-list, McKinley Errata 9 workaround, and gate
11 * shared library. Undoubtedly, some of these reasons will disappear and others will
12 * be added over time.
13 */
14#include <linux/elf.h>
15#include <linux/types.h>
16
17extern void ia64_patch (u64 insn_addr, u64 mask, u64 val); /* patch any insn slot */
18extern void ia64_patch_imm64 (u64 insn_addr, u64 val); /* patch "movl" w/abs. value*/
19extern void ia64_patch_imm60 (u64 insn_addr, u64 val); /* patch "brl" w/ip-rel value */
20
21extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
22extern void ia64_patch_vtop (unsigned long start, unsigned long end);
23extern void ia64_patch_phys_stack_reg(unsigned long val);
24extern void ia64_patch_rse (unsigned long start, unsigned long end);
25extern void ia64_patch_gate (void);
26
27#endif /* _ASM_IA64_PATCH_H */
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
new file mode 100644
index 000000000000..0149097b736d
--- /dev/null
+++ b/arch/ia64/include/asm/pci.h
@@ -0,0 +1,167 @@
1#ifndef _ASM_IA64_PCI_H
2#define _ASM_IA64_PCI_H
3
4#include <linux/mm.h>
5#include <linux/slab.h>
6#include <linux/spinlock.h>
7#include <linux/string.h>
8#include <linux/types.h>
9
10#include <asm/io.h>
11#include <asm/scatterlist.h>
12#include <asm/hw_irq.h>
13
14/*
15 * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
16 * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
17 * loader.
18 */
19#define pcibios_assign_all_busses() 0
20#define pcibios_scan_all_fns(a, b) 0
21
22#define PCIBIOS_MIN_IO 0x1000
23#define PCIBIOS_MIN_MEM 0x10000000
24
25void pcibios_config_init(void);
26
27struct pci_dev;
28
29/*
30 * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
31 * correspondence between device bus addresses and CPU physical addresses.
32 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
33 * bounce buffer handling code in the block and network device layers.
34 * Platforms with separate bus address spaces _must_ turn this off and provide
35 * a device DMA mapping implementation that takes care of the necessary
36 * address translation.
37 *
38 * For now, the ia64 platforms which may have separate/multiple bus address
39 * spaces all have I/O MMUs which support the merging of physically
40 * discontiguous buffers, so we can use that as the sole factor to determine
41 * the setting of PCI_DMA_BUS_IS_PHYS.
42 */
43extern unsigned long ia64_max_iommu_merge_mask;
44#define PCI_DMA_BUS_IS_PHYS (ia64_max_iommu_merge_mask == ~0UL)
45
46static inline void
47pcibios_set_master (struct pci_dev *dev)
48{
49 /* No special bus mastering setup handling */
50}
51
52static inline void
53pcibios_penalize_isa_irq (int irq, int active)
54{
55 /* We don't do dynamic PCI IRQ allocation */
56}
57
58#include <asm-generic/pci-dma-compat.h>
59
60/* pci_unmap_{single,page} is not a nop, thus... */
61#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
62 dma_addr_t ADDR_NAME;
63#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
64 __u32 LEN_NAME;
65#define pci_unmap_addr(PTR, ADDR_NAME) \
66 ((PTR)->ADDR_NAME)
67#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
68 (((PTR)->ADDR_NAME) = (VAL))
69#define pci_unmap_len(PTR, LEN_NAME) \
70 ((PTR)->LEN_NAME)
71#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
72 (((PTR)->LEN_NAME) = (VAL))
73
74#ifdef CONFIG_PCI
75static inline void pci_dma_burst_advice(struct pci_dev *pdev,
76 enum pci_dma_burst_strategy *strat,
77 unsigned long *strategy_parameter)
78{
79 unsigned long cacheline_size;
80 u8 byte;
81
82 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
83 if (byte == 0)
84 cacheline_size = 1024;
85 else
86 cacheline_size = (int) byte * 4;
87
88 *strat = PCI_DMA_BURST_MULTIPLE;
89 *strategy_parameter = cacheline_size;
90}
91#endif
92
93#define HAVE_PCI_MMAP
94extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
95 enum pci_mmap_state mmap_state, int write_combine);
96#define HAVE_PCI_LEGACY
97extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
98 struct vm_area_struct *vma);
99extern ssize_t pci_read_legacy_io(struct kobject *kobj,
100 struct bin_attribute *bin_attr,
101 char *buf, loff_t off, size_t count);
102extern ssize_t pci_write_legacy_io(struct kobject *kobj,
103 struct bin_attribute *bin_attr,
104 char *buf, loff_t off, size_t count);
105extern int pci_mmap_legacy_mem(struct kobject *kobj,
106 struct bin_attribute *attr,
107 struct vm_area_struct *vma);
108
109#define pci_get_legacy_mem platform_pci_get_legacy_mem
110#define pci_legacy_read platform_pci_legacy_read
111#define pci_legacy_write platform_pci_legacy_write
112
113struct pci_window {
114 struct resource resource;
115 u64 offset;
116};
117
118struct pci_controller {
119 void *acpi_handle;
120 void *iommu;
121 int segment;
122 int node; /* nearest node with memory or -1 for global allocation */
123
124 unsigned int windows;
125 struct pci_window *window;
126
127 void *platform_data;
128};
129
130#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
131#define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
132
133extern struct pci_ops pci_root_ops;
134
135static inline int pci_proc_domain(struct pci_bus *bus)
136{
137 return (pci_domain_nr(bus) != 0);
138}
139
140extern void pcibios_resource_to_bus(struct pci_dev *dev,
141 struct pci_bus_region *region, struct resource *res);
142
143extern void pcibios_bus_to_resource(struct pci_dev *dev,
144 struct resource *res, struct pci_bus_region *region);
145
146static inline struct resource *
147pcibios_select_root(struct pci_dev *pdev, struct resource *res)
148{
149 struct resource *root = NULL;
150
151 if (res->flags & IORESOURCE_IO)
152 root = &ioport_resource;
153 if (res->flags & IORESOURCE_MEM)
154 root = &iomem_resource;
155
156 return root;
157}
158
159#define pcibios_scan_all_fns(a, b) 0
160
161#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
162static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
163{
164 return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
165}
166
167#endif /* _ASM_IA64_PCI_H */
diff --git a/arch/ia64/include/asm/percpu.h b/arch/ia64/include/asm/percpu.h
new file mode 100644
index 000000000000..77f30b664b4e
--- /dev/null
+++ b/arch/ia64/include/asm/percpu.h
@@ -0,0 +1,51 @@
1#ifndef _ASM_IA64_PERCPU_H
2#define _ASM_IA64_PERCPU_H
3
4/*
5 * Copyright (C) 2002-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#define PERCPU_ENOUGH_ROOM PERCPU_PAGE_SIZE
10
11#ifdef __ASSEMBLY__
12# define THIS_CPU(var) (per_cpu__##var) /* use this to mark accesses to per-CPU variables... */
13#else /* !__ASSEMBLY__ */
14
15
16#include <linux/threads.h>
17
18#ifdef CONFIG_SMP
19
20#ifdef HAVE_MODEL_SMALL_ATTRIBUTE
21# define PER_CPU_ATTRIBUTES __attribute__((__model__ (__small__)))
22#endif
23
24#define __my_cpu_offset __ia64_per_cpu_var(local_per_cpu_offset)
25
26extern void *per_cpu_init(void);
27
28#else /* ! SMP */
29
30#define PER_CPU_ATTRIBUTES __attribute__((__section__(".data.percpu")))
31
32#define per_cpu_init() (__phys_per_cpu_start)
33
34#endif /* SMP */
35
36/*
37 * Be extremely careful when taking the address of this variable! Due to virtual
38 * remapping, it is different from the canonical address returned by __get_cpu_var(var)!
39 * On the positive side, using __ia64_per_cpu_var() instead of __get_cpu_var() is slightly
40 * more efficient.
41 */
42#define __ia64_per_cpu_var(var) per_cpu__##var
43
44#include <asm-generic/percpu.h>
45
46/* Equal to __per_cpu_offset[smp_processor_id()], but faster to access: */
47DECLARE_PER_CPU(unsigned long, local_per_cpu_offset);
48
49#endif /* !__ASSEMBLY__ */
50
51#endif /* _ASM_IA64_PERCPU_H */
diff --git a/arch/ia64/include/asm/perfmon.h b/arch/ia64/include/asm/perfmon.h
new file mode 100644
index 000000000000..7f3333dd00e4
--- /dev/null
+++ b/arch/ia64/include/asm/perfmon.h
@@ -0,0 +1,279 @@
1/*
2 * Copyright (C) 2001-2003 Hewlett-Packard Co
3 * Stephane Eranian <eranian@hpl.hp.com>
4 */
5
6#ifndef _ASM_IA64_PERFMON_H
7#define _ASM_IA64_PERFMON_H
8
9/*
10 * perfmon comamnds supported on all CPU models
11 */
12#define PFM_WRITE_PMCS 0x01
13#define PFM_WRITE_PMDS 0x02
14#define PFM_READ_PMDS 0x03
15#define PFM_STOP 0x04
16#define PFM_START 0x05
17#define PFM_ENABLE 0x06 /* obsolete */
18#define PFM_DISABLE 0x07 /* obsolete */
19#define PFM_CREATE_CONTEXT 0x08
20#define PFM_DESTROY_CONTEXT 0x09 /* obsolete use close() */
21#define PFM_RESTART 0x0a
22#define PFM_PROTECT_CONTEXT 0x0b /* obsolete */
23#define PFM_GET_FEATURES 0x0c
24#define PFM_DEBUG 0x0d
25#define PFM_UNPROTECT_CONTEXT 0x0e /* obsolete */
26#define PFM_GET_PMC_RESET_VAL 0x0f
27#define PFM_LOAD_CONTEXT 0x10
28#define PFM_UNLOAD_CONTEXT 0x11
29
30/*
31 * PMU model specific commands (may not be supported on all PMU models)
32 */
33#define PFM_WRITE_IBRS 0x20
34#define PFM_WRITE_DBRS 0x21
35
36/*
37 * context flags
38 */
39#define PFM_FL_NOTIFY_BLOCK 0x01 /* block task on user level notifications */
40#define PFM_FL_SYSTEM_WIDE 0x02 /* create a system wide context */
41#define PFM_FL_OVFL_NO_MSG 0x80 /* do not post overflow/end messages for notification */
42
43/*
44 * event set flags
45 */
46#define PFM_SETFL_EXCL_IDLE 0x01 /* exclude idle task (syswide only) XXX: DO NOT USE YET */
47
48/*
49 * PMC flags
50 */
51#define PFM_REGFL_OVFL_NOTIFY 0x1 /* send notification on overflow */
52#define PFM_REGFL_RANDOM 0x2 /* randomize sampling interval */
53
54/*
55 * PMD/PMC/IBR/DBR return flags (ignored on input)
56 *
57 * Those flags are used on output and must be checked in case EAGAIN is returned
58 * by any of the calls using a pfarg_reg_t or pfarg_dbreg_t structure.
59 */
60#define PFM_REG_RETFL_NOTAVAIL (1UL<<31) /* set if register is implemented but not available */
61#define PFM_REG_RETFL_EINVAL (1UL<<30) /* set if register entry is invalid */
62#define PFM_REG_RETFL_MASK (PFM_REG_RETFL_NOTAVAIL|PFM_REG_RETFL_EINVAL)
63
64#define PFM_REG_HAS_ERROR(flag) (((flag) & PFM_REG_RETFL_MASK) != 0)
65
66typedef unsigned char pfm_uuid_t[16]; /* custom sampling buffer identifier type */
67
68/*
69 * Request structure used to define a context
70 */
71typedef struct {
72 pfm_uuid_t ctx_smpl_buf_id; /* which buffer format to use (if needed) */
73 unsigned long ctx_flags; /* noblock/block */
74 unsigned short ctx_nextra_sets; /* number of extra event sets (you always get 1) */
75 unsigned short ctx_reserved1; /* for future use */
76 int ctx_fd; /* return arg: unique identification for context */
77 void *ctx_smpl_vaddr; /* return arg: virtual address of sampling buffer, is used */
78 unsigned long ctx_reserved2[11];/* for future use */
79} pfarg_context_t;
80
81/*
82 * Request structure used to write/read a PMC or PMD
83 */
84typedef struct {
85 unsigned int reg_num; /* which register */
86 unsigned short reg_set; /* event set for this register */
87 unsigned short reg_reserved1; /* for future use */
88
89 unsigned long reg_value; /* initial pmc/pmd value */
90 unsigned long reg_flags; /* input: pmc/pmd flags, return: reg error */
91
92 unsigned long reg_long_reset; /* reset after buffer overflow notification */
93 unsigned long reg_short_reset; /* reset after counter overflow */
94
95 unsigned long reg_reset_pmds[4]; /* which other counters to reset on overflow */
96 unsigned long reg_random_seed; /* seed value when randomization is used */
97 unsigned long reg_random_mask; /* bitmask used to limit random value */
98 unsigned long reg_last_reset_val;/* return: PMD last reset value */
99
100 unsigned long reg_smpl_pmds[4]; /* which pmds are accessed when PMC overflows */
101 unsigned long reg_smpl_eventid; /* opaque sampling event identifier */
102
103 unsigned long reg_reserved2[3]; /* for future use */
104} pfarg_reg_t;
105
106typedef struct {
107 unsigned int dbreg_num; /* which debug register */
108 unsigned short dbreg_set; /* event set for this register */
109 unsigned short dbreg_reserved1; /* for future use */
110 unsigned long dbreg_value; /* value for debug register */
111 unsigned long dbreg_flags; /* return: dbreg error */
112 unsigned long dbreg_reserved2[1]; /* for future use */
113} pfarg_dbreg_t;
114
115typedef struct {
116 unsigned int ft_version; /* perfmon: major [16-31], minor [0-15] */
117 unsigned int ft_reserved; /* reserved for future use */
118 unsigned long reserved[4]; /* for future use */
119} pfarg_features_t;
120
121typedef struct {
122 pid_t load_pid; /* process to load the context into */
123 unsigned short load_set; /* first event set to load */
124 unsigned short load_reserved1; /* for future use */
125 unsigned long load_reserved2[3]; /* for future use */
126} pfarg_load_t;
127
128typedef struct {
129 int msg_type; /* generic message header */
130 int msg_ctx_fd; /* generic message header */
131 unsigned long msg_ovfl_pmds[4]; /* which PMDs overflowed */
132 unsigned short msg_active_set; /* active set at the time of overflow */
133 unsigned short msg_reserved1; /* for future use */
134 unsigned int msg_reserved2; /* for future use */
135 unsigned long msg_tstamp; /* for perf tuning/debug */
136} pfm_ovfl_msg_t;
137
138typedef struct {
139 int msg_type; /* generic message header */
140 int msg_ctx_fd; /* generic message header */
141 unsigned long msg_tstamp; /* for perf tuning */
142} pfm_end_msg_t;
143
144typedef struct {
145 int msg_type; /* type of the message */
146 int msg_ctx_fd; /* unique identifier for the context */
147 unsigned long msg_tstamp; /* for perf tuning */
148} pfm_gen_msg_t;
149
150#define PFM_MSG_OVFL 1 /* an overflow happened */
151#define PFM_MSG_END 2 /* task to which context was attached ended */
152
153typedef union {
154 pfm_ovfl_msg_t pfm_ovfl_msg;
155 pfm_end_msg_t pfm_end_msg;
156 pfm_gen_msg_t pfm_gen_msg;
157} pfm_msg_t;
158
159/*
160 * Define the version numbers for both perfmon as a whole and the sampling buffer format.
161 */
162#define PFM_VERSION_MAJ 2U
163#define PFM_VERSION_MIN 0U
164#define PFM_VERSION (((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff))
165#define PFM_VERSION_MAJOR(x) (((x)>>16) & 0xffff)
166#define PFM_VERSION_MINOR(x) ((x) & 0xffff)
167
168
169/*
170 * miscellaneous architected definitions
171 */
172#define PMU_FIRST_COUNTER 4 /* first counting monitor (PMC/PMD) */
173#define PMU_MAX_PMCS 256 /* maximum architected number of PMC registers */
174#define PMU_MAX_PMDS 256 /* maximum architected number of PMD registers */
175
176#ifdef __KERNEL__
177
178extern long perfmonctl(int fd, int cmd, void *arg, int narg);
179
180typedef struct {
181 void (*handler)(int irq, void *arg, struct pt_regs *regs);
182} pfm_intr_handler_desc_t;
183
184extern void pfm_save_regs (struct task_struct *);
185extern void pfm_load_regs (struct task_struct *);
186
187extern void pfm_exit_thread(struct task_struct *);
188extern int pfm_use_debug_registers(struct task_struct *);
189extern int pfm_release_debug_registers(struct task_struct *);
190extern void pfm_syst_wide_update_task(struct task_struct *, unsigned long info, int is_ctxswin);
191extern void pfm_inherit(struct task_struct *task, struct pt_regs *regs);
192extern void pfm_init_percpu(void);
193extern void pfm_handle_work(void);
194extern int pfm_install_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
195extern int pfm_remove_alt_pmu_interrupt(pfm_intr_handler_desc_t *h);
196
197
198
199/*
200 * Reset PMD register flags
201 */
202#define PFM_PMD_SHORT_RESET 0
203#define PFM_PMD_LONG_RESET 1
204
205typedef union {
206 unsigned int val;
207 struct {
208 unsigned int notify_user:1; /* notify user program of overflow */
209 unsigned int reset_ovfl_pmds:1; /* reset overflowed PMDs */
210 unsigned int block_task:1; /* block monitored task on kernel exit */
211 unsigned int mask_monitoring:1; /* mask monitors via PMCx.plm */
212 unsigned int reserved:28; /* for future use */
213 } bits;
214} pfm_ovfl_ctrl_t;
215
216typedef struct {
217 unsigned char ovfl_pmd; /* index of overflowed PMD */
218 unsigned char ovfl_notify; /* =1 if monitor requested overflow notification */
219 unsigned short active_set; /* event set active at the time of the overflow */
220 pfm_ovfl_ctrl_t ovfl_ctrl; /* return: perfmon controls to set by handler */
221
222 unsigned long pmd_last_reset; /* last reset value of of the PMD */
223 unsigned long smpl_pmds[4]; /* bitmask of other PMD of interest on overflow */
224 unsigned long smpl_pmds_values[PMU_MAX_PMDS]; /* values for the other PMDs of interest */
225 unsigned long pmd_value; /* current 64-bit value of the PMD */
226 unsigned long pmd_eventid; /* eventid associated with PMD */
227} pfm_ovfl_arg_t;
228
229
230typedef struct {
231 char *fmt_name;
232 pfm_uuid_t fmt_uuid;
233 size_t fmt_arg_size;
234 unsigned long fmt_flags;
235
236 int (*fmt_validate)(struct task_struct *task, unsigned int flags, int cpu, void *arg);
237 int (*fmt_getsize)(struct task_struct *task, unsigned int flags, int cpu, void *arg, unsigned long *size);
238 int (*fmt_init)(struct task_struct *task, void *buf, unsigned int flags, int cpu, void *arg);
239 int (*fmt_handler)(struct task_struct *task, void *buf, pfm_ovfl_arg_t *arg, struct pt_regs *regs, unsigned long stamp);
240 int (*fmt_restart)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
241 int (*fmt_restart_active)(struct task_struct *task, pfm_ovfl_ctrl_t *ctrl, void *buf, struct pt_regs *regs);
242 int (*fmt_exit)(struct task_struct *task, void *buf, struct pt_regs *regs);
243
244 struct list_head fmt_list;
245} pfm_buffer_fmt_t;
246
247extern int pfm_register_buffer_fmt(pfm_buffer_fmt_t *fmt);
248extern int pfm_unregister_buffer_fmt(pfm_uuid_t uuid);
249
250/*
251 * perfmon interface exported to modules
252 */
253extern int pfm_mod_read_pmds(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
254extern int pfm_mod_write_pmcs(struct task_struct *, void *req, unsigned int nreq, struct pt_regs *regs);
255extern int pfm_mod_write_ibrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
256extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int nreq, struct pt_regs *regs);
257
258/*
259 * describe the content of the local_cpu_date->pfm_syst_info field
260 */
261#define PFM_CPUINFO_SYST_WIDE 0x1 /* if set a system wide session exists */
262#define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */
263#define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */
264
265/*
266 * sysctl control structure. visible to sampling formats
267 */
268typedef struct {
269 int debug; /* turn on/off debugging via syslog */
270 int debug_ovfl; /* turn on/off debug printk in overflow handler */
271 int fastctxsw; /* turn on/off fast (unsecure) ctxsw */
272 int expert_mode; /* turn on/off value checking */
273} pfm_sysctl_t;
274extern pfm_sysctl_t pfm_sysctl;
275
276
277#endif /* __KERNEL__ */
278
279#endif /* _ASM_IA64_PERFMON_H */
diff --git a/arch/ia64/include/asm/perfmon_default_smpl.h b/arch/ia64/include/asm/perfmon_default_smpl.h
new file mode 100644
index 000000000000..48822c0811d8
--- /dev/null
+++ b/arch/ia64/include/asm/perfmon_default_smpl.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2002-2003 Hewlett-Packard Co
3 * Stephane Eranian <eranian@hpl.hp.com>
4 *
5 * This file implements the default sampling buffer format
6 * for Linux/ia64 perfmon subsystem.
7 */
8#ifndef __PERFMON_DEFAULT_SMPL_H__
9#define __PERFMON_DEFAULT_SMPL_H__ 1
10
11#define PFM_DEFAULT_SMPL_UUID { \
12 0x4d, 0x72, 0xbe, 0xc0, 0x06, 0x64, 0x41, 0x43, 0x82, 0xb4, 0xd3, 0xfd, 0x27, 0x24, 0x3c, 0x97}
13
14/*
15 * format specific parameters (passed at context creation)
16 */
17typedef struct {
18 unsigned long buf_size; /* size of the buffer in bytes */
19 unsigned int flags; /* buffer specific flags */
20 unsigned int res1; /* for future use */
21 unsigned long reserved[2]; /* for future use */
22} pfm_default_smpl_arg_t;
23
24/*
25 * combined context+format specific structure. Can be passed
26 * to PFM_CONTEXT_CREATE
27 */
28typedef struct {
29 pfarg_context_t ctx_arg;
30 pfm_default_smpl_arg_t buf_arg;
31} pfm_default_smpl_ctx_arg_t;
32
33/*
34 * This header is at the beginning of the sampling buffer returned to the user.
35 * It is directly followed by the first record.
36 */
37typedef struct {
38 unsigned long hdr_count; /* how many valid entries */
39 unsigned long hdr_cur_offs; /* current offset from top of buffer */
40 unsigned long hdr_reserved2; /* reserved for future use */
41
42 unsigned long hdr_overflows; /* how many times the buffer overflowed */
43 unsigned long hdr_buf_size; /* how many bytes in the buffer */
44
45 unsigned int hdr_version; /* contains perfmon version (smpl format diffs) */
46 unsigned int hdr_reserved1; /* for future use */
47 unsigned long hdr_reserved[10]; /* for future use */
48} pfm_default_smpl_hdr_t;
49
50/*
51 * Entry header in the sampling buffer. The header is directly followed
52 * with the values of the PMD registers of interest saved in increasing
53 * index order: PMD4, PMD5, and so on. How many PMDs are present depends
54 * on how the session was programmed.
55 *
56 * In the case where multiple counters overflow at the same time, multiple
57 * entries are written consecutively.
58 *
59 * last_reset_value member indicates the initial value of the overflowed PMD.
60 */
61typedef struct {
62 int pid; /* thread id (for NPTL, this is gettid()) */
63 unsigned char reserved1[3]; /* reserved for future use */
64 unsigned char ovfl_pmd; /* index of overflowed PMD */
65
66 unsigned long last_reset_val; /* initial value of overflowed PMD */
67 unsigned long ip; /* where did the overflow interrupt happened */
68 unsigned long tstamp; /* ar.itc when entering perfmon intr. handler */
69
70 unsigned short cpu; /* cpu on which the overfow occured */
71 unsigned short set; /* event set active when overflow ocurred */
72 int tgid; /* thread group id (for NPTL, this is getpid()) */
73} pfm_default_smpl_entry_t;
74
75#define PFM_DEFAULT_MAX_PMDS 64 /* how many pmds supported by data structures (sizeof(unsigned long) */
76#define PFM_DEFAULT_MAX_ENTRY_SIZE (sizeof(pfm_default_smpl_entry_t)+(sizeof(unsigned long)*PFM_DEFAULT_MAX_PMDS))
77#define PFM_DEFAULT_SMPL_MIN_BUF_SIZE (sizeof(pfm_default_smpl_hdr_t)+PFM_DEFAULT_MAX_ENTRY_SIZE)
78
79#define PFM_DEFAULT_SMPL_VERSION_MAJ 2U
80#define PFM_DEFAULT_SMPL_VERSION_MIN 0U
81#define PFM_DEFAULT_SMPL_VERSION (((PFM_DEFAULT_SMPL_VERSION_MAJ&0xffff)<<16)|(PFM_DEFAULT_SMPL_VERSION_MIN & 0xffff))
82
83#endif /* __PERFMON_DEFAULT_SMPL_H__ */
diff --git a/arch/ia64/include/asm/pgalloc.h b/arch/ia64/include/asm/pgalloc.h
new file mode 100644
index 000000000000..b9ac1a6fc216
--- /dev/null
+++ b/arch/ia64/include/asm/pgalloc.h
@@ -0,0 +1,122 @@
1#ifndef _ASM_IA64_PGALLOC_H
2#define _ASM_IA64_PGALLOC_H
3
4/*
5 * This file contains the functions and defines necessary to allocate
6 * page tables.
7 *
8 * This hopefully works with any (fixed) ia-64 page-size, as defined
9 * in <asm/page.h> (currently 8192).
10 *
11 * Copyright (C) 1998-2001 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 * Copyright (C) 2000, Goutham Rao <goutham.rao@intel.com>
14 */
15
16
17#include <linux/compiler.h>
18#include <linux/mm.h>
19#include <linux/page-flags.h>
20#include <linux/threads.h>
21#include <linux/quicklist.h>
22
23#include <asm/mmu_context.h>
24
25static inline pgd_t *pgd_alloc(struct mm_struct *mm)
26{
27 return quicklist_alloc(0, GFP_KERNEL, NULL);
28}
29
30static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
31{
32 quicklist_free(0, NULL, pgd);
33}
34
35#ifdef CONFIG_PGTABLE_4
36static inline void
37pgd_populate(struct mm_struct *mm, pgd_t * pgd_entry, pud_t * pud)
38{
39 pgd_val(*pgd_entry) = __pa(pud);
40}
41
42static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
43{
44 return quicklist_alloc(0, GFP_KERNEL, NULL);
45}
46
47static inline void pud_free(struct mm_struct *mm, pud_t *pud)
48{
49 quicklist_free(0, NULL, pud);
50}
51#define __pud_free_tlb(tlb, pud) pud_free((tlb)->mm, pud)
52#endif /* CONFIG_PGTABLE_4 */
53
54static inline void
55pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
56{
57 pud_val(*pud_entry) = __pa(pmd);
58}
59
60static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
61{
62 return quicklist_alloc(0, GFP_KERNEL, NULL);
63}
64
65static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
66{
67 quicklist_free(0, NULL, pmd);
68}
69
70#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
71
72static inline void
73pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte)
74{
75 pmd_val(*pmd_entry) = page_to_phys(pte);
76}
77#define pmd_pgtable(pmd) pmd_page(pmd)
78
79static inline void
80pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
81{
82 pmd_val(*pmd_entry) = __pa(pte);
83}
84
85static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
86{
87 struct page *page;
88 void *pg;
89
90 pg = quicklist_alloc(0, GFP_KERNEL, NULL);
91 if (!pg)
92 return NULL;
93 page = virt_to_page(pg);
94 pgtable_page_ctor(page);
95 return page;
96}
97
98static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
99 unsigned long addr)
100{
101 return quicklist_alloc(0, GFP_KERNEL, NULL);
102}
103
104static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
105{
106 pgtable_page_dtor(pte);
107 quicklist_free_page(0, NULL, pte);
108}
109
110static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
111{
112 quicklist_free(0, NULL, pte);
113}
114
115static inline void check_pgt_cache(void)
116{
117 quicklist_trim(0, NULL, 25, 16);
118}
119
120#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
121
122#endif /* _ASM_IA64_PGALLOC_H */
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
new file mode 100644
index 000000000000..7a9bff47564f
--- /dev/null
+++ b/arch/ia64/include/asm/pgtable.h
@@ -0,0 +1,615 @@
1#ifndef _ASM_IA64_PGTABLE_H
2#define _ASM_IA64_PGTABLE_H
3
4/*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
11 * Copyright (C) 1998-2005 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
14
15
16#include <asm/mman.h>
17#include <asm/page.h>
18#include <asm/processor.h>
19#include <asm/system.h>
20#include <asm/types.h>
21
22#define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
23
24/*
25 * First, define the various bits in a PTE. Note that the PTE format
26 * matches the VHPT short format, the firt doubleword of the VHPD long
27 * format, and the first doubleword of the TLB insertion format.
28 */
29#define _PAGE_P_BIT 0
30#define _PAGE_A_BIT 5
31#define _PAGE_D_BIT 6
32
33#define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
34#define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
35#define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
36#define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
37#define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
38#define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
39#define _PAGE_MA_MASK (0x7 << 2)
40#define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
41#define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
42#define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
43#define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
44#define _PAGE_PL_MASK (3 << 7)
45#define _PAGE_AR_R (0 << 9) /* read only */
46#define _PAGE_AR_RX (1 << 9) /* read & execute */
47#define _PAGE_AR_RW (2 << 9) /* read & write */
48#define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
49#define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
50#define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
51#define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
52#define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
53#define _PAGE_AR_MASK (7 << 9)
54#define _PAGE_AR_SHIFT 9
55#define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
56#define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
57#define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
58#define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
59#define _PAGE_PROTNONE (__IA64_UL(1) << 63)
60
61/* Valid only for a PTE with the present bit cleared: */
62#define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
63
64#define _PFN_MASK _PAGE_PPN_MASK
65/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
66#define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
67
68#define _PAGE_SIZE_4K 12
69#define _PAGE_SIZE_8K 13
70#define _PAGE_SIZE_16K 14
71#define _PAGE_SIZE_64K 16
72#define _PAGE_SIZE_256K 18
73#define _PAGE_SIZE_1M 20
74#define _PAGE_SIZE_4M 22
75#define _PAGE_SIZE_16M 24
76#define _PAGE_SIZE_64M 26
77#define _PAGE_SIZE_256M 28
78#define _PAGE_SIZE_1G 30
79#define _PAGE_SIZE_4G 32
80
81#define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
82#define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
83#define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
84
85/*
86 * How many pointers will a page table level hold expressed in shift
87 */
88#define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
89
90/*
91 * Definitions for fourth level:
92 */
93#define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
94
95/*
96 * Definitions for third level:
97 *
98 * PMD_SHIFT determines the size of the area a third-level page table
99 * can map.
100 */
101#define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
102#define PMD_SIZE (1UL << PMD_SHIFT)
103#define PMD_MASK (~(PMD_SIZE-1))
104#define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
105
106#ifdef CONFIG_PGTABLE_4
107/*
108 * Definitions for second level:
109 *
110 * PUD_SHIFT determines the size of the area a second-level page table
111 * can map.
112 */
113#define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
114#define PUD_SIZE (1UL << PUD_SHIFT)
115#define PUD_MASK (~(PUD_SIZE-1))
116#define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
117#endif
118
119/*
120 * Definitions for first level:
121 *
122 * PGDIR_SHIFT determines what a first-level page table entry can map.
123 */
124#ifdef CONFIG_PGTABLE_4
125#define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
126#else
127#define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
128#endif
129#define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
130#define PGDIR_MASK (~(PGDIR_SIZE-1))
131#define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
132#define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
133#define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
134#define FIRST_USER_ADDRESS 0
135
136/*
137 * All the normal masks have the "page accessed" bits on, as any time
138 * they are used, the page is accessed. They are cleared only by the
139 * page-out routines.
140 */
141#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
142#define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
143#define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
144#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
145#define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
146#define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
147#define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
148#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
149
150# ifndef __ASSEMBLY__
151
152#include <linux/sched.h> /* for mm_struct */
153#include <linux/bitops.h>
154#include <asm/cacheflush.h>
155#include <asm/mmu_context.h>
156#include <asm/processor.h>
157
158/*
159 * Next come the mappings that determine how mmap() protection bits
160 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
161 * _P version gets used for a private shared memory segment, the _S
162 * version gets used for a shared memory segment with MAP_SHARED on.
163 * In a private shared memory segment, we do a copy-on-write if a task
164 * attempts to write to the page.
165 */
166 /* xwr */
167#define __P000 PAGE_NONE
168#define __P001 PAGE_READONLY
169#define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
170#define __P011 PAGE_READONLY /* ditto */
171#define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
172#define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
173#define __P110 PAGE_COPY_EXEC
174#define __P111 PAGE_COPY_EXEC
175
176#define __S000 PAGE_NONE
177#define __S001 PAGE_READONLY
178#define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
179#define __S011 PAGE_SHARED
180#define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
181#define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
182#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
183#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
184
185#define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
186#ifdef CONFIG_PGTABLE_4
187#define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
188#endif
189#define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
190#define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
191
192
193/*
194 * Some definitions to translate between mem_map, PTEs, and page addresses:
195 */
196
197
198/* Quick test to see if ADDR is a (potentially) valid physical address. */
199static inline long
200ia64_phys_addr_valid (unsigned long addr)
201{
202 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
203}
204
205/*
206 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
207 * memory. For the return value to be meaningful, ADDR must be >=
208 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
209 * require a hash-, or multi-level tree-lookup or something of that
210 * sort) but it guarantees to return TRUE only if accessing the page
211 * at that address does not cause an error. Note that there may be
212 * addresses for which kern_addr_valid() returns FALSE even though an
213 * access would not cause an error (e.g., this is typically true for
214 * memory mapped I/O regions.
215 *
216 * XXX Need to implement this for IA-64.
217 */
218#define kern_addr_valid(addr) (1)
219
220
221/*
222 * Now come the defines and routines to manage and access the three-level
223 * page table.
224 */
225
226
227#define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
228#ifdef CONFIG_VIRTUAL_MEM_MAP
229# define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
230# define VMALLOC_END vmalloc_end
231 extern unsigned long vmalloc_end;
232#else
233#if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
234/* SPARSEMEM_VMEMMAP uses half of vmalloc... */
235# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
236# define vmemmap ((struct page *)VMALLOC_END)
237#else
238# define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
239#endif
240#endif
241
242/* fs/proc/kcore.c */
243#define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
244#define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
245
246#define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
247#define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */
248
249/*
250 * Conversion functions: convert page frame number (pfn) and a protection value to a page
251 * table entry (pte).
252 */
253#define pfn_pte(pfn, pgprot) \
254({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
255
256/* Extract pfn from pte. */
257#define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
258
259#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
260
261/* This takes a physical page address that is used by the remapping functions */
262#define mk_pte_phys(physpage, pgprot) \
263({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
264
265#define pte_modify(_pte, newprot) \
266 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
267
268#define pte_none(pte) (!pte_val(pte))
269#define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
270#define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
271/* pte_page() returns the "struct page *" corresponding to the PTE: */
272#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
273
274#define pmd_none(pmd) (!pmd_val(pmd))
275#define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
276#define pmd_present(pmd) (pmd_val(pmd) != 0UL)
277#define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
278#define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
279#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
280
281#define pud_none(pud) (!pud_val(pud))
282#define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
283#define pud_present(pud) (pud_val(pud) != 0UL)
284#define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
285#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
286#define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
287
288#ifdef CONFIG_PGTABLE_4
289#define pgd_none(pgd) (!pgd_val(pgd))
290#define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd)))
291#define pgd_present(pgd) (pgd_val(pgd) != 0UL)
292#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
293#define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_val(pgd) & _PFN_MASK))
294#define pgd_page(pgd) virt_to_page((pgd_val(pgd) + PAGE_OFFSET))
295#endif
296
297/*
298 * The following have defined behavior only work if pte_present() is true.
299 */
300#define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
301#define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
302#define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
303#define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
304#define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
305#define pte_special(pte) 0
306
307/*
308 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
309 * access rights:
310 */
311#define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
312#define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
313#define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
314#define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
315#define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
316#define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
317#define pte_mkhuge(pte) (__pte(pte_val(pte)))
318#define pte_mkspecial(pte) (pte)
319
320/*
321 * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
322 * sync icache and dcache when we insert *new* executable page.
323 * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
324 * if necessary.
325 *
326 * set_pte() is also called by the kernel, but we can expect that the kernel
327 * flushes icache explicitly if necessary.
328 */
329#define pte_present_exec_user(pte)\
330 ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
331 (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
332
333extern void __ia64_sync_icache_dcache(pte_t pteval);
334static inline void set_pte(pte_t *ptep, pte_t pteval)
335{
336 /* page is present && page is user && page is executable
337 * && (page swapin or new page or page migraton
338 * || copy_on_write with page copying.)
339 */
340 if (pte_present_exec_user(pteval) &&
341 (!pte_present(*ptep) ||
342 pte_pfn(*ptep) != pte_pfn(pteval)))
343 /* load_module() calles flush_icache_range() explicitly*/
344 __ia64_sync_icache_dcache(pteval);
345 *ptep = pteval;
346}
347
348#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
349
350/*
351 * Make page protection values cacheable, uncacheable, or write-
352 * combining. Note that "protection" is really a misnomer here as the
353 * protection value contains the memory attribute bits, dirty bits, and
354 * various other bits as well.
355 */
356#define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
357#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
358#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
359
360struct file;
361extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
362 unsigned long size, pgprot_t vma_prot);
363#define __HAVE_PHYS_MEM_ACCESS_PROT
364
365static inline unsigned long
366pgd_index (unsigned long address)
367{
368 unsigned long region = address >> 61;
369 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
370
371 return (region << (PAGE_SHIFT - 6)) | l1index;
372}
373
374/* The offset in the 1-level directory is given by the 3 region bits
375 (61..63) and the level-1 bits. */
376static inline pgd_t*
377pgd_offset (const struct mm_struct *mm, unsigned long address)
378{
379 return mm->pgd + pgd_index(address);
380}
381
382/* In the kernel's mapped region we completely ignore the region number
383 (since we know it's in region number 5). */
384#define pgd_offset_k(addr) \
385 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
386
387/* Look up a pgd entry in the gate area. On IA-64, the gate-area
388 resides in the kernel-mapped segment, hence we use pgd_offset_k()
389 here. */
390#define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
391
392#ifdef CONFIG_PGTABLE_4
393/* Find an entry in the second-level page table.. */
394#define pud_offset(dir,addr) \
395 ((pud_t *) pgd_page_vaddr(*(dir)) + (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
396#endif
397
398/* Find an entry in the third-level page table.. */
399#define pmd_offset(dir,addr) \
400 ((pmd_t *) pud_page_vaddr(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
401
402/*
403 * Find an entry in the third-level page table. This looks more complicated than it
404 * should be because some platforms place page tables in high memory.
405 */
406#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
407#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
408#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
409#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
410#define pte_unmap(pte) do { } while (0)
411#define pte_unmap_nested(pte) do { } while (0)
412
413/* atomic versions of the some PTE manipulations: */
414
415static inline int
416ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
417{
418#ifdef CONFIG_SMP
419 if (!pte_young(*ptep))
420 return 0;
421 return test_and_clear_bit(_PAGE_A_BIT, ptep);
422#else
423 pte_t pte = *ptep;
424 if (!pte_young(pte))
425 return 0;
426 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
427 return 1;
428#endif
429}
430
431static inline pte_t
432ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
433{
434#ifdef CONFIG_SMP
435 return __pte(xchg((long *) ptep, 0));
436#else
437 pte_t pte = *ptep;
438 pte_clear(mm, addr, ptep);
439 return pte;
440#endif
441}
442
443static inline void
444ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
445{
446#ifdef CONFIG_SMP
447 unsigned long new, old;
448
449 do {
450 old = pte_val(*ptep);
451 new = pte_val(pte_wrprotect(__pte (old)));
452 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
453#else
454 pte_t old_pte = *ptep;
455 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
456#endif
457}
458
459static inline int
460pte_same (pte_t a, pte_t b)
461{
462 return pte_val(a) == pte_val(b);
463}
464
465#define update_mmu_cache(vma, address, pte) do { } while (0)
466
467extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
468extern void paging_init (void);
469
470/*
471 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
472 * bits in the swap-type field of the swap pte. It would be nice to
473 * enforce that, but we can't easily include <linux/swap.h> here.
474 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
475 *
476 * Format of swap pte:
477 * bit 0 : present bit (must be zero)
478 * bit 1 : _PAGE_FILE (must be zero)
479 * bits 2- 8: swap-type
480 * bits 9-62: swap offset
481 * bit 63 : _PAGE_PROTNONE bit
482 *
483 * Format of file pte:
484 * bit 0 : present bit (must be zero)
485 * bit 1 : _PAGE_FILE (must be one)
486 * bits 2-62: file_offset/PAGE_SIZE
487 * bit 63 : _PAGE_PROTNONE bit
488 */
489#define __swp_type(entry) (((entry).val >> 2) & 0x7f)
490#define __swp_offset(entry) (((entry).val << 1) >> 10)
491#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
492#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
493#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
494
495#define PTE_FILE_MAX_BITS 61
496#define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
497#define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
498
499#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
500 remap_pfn_range(vma, vaddr, pfn, size, prot)
501
502/*
503 * ZERO_PAGE is a global shared page that is always zero: used
504 * for zero-mapped memory areas etc..
505 */
506extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
507extern struct page *zero_page_memmap_ptr;
508#define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
509
510/* We provide our own get_unmapped_area to cope with VA holes for userland */
511#define HAVE_ARCH_UNMAPPED_AREA
512
513#ifdef CONFIG_HUGETLB_PAGE
514#define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
515#define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
516#define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
517#endif
518
519
520#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
521/*
522 * Update PTEP with ENTRY, which is guaranteed to be a less
523 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
524 * WRITABLE bits turned on, when the value at PTEP did not. The
525 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
526 *
527 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
528 * having to worry about races. On SMP machines, there are only two
529 * cases where this is true:
530 *
531 * (1) *PTEP has the PRESENT bit turned OFF
532 * (2) ENTRY has the DIRTY bit turned ON
533 *
534 * On ia64, we could implement this routine with a cmpxchg()-loop
535 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
536 * However, like on x86, we can get a more streamlined version by
537 * observing that it is OK to drop ACCESSED bit updates when
538 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
539 * result in an extra Access-bit fault, which would then turn on the
540 * ACCESSED bit in the low-level fault handler (iaccess_bit or
541 * daccess_bit in ivt.S).
542 */
543#ifdef CONFIG_SMP
544# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
545({ \
546 int __changed = !pte_same(*(__ptep), __entry); \
547 if (__changed && __safely_writable) { \
548 set_pte(__ptep, __entry); \
549 flush_tlb_page(__vma, __addr); \
550 } \
551 __changed; \
552})
553#else
554# define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
555({ \
556 int __changed = !pte_same(*(__ptep), __entry); \
557 if (__changed) { \
558 set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \
559 flush_tlb_page(__vma, __addr); \
560 } \
561 __changed; \
562})
563#endif
564
565# ifdef CONFIG_VIRTUAL_MEM_MAP
566 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
567# define __HAVE_ARCH_MEMMAP_INIT
568 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
569 unsigned long start_pfn);
570# endif /* CONFIG_VIRTUAL_MEM_MAP */
571# endif /* !__ASSEMBLY__ */
572
573/*
574 * Identity-mapped regions use a large page size. We'll call such large pages
575 * "granules". If you can think of a better name that's unambiguous, let me
576 * know...
577 */
578#if defined(CONFIG_IA64_GRANULE_64MB)
579# define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
580#elif defined(CONFIG_IA64_GRANULE_16MB)
581# define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
582#endif
583#define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
584/*
585 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
586 */
587#define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
588#define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
589
590/*
591 * No page table caches to initialise
592 */
593#define pgtable_cache_init() do { } while (0)
594
595/* These tell get_user_pages() that the first gate page is accessible from user-level. */
596#define FIXADDR_USER_START GATE_ADDR
597#ifdef HAVE_BUGGY_SEGREL
598# define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
599#else
600# define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
601#endif
602
603#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
604#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
605#define __HAVE_ARCH_PTEP_SET_WRPROTECT
606#define __HAVE_ARCH_PTE_SAME
607#define __HAVE_ARCH_PGD_OFFSET_GATE
608
609
610#ifndef CONFIG_PGTABLE_4
611#include <asm-generic/pgtable-nopud.h>
612#endif
613#include <asm-generic/pgtable.h>
614
615#endif /* _ASM_IA64_PGTABLE_H */
diff --git a/arch/ia64/include/asm/poll.h b/arch/ia64/include/asm/poll.h
new file mode 100644
index 000000000000..c98509d3149e
--- /dev/null
+++ b/arch/ia64/include/asm/poll.h
@@ -0,0 +1 @@
#include <asm-generic/poll.h>
diff --git a/arch/ia64/include/asm/posix_types.h b/arch/ia64/include/asm/posix_types.h
new file mode 100644
index 000000000000..17885567b731
--- /dev/null
+++ b/arch/ia64/include/asm/posix_types.h
@@ -0,0 +1,126 @@
1#ifndef _ASM_IA64_POSIX_TYPES_H
2#define _ASM_IA64_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 *
9 * Based on <asm-alpha/posix_types.h>.
10 *
11 * Modified 1998-2000, 2003
12 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
13 */
14
15typedef unsigned long __kernel_ino_t;
16typedef unsigned int __kernel_mode_t;
17typedef unsigned int __kernel_nlink_t;
18typedef long __kernel_off_t;
19typedef long long __kernel_loff_t;
20typedef int __kernel_pid_t;
21typedef int __kernel_ipc_pid_t;
22typedef unsigned int __kernel_uid_t;
23typedef unsigned int __kernel_gid_t;
24typedef unsigned long __kernel_size_t;
25typedef long __kernel_ssize_t;
26typedef long __kernel_ptrdiff_t;
27typedef long __kernel_time_t;
28typedef long __kernel_suseconds_t;
29typedef long __kernel_clock_t;
30typedef int __kernel_timer_t;
31typedef int __kernel_clockid_t;
32typedef int __kernel_daddr_t;
33typedef char * __kernel_caddr_t;
34typedef unsigned long __kernel_sigset_t; /* at least 32 bits */
35typedef unsigned short __kernel_uid16_t;
36typedef unsigned short __kernel_gid16_t;
37
38typedef struct {
39 int val[2];
40} __kernel_fsid_t;
41
42typedef __kernel_uid_t __kernel_old_uid_t;
43typedef __kernel_gid_t __kernel_old_gid_t;
44typedef __kernel_uid_t __kernel_uid32_t;
45typedef __kernel_gid_t __kernel_gid32_t;
46
47typedef unsigned int __kernel_old_dev_t;
48
49# ifdef __KERNEL__
50
51# ifndef __GNUC__
52
53#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
54#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
55#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
56#define __FD_ZERO(set) \
57 ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
58
59# else /* !__GNUC__ */
60
61/* With GNU C, use inline functions instead so args are evaluated only once: */
62
63#undef __FD_SET
64static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
65{
66 unsigned long _tmp = fd / __NFDBITS;
67 unsigned long _rem = fd % __NFDBITS;
68 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
69}
70
71#undef __FD_CLR
72static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
73{
74 unsigned long _tmp = fd / __NFDBITS;
75 unsigned long _rem = fd % __NFDBITS;
76 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
77}
78
79#undef __FD_ISSET
80static __inline__ int __FD_ISSET(unsigned long fd, const __kernel_fd_set *p)
81{
82 unsigned long _tmp = fd / __NFDBITS;
83 unsigned long _rem = fd % __NFDBITS;
84 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
85}
86
87/*
88 * This will unroll the loop for the normal constant case (8 ints,
89 * for a 256-bit fd_set)
90 */
91#undef __FD_ZERO
92static __inline__ void __FD_ZERO(__kernel_fd_set *p)
93{
94 unsigned long *tmp = p->fds_bits;
95 int i;
96
97 if (__builtin_constant_p(__FDSET_LONGS)) {
98 switch (__FDSET_LONGS) {
99 case 16:
100 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
101 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
102 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
103 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
104 return;
105
106 case 8:
107 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
108 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
109 return;
110
111 case 4:
112 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
113 return;
114 }
115 }
116 i = __FDSET_LONGS;
117 while (i) {
118 i--;
119 *tmp = 0;
120 tmp++;
121 }
122}
123
124# endif /* !__GNUC__ */
125# endif /* __KERNEL__ */
126#endif /* _ASM_IA64_POSIX_TYPES_H */
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
new file mode 100644
index 000000000000..f88fa054d01d
--- /dev/null
+++ b/arch/ia64/include/asm/processor.h
@@ -0,0 +1,771 @@
1#ifndef _ASM_IA64_PROCESSOR_H
2#define _ASM_IA64_PROCESSOR_H
3
4/*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
15
16
17#include <asm/intrinsics.h>
18#include <asm/kregs.h>
19#include <asm/ptrace.h>
20#include <asm/ustack.h>
21
22#define IA64_NUM_PHYS_STACK_REG 96
23#define IA64_NUM_DBG_REGS 8
24
25#define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
26#define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
27
28/*
29 * TASK_SIZE really is a mis-named. It really is the maximum user
30 * space address (plus one). On IA-64, there are five regions of 2TB
31 * each (assuming 8KB page size), for a total of 8TB of user virtual
32 * address space.
33 */
34#define TASK_SIZE_OF(tsk) ((tsk)->thread.task_size)
35#define TASK_SIZE TASK_SIZE_OF(current)
36
37/*
38 * This decides where the kernel will search for a free chunk of vm
39 * space during mmap's.
40 */
41#define TASK_UNMAPPED_BASE (current->thread.map_base)
42
43#define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
44#define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
45#define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
46#define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
47#define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
48#define IA64_THREAD_MIGRATION (__IA64_UL(1) << 5) /* require migration
49 sync at ctx sw */
50#define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
51#define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
52
53#define IA64_THREAD_UAC_SHIFT 3
54#define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
55#define IA64_THREAD_FPEMU_SHIFT 6
56#define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
57
58
59/*
60 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
61 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
62 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
63 */
64#define IA64_NSEC_PER_CYC_SHIFT 30
65
66#ifndef __ASSEMBLY__
67
68#include <linux/cache.h>
69#include <linux/compiler.h>
70#include <linux/threads.h>
71#include <linux/types.h>
72
73#include <asm/fpu.h>
74#include <asm/page.h>
75#include <asm/percpu.h>
76#include <asm/rse.h>
77#include <asm/unwind.h>
78#include <asm/atomic.h>
79#ifdef CONFIG_NUMA
80#include <asm/nodedata.h>
81#endif
82
83/* like above but expressed as bitfields for more efficient access: */
84struct ia64_psr {
85 __u64 reserved0 : 1;
86 __u64 be : 1;
87 __u64 up : 1;
88 __u64 ac : 1;
89 __u64 mfl : 1;
90 __u64 mfh : 1;
91 __u64 reserved1 : 7;
92 __u64 ic : 1;
93 __u64 i : 1;
94 __u64 pk : 1;
95 __u64 reserved2 : 1;
96 __u64 dt : 1;
97 __u64 dfl : 1;
98 __u64 dfh : 1;
99 __u64 sp : 1;
100 __u64 pp : 1;
101 __u64 di : 1;
102 __u64 si : 1;
103 __u64 db : 1;
104 __u64 lp : 1;
105 __u64 tb : 1;
106 __u64 rt : 1;
107 __u64 reserved3 : 4;
108 __u64 cpl : 2;
109 __u64 is : 1;
110 __u64 mc : 1;
111 __u64 it : 1;
112 __u64 id : 1;
113 __u64 da : 1;
114 __u64 dd : 1;
115 __u64 ss : 1;
116 __u64 ri : 2;
117 __u64 ed : 1;
118 __u64 bn : 1;
119 __u64 reserved4 : 19;
120};
121
122union ia64_isr {
123 __u64 val;
124 struct {
125 __u64 code : 16;
126 __u64 vector : 8;
127 __u64 reserved1 : 8;
128 __u64 x : 1;
129 __u64 w : 1;
130 __u64 r : 1;
131 __u64 na : 1;
132 __u64 sp : 1;
133 __u64 rs : 1;
134 __u64 ir : 1;
135 __u64 ni : 1;
136 __u64 so : 1;
137 __u64 ei : 2;
138 __u64 ed : 1;
139 __u64 reserved2 : 20;
140 };
141};
142
143union ia64_lid {
144 __u64 val;
145 struct {
146 __u64 rv : 16;
147 __u64 eid : 8;
148 __u64 id : 8;
149 __u64 ig : 32;
150 };
151};
152
153union ia64_tpr {
154 __u64 val;
155 struct {
156 __u64 ig0 : 4;
157 __u64 mic : 4;
158 __u64 rsv : 8;
159 __u64 mmi : 1;
160 __u64 ig1 : 47;
161 };
162};
163
164union ia64_itir {
165 __u64 val;
166 struct {
167 __u64 rv3 : 2; /* 0-1 */
168 __u64 ps : 6; /* 2-7 */
169 __u64 key : 24; /* 8-31 */
170 __u64 rv4 : 32; /* 32-63 */
171 };
172};
173
174union ia64_rr {
175 __u64 val;
176 struct {
177 __u64 ve : 1; /* enable hw walker */
178 __u64 reserved0: 1; /* reserved */
179 __u64 ps : 6; /* log page size */
180 __u64 rid : 24; /* region id */
181 __u64 reserved1: 32; /* reserved */
182 };
183};
184
185/*
186 * CPU type, hardware bug flags, and per-CPU state. Frequently used
187 * state comes earlier:
188 */
189struct cpuinfo_ia64 {
190 __u32 softirq_pending;
191 __u64 itm_delta; /* # of clock cycles between clock ticks */
192 __u64 itm_next; /* interval timer mask value to use for next clock tick */
193 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
194 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
195 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
196 __u64 itc_freq; /* frequency of ITC counter */
197 __u64 proc_freq; /* frequency of processor */
198 __u64 cyc_per_usec; /* itc_freq/1000000 */
199 __u64 ptce_base;
200 __u32 ptce_count[2];
201 __u32 ptce_stride[2];
202 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
203
204#ifdef CONFIG_SMP
205 __u64 loops_per_jiffy;
206 int cpu;
207 __u32 socket_id; /* physical processor socket id */
208 __u16 core_id; /* core id */
209 __u16 thread_id; /* thread id */
210 __u16 num_log; /* Total number of logical processors on
211 * this socket that were successfully booted */
212 __u8 cores_per_socket; /* Cores per processor socket */
213 __u8 threads_per_core; /* Threads per core */
214#endif
215
216 /* CPUID-derived information: */
217 __u64 ppn;
218 __u64 features;
219 __u8 number;
220 __u8 revision;
221 __u8 model;
222 __u8 family;
223 __u8 archrev;
224 char vendor[16];
225 char *model_name;
226
227#ifdef CONFIG_NUMA
228 struct ia64_node_data *node_data;
229#endif
230};
231
232DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
233
234/*
235 * The "local" data variable. It refers to the per-CPU data of the currently executing
236 * CPU, much like "current" points to the per-task data of the currently executing task.
237 * Do not use the address of local_cpu_data, since it will be different from
238 * cpu_data(smp_processor_id())!
239 */
240#define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
241#define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
242
243extern void print_cpu_info (struct cpuinfo_ia64 *);
244
245typedef struct {
246 unsigned long seg;
247} mm_segment_t;
248
249#define SET_UNALIGN_CTL(task,value) \
250({ \
251 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
252 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
253 0; \
254})
255#define GET_UNALIGN_CTL(task,addr) \
256({ \
257 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
258 (int __user *) (addr)); \
259})
260
261#define SET_FPEMU_CTL(task,value) \
262({ \
263 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
264 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
265 0; \
266})
267#define GET_FPEMU_CTL(task,addr) \
268({ \
269 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
270 (int __user *) (addr)); \
271})
272
273#ifdef CONFIG_IA32_SUPPORT
274struct desc_struct {
275 unsigned int a, b;
276};
277
278#define desc_empty(desc) (!((desc)->a | (desc)->b))
279#define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
280
281#define GDT_ENTRY_TLS_ENTRIES 3
282#define GDT_ENTRY_TLS_MIN 6
283#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
284
285#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
286
287struct ia64_partial_page_list;
288#endif
289
290struct thread_struct {
291 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
292 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
293 __u8 on_ustack; /* executing on user-stacks? */
294 __u8 pad[3];
295 __u64 ksp; /* kernel stack pointer */
296 __u64 map_base; /* base address for get_unmapped_area() */
297 __u64 task_size; /* limit for task size */
298 __u64 rbs_bot; /* the base address for the RBS */
299 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
300
301#ifdef CONFIG_IA32_SUPPORT
302 __u64 eflag; /* IA32 EFLAGS reg */
303 __u64 fsr; /* IA32 floating pt status reg */
304 __u64 fcr; /* IA32 floating pt control reg */
305 __u64 fir; /* IA32 fp except. instr. reg */
306 __u64 fdr; /* IA32 fp except. data reg */
307 __u64 old_k1; /* old value of ar.k1 */
308 __u64 old_iob; /* old IOBase value */
309 struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */
310 /* cached TLS descriptors. */
311 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
312
313# define INIT_THREAD_IA32 .eflag = 0, \
314 .fsr = 0, \
315 .fcr = 0x17800000037fULL, \
316 .fir = 0, \
317 .fdr = 0, \
318 .old_k1 = 0, \
319 .old_iob = 0, \
320 .ppl = NULL,
321#else
322# define INIT_THREAD_IA32
323#endif /* CONFIG_IA32_SUPPORT */
324#ifdef CONFIG_PERFMON
325 void *pfm_context; /* pointer to detailed PMU context */
326 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
327# define INIT_THREAD_PM .pfm_context = NULL, \
328 .pfm_needs_checking = 0UL,
329#else
330# define INIT_THREAD_PM
331#endif
332 __u64 dbr[IA64_NUM_DBG_REGS];
333 __u64 ibr[IA64_NUM_DBG_REGS];
334 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
335};
336
337#define INIT_THREAD { \
338 .flags = 0, \
339 .on_ustack = 0, \
340 .ksp = 0, \
341 .map_base = DEFAULT_MAP_BASE, \
342 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
343 .task_size = DEFAULT_TASK_SIZE, \
344 .last_fph_cpu = -1, \
345 INIT_THREAD_IA32 \
346 INIT_THREAD_PM \
347 .dbr = {0, }, \
348 .ibr = {0, }, \
349 .fph = {{{{0}}}, } \
350}
351
352#define start_thread(regs,new_ip,new_sp) do { \
353 set_fs(USER_DS); \
354 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
355 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
356 regs->cr_iip = new_ip; \
357 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
358 regs->ar_rnat = 0; \
359 regs->ar_bspstore = current->thread.rbs_bot; \
360 regs->ar_fpsr = FPSR_DEFAULT; \
361 regs->loadrs = 0; \
362 regs->r8 = get_dumpable(current->mm); /* set "don't zap registers" flag */ \
363 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
364 if (unlikely(!get_dumpable(current->mm))) { \
365 /* \
366 * Zap scratch regs to avoid leaking bits between processes with different \
367 * uid/privileges. \
368 */ \
369 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
370 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
371 } \
372} while (0)
373
374/* Forward declarations, a strange C thing... */
375struct mm_struct;
376struct task_struct;
377
378/*
379 * Free all resources held by a thread. This is called after the
380 * parent of DEAD_TASK has collected the exit status of the task via
381 * wait().
382 */
383#define release_thread(dead_task)
384
385/* Prepare to copy thread state - unlazy all lazy status */
386#define prepare_to_copy(tsk) do { } while (0)
387
388/*
389 * This is the mechanism for creating a new kernel thread.
390 *
391 * NOTE 1: Only a kernel-only process (ie the swapper or direct
392 * descendants who haven't done an "execve()") should use this: it
393 * will work within a system call from a "real" process, but the
394 * process memory space will not be free'd until both the parent and
395 * the child have exited.
396 *
397 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
398 * into trouble in init/main.c when the child thread returns to
399 * do_basic_setup() and the timing is such that free_initmem() has
400 * been called already.
401 */
402extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
403
404/* Get wait channel for task P. */
405extern unsigned long get_wchan (struct task_struct *p);
406
407/* Return instruction pointer of blocked task TSK. */
408#define KSTK_EIP(tsk) \
409 ({ \
410 struct pt_regs *_regs = task_pt_regs(tsk); \
411 _regs->cr_iip + ia64_psr(_regs)->ri; \
412 })
413
414/* Return stack pointer of blocked task TSK. */
415#define KSTK_ESP(tsk) ((tsk)->thread.ksp)
416
417extern void ia64_getreg_unknown_kr (void);
418extern void ia64_setreg_unknown_kr (void);
419
420#define ia64_get_kr(regnum) \
421({ \
422 unsigned long r = 0; \
423 \
424 switch (regnum) { \
425 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
426 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
427 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
428 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
429 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
430 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
431 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
432 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
433 default: ia64_getreg_unknown_kr(); break; \
434 } \
435 r; \
436})
437
438#define ia64_set_kr(regnum, r) \
439({ \
440 switch (regnum) { \
441 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
442 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
443 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
444 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
445 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
446 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
447 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
448 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
449 default: ia64_setreg_unknown_kr(); break; \
450 } \
451})
452
453/*
454 * The following three macros can't be inline functions because we don't have struct
455 * task_struct at this point.
456 */
457
458/*
459 * Return TRUE if task T owns the fph partition of the CPU we're running on.
460 * Must be called from code that has preemption disabled.
461 */
462#define ia64_is_local_fpu_owner(t) \
463({ \
464 struct task_struct *__ia64_islfo_task = (t); \
465 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
466 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
467})
468
469/*
470 * Mark task T as owning the fph partition of the CPU we're running on.
471 * Must be called from code that has preemption disabled.
472 */
473#define ia64_set_local_fpu_owner(t) do { \
474 struct task_struct *__ia64_slfo_task = (t); \
475 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
476 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
477} while (0)
478
479/* Mark the fph partition of task T as being invalid on all CPUs. */
480#define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
481
482extern void __ia64_init_fpu (void);
483extern void __ia64_save_fpu (struct ia64_fpreg *fph);
484extern void __ia64_load_fpu (struct ia64_fpreg *fph);
485extern void ia64_save_debug_regs (unsigned long *save_area);
486extern void ia64_load_debug_regs (unsigned long *save_area);
487
488#ifdef CONFIG_IA32_SUPPORT
489extern void ia32_save_state (struct task_struct *task);
490extern void ia32_load_state (struct task_struct *task);
491#endif
492
493#define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
494#define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
495
496/* load fp 0.0 into fph */
497static inline void
498ia64_init_fpu (void) {
499 ia64_fph_enable();
500 __ia64_init_fpu();
501 ia64_fph_disable();
502}
503
504/* save f32-f127 at FPH */
505static inline void
506ia64_save_fpu (struct ia64_fpreg *fph) {
507 ia64_fph_enable();
508 __ia64_save_fpu(fph);
509 ia64_fph_disable();
510}
511
512/* load f32-f127 from FPH */
513static inline void
514ia64_load_fpu (struct ia64_fpreg *fph) {
515 ia64_fph_enable();
516 __ia64_load_fpu(fph);
517 ia64_fph_disable();
518}
519
520static inline __u64
521ia64_clear_ic (void)
522{
523 __u64 psr;
524 psr = ia64_getreg(_IA64_REG_PSR);
525 ia64_stop();
526 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
527 ia64_srlz_i();
528 return psr;
529}
530
531/*
532 * Restore the psr.
533 */
534static inline void
535ia64_set_psr (__u64 psr)
536{
537 ia64_stop();
538 ia64_setreg(_IA64_REG_PSR_L, psr);
539 ia64_srlz_i();
540}
541
542/*
543 * Insert a translation into an instruction and/or data translation
544 * register.
545 */
546static inline void
547ia64_itr (__u64 target_mask, __u64 tr_num,
548 __u64 vmaddr, __u64 pte,
549 __u64 log_page_size)
550{
551 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
552 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
553 ia64_stop();
554 if (target_mask & 0x1)
555 ia64_itri(tr_num, pte);
556 if (target_mask & 0x2)
557 ia64_itrd(tr_num, pte);
558}
559
560/*
561 * Insert a translation into the instruction and/or data translation
562 * cache.
563 */
564static inline void
565ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
566 __u64 log_page_size)
567{
568 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
569 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
570 ia64_stop();
571 /* as per EAS2.6, itc must be the last instruction in an instruction group */
572 if (target_mask & 0x1)
573 ia64_itci(pte);
574 if (target_mask & 0x2)
575 ia64_itcd(pte);
576}
577
578/*
579 * Purge a range of addresses from instruction and/or data translation
580 * register(s).
581 */
582static inline void
583ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
584{
585 if (target_mask & 0x1)
586 ia64_ptri(vmaddr, (log_size << 2));
587 if (target_mask & 0x2)
588 ia64_ptrd(vmaddr, (log_size << 2));
589}
590
591/* Set the interrupt vector address. The address must be suitably aligned (32KB). */
592static inline void
593ia64_set_iva (void *ivt_addr)
594{
595 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
596 ia64_srlz_i();
597}
598
599/* Set the page table address and control bits. */
600static inline void
601ia64_set_pta (__u64 pta)
602{
603 /* Note: srlz.i implies srlz.d */
604 ia64_setreg(_IA64_REG_CR_PTA, pta);
605 ia64_srlz_i();
606}
607
608static inline void
609ia64_eoi (void)
610{
611 ia64_setreg(_IA64_REG_CR_EOI, 0);
612 ia64_srlz_d();
613}
614
615#define cpu_relax() ia64_hint(ia64_hint_pause)
616
617static inline int
618ia64_get_irr(unsigned int vector)
619{
620 unsigned int reg = vector / 64;
621 unsigned int bit = vector % 64;
622 u64 irr;
623
624 switch (reg) {
625 case 0: irr = ia64_getreg(_IA64_REG_CR_IRR0); break;
626 case 1: irr = ia64_getreg(_IA64_REG_CR_IRR1); break;
627 case 2: irr = ia64_getreg(_IA64_REG_CR_IRR2); break;
628 case 3: irr = ia64_getreg(_IA64_REG_CR_IRR3); break;
629 }
630
631 return test_bit(bit, &irr);
632}
633
634static inline void
635ia64_set_lrr0 (unsigned long val)
636{
637 ia64_setreg(_IA64_REG_CR_LRR0, val);
638 ia64_srlz_d();
639}
640
641static inline void
642ia64_set_lrr1 (unsigned long val)
643{
644 ia64_setreg(_IA64_REG_CR_LRR1, val);
645 ia64_srlz_d();
646}
647
648
649/*
650 * Given the address to which a spill occurred, return the unat bit
651 * number that corresponds to this address.
652 */
653static inline __u64
654ia64_unat_pos (void *spill_addr)
655{
656 return ((__u64) spill_addr >> 3) & 0x3f;
657}
658
659/*
660 * Set the NaT bit of an integer register which was spilled at address
661 * SPILL_ADDR. UNAT is the mask to be updated.
662 */
663static inline void
664ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
665{
666 __u64 bit = ia64_unat_pos(spill_addr);
667 __u64 mask = 1UL << bit;
668
669 *unat = (*unat & ~mask) | (nat << bit);
670}
671
672/*
673 * Return saved PC of a blocked thread.
674 * Note that the only way T can block is through a call to schedule() -> switch_to().
675 */
676static inline unsigned long
677thread_saved_pc (struct task_struct *t)
678{
679 struct unw_frame_info info;
680 unsigned long ip;
681
682 unw_init_from_blocked_task(&info, t);
683 if (unw_unwind(&info) < 0)
684 return 0;
685 unw_get_ip(&info, &ip);
686 return ip;
687}
688
689/*
690 * Get the current instruction/program counter value.
691 */
692#define current_text_addr() \
693 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
694
695static inline __u64
696ia64_get_ivr (void)
697{
698 __u64 r;
699 ia64_srlz_d();
700 r = ia64_getreg(_IA64_REG_CR_IVR);
701 ia64_srlz_d();
702 return r;
703}
704
705static inline void
706ia64_set_dbr (__u64 regnum, __u64 value)
707{
708 __ia64_set_dbr(regnum, value);
709#ifdef CONFIG_ITANIUM
710 ia64_srlz_d();
711#endif
712}
713
714static inline __u64
715ia64_get_dbr (__u64 regnum)
716{
717 __u64 retval;
718
719 retval = __ia64_get_dbr(regnum);
720#ifdef CONFIG_ITANIUM
721 ia64_srlz_d();
722#endif
723 return retval;
724}
725
726static inline __u64
727ia64_rotr (__u64 w, __u64 n)
728{
729 return (w >> n) | (w << (64 - n));
730}
731
732#define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
733
734/*
735 * Take a mapped kernel address and return the equivalent address
736 * in the region 7 identity mapped virtual area.
737 */
738static inline void *
739ia64_imva (void *addr)
740{
741 void *result;
742 result = (void *) ia64_tpa(addr);
743 return __va(result);
744}
745
746#define ARCH_HAS_PREFETCH
747#define ARCH_HAS_PREFETCHW
748#define ARCH_HAS_SPINLOCK_PREFETCH
749#define PREFETCH_STRIDE L1_CACHE_BYTES
750
751static inline void
752prefetch (const void *x)
753{
754 ia64_lfetch(ia64_lfhint_none, x);
755}
756
757static inline void
758prefetchw (const void *x)
759{
760 ia64_lfetch_excl(ia64_lfhint_none, x);
761}
762
763#define spin_lock_prefetch(x) prefetchw(x)
764
765extern unsigned long boot_option_idle_override;
766extern unsigned long idle_halt;
767extern unsigned long idle_nomwait;
768
769#endif /* !__ASSEMBLY__ */
770
771#endif /* _ASM_IA64_PROCESSOR_H */
diff --git a/arch/ia64/include/asm/ptrace.h b/arch/ia64/include/asm/ptrace.h
new file mode 100644
index 000000000000..15f8dcfe6eee
--- /dev/null
+++ b/arch/ia64/include/asm/ptrace.h
@@ -0,0 +1,364 @@
1#ifndef _ASM_IA64_PTRACE_H
2#define _ASM_IA64_PTRACE_H
3
4/*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 2003 Intel Co
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Fenghua Yu <fenghua.yu@intel.com>
11 * Arun Sharma <arun.sharma@intel.com>
12 *
13 * 12/07/98 S. Eranian added pt_regs & switch_stack
14 * 12/21/98 D. Mosberger updated to match latest code
15 * 6/17/99 D. Mosberger added second unat member to "struct switch_stack"
16 *
17 */
18/*
19 * When a user process is blocked, its state looks as follows:
20 *
21 * +----------------------+ ------- IA64_STK_OFFSET
22 * | | ^
23 * | struct pt_regs | |
24 * | | |
25 * +----------------------+ |
26 * | | |
27 * | memory stack | |
28 * | (growing downwards) | |
29 * //.....................// |
30 * |
31 * //.....................// |
32 * | | |
33 * +----------------------+ |
34 * | struct switch_stack | |
35 * | | |
36 * +----------------------+ |
37 * | | |
38 * //.....................// |
39 * |
40 * //.....................// |
41 * | | |
42 * | register stack | |
43 * | (growing upwards) | |
44 * | | |
45 * +----------------------+ | --- IA64_RBS_OFFSET
46 * | struct thread_info | | ^
47 * +----------------------+ | |
48 * | | | |
49 * | struct task_struct | | |
50 * current -> | | | |
51 * +----------------------+ -------
52 *
53 * Note that ar.ec is not saved explicitly in pt_reg or switch_stack.
54 * This is because ar.ec is saved as part of ar.pfs.
55 */
56
57
58#include <asm/fpu.h>
59
60#ifdef __KERNEL__
61#ifndef ASM_OFFSETS_C
62#include <asm/asm-offsets.h>
63#endif
64
65/*
66 * Base-2 logarithm of number of pages to allocate per task structure
67 * (including register backing store and memory stack):
68 */
69#if defined(CONFIG_IA64_PAGE_SIZE_4KB)
70# define KERNEL_STACK_SIZE_ORDER 3
71#elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
72# define KERNEL_STACK_SIZE_ORDER 2
73#elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
74# define KERNEL_STACK_SIZE_ORDER 1
75#else
76# define KERNEL_STACK_SIZE_ORDER 0
77#endif
78
79#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 31) & ~31)
80#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
81
82#define KERNEL_STACK_SIZE IA64_STK_OFFSET
83
84#endif /* __KERNEL__ */
85
86#ifndef __ASSEMBLY__
87
88/*
89 * This struct defines the way the registers are saved on system
90 * calls.
91 *
92 * We don't save all floating point register because the kernel
93 * is compiled to use only a very small subset, so the other are
94 * untouched.
95 *
96 * THIS STRUCTURE MUST BE A MULTIPLE 16-BYTE IN SIZE
97 * (because the memory stack pointer MUST ALWAYS be aligned this way)
98 *
99 */
100struct pt_regs {
101 /* The following registers are saved by SAVE_MIN: */
102 unsigned long b6; /* scratch */
103 unsigned long b7; /* scratch */
104
105 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
106 unsigned long ar_ssd; /* reserved for future use (scratch) */
107
108 unsigned long r8; /* scratch (return value register 0) */
109 unsigned long r9; /* scratch (return value register 1) */
110 unsigned long r10; /* scratch (return value register 2) */
111 unsigned long r11; /* scratch (return value register 3) */
112
113 unsigned long cr_ipsr; /* interrupted task's psr */
114 unsigned long cr_iip; /* interrupted task's instruction pointer */
115 /*
116 * interrupted task's function state; if bit 63 is cleared, it
117 * contains syscall's ar.pfs.pfm:
118 */
119 unsigned long cr_ifs;
120
121 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
122 unsigned long ar_pfs; /* prev function state */
123 unsigned long ar_rsc; /* RSE configuration */
124 /* The following two are valid only if cr_ipsr.cpl > 0 || ti->flags & _TIF_MCA_INIT */
125 unsigned long ar_rnat; /* RSE NaT */
126 unsigned long ar_bspstore; /* RSE bspstore */
127
128 unsigned long pr; /* 64 predicate registers (1 bit each) */
129 unsigned long b0; /* return pointer (bp) */
130 unsigned long loadrs; /* size of dirty partition << 16 */
131
132 unsigned long r1; /* the gp pointer */
133 unsigned long r12; /* interrupted task's memory stack pointer */
134 unsigned long r13; /* thread pointer */
135
136 unsigned long ar_fpsr; /* floating point status (preserved) */
137 unsigned long r15; /* scratch */
138
139 /* The remaining registers are NOT saved for system calls. */
140
141 unsigned long r14; /* scratch */
142 unsigned long r2; /* scratch */
143 unsigned long r3; /* scratch */
144
145 /* The following registers are saved by SAVE_REST: */
146 unsigned long r16; /* scratch */
147 unsigned long r17; /* scratch */
148 unsigned long r18; /* scratch */
149 unsigned long r19; /* scratch */
150 unsigned long r20; /* scratch */
151 unsigned long r21; /* scratch */
152 unsigned long r22; /* scratch */
153 unsigned long r23; /* scratch */
154 unsigned long r24; /* scratch */
155 unsigned long r25; /* scratch */
156 unsigned long r26; /* scratch */
157 unsigned long r27; /* scratch */
158 unsigned long r28; /* scratch */
159 unsigned long r29; /* scratch */
160 unsigned long r30; /* scratch */
161 unsigned long r31; /* scratch */
162
163 unsigned long ar_ccv; /* compare/exchange value (scratch) */
164
165 /*
166 * Floating point registers that the kernel considers scratch:
167 */
168 struct ia64_fpreg f6; /* scratch */
169 struct ia64_fpreg f7; /* scratch */
170 struct ia64_fpreg f8; /* scratch */
171 struct ia64_fpreg f9; /* scratch */
172 struct ia64_fpreg f10; /* scratch */
173 struct ia64_fpreg f11; /* scratch */
174};
175
176/*
177 * This structure contains the addition registers that need to
178 * preserved across a context switch. This generally consists of
179 * "preserved" registers.
180 */
181struct switch_stack {
182 unsigned long caller_unat; /* user NaT collection register (preserved) */
183 unsigned long ar_fpsr; /* floating-point status register */
184
185 struct ia64_fpreg f2; /* preserved */
186 struct ia64_fpreg f3; /* preserved */
187 struct ia64_fpreg f4; /* preserved */
188 struct ia64_fpreg f5; /* preserved */
189
190 struct ia64_fpreg f12; /* scratch, but untouched by kernel */
191 struct ia64_fpreg f13; /* scratch, but untouched by kernel */
192 struct ia64_fpreg f14; /* scratch, but untouched by kernel */
193 struct ia64_fpreg f15; /* scratch, but untouched by kernel */
194 struct ia64_fpreg f16; /* preserved */
195 struct ia64_fpreg f17; /* preserved */
196 struct ia64_fpreg f18; /* preserved */
197 struct ia64_fpreg f19; /* preserved */
198 struct ia64_fpreg f20; /* preserved */
199 struct ia64_fpreg f21; /* preserved */
200 struct ia64_fpreg f22; /* preserved */
201 struct ia64_fpreg f23; /* preserved */
202 struct ia64_fpreg f24; /* preserved */
203 struct ia64_fpreg f25; /* preserved */
204 struct ia64_fpreg f26; /* preserved */
205 struct ia64_fpreg f27; /* preserved */
206 struct ia64_fpreg f28; /* preserved */
207 struct ia64_fpreg f29; /* preserved */
208 struct ia64_fpreg f30; /* preserved */
209 struct ia64_fpreg f31; /* preserved */
210
211 unsigned long r4; /* preserved */
212 unsigned long r5; /* preserved */
213 unsigned long r6; /* preserved */
214 unsigned long r7; /* preserved */
215
216 unsigned long b0; /* so we can force a direct return in copy_thread */
217 unsigned long b1;
218 unsigned long b2;
219 unsigned long b3;
220 unsigned long b4;
221 unsigned long b5;
222
223 unsigned long ar_pfs; /* previous function state */
224 unsigned long ar_lc; /* loop counter (preserved) */
225 unsigned long ar_unat; /* NaT bits for r4-r7 */
226 unsigned long ar_rnat; /* RSE NaT collection register */
227 unsigned long ar_bspstore; /* RSE dirty base (preserved) */
228 unsigned long pr; /* 64 predicate registers (1 bit each) */
229};
230
231#ifdef __KERNEL__
232
233#include <asm/current.h>
234#include <asm/page.h>
235
236/*
237 * We use the ia64_psr(regs)->ri to determine which of the three
238 * instructions in bundle (16 bytes) took the sample. Generate
239 * the canonical representation by adding to instruction pointer.
240 */
241# define instruction_pointer(regs) ((regs)->cr_iip + ia64_psr(regs)->ri)
242
243#define regs_return_value(regs) ((regs)->r8)
244
245/* Conserve space in histogram by encoding slot bits in address
246 * bits 2 and 3 rather than bits 0 and 1.
247 */
248#define profile_pc(regs) \
249({ \
250 unsigned long __ip = instruction_pointer(regs); \
251 (__ip & ~3UL) + ((__ip & 3UL) << 2); \
252})
253
254 /* given a pointer to a task_struct, return the user's pt_regs */
255# define task_pt_regs(t) (((struct pt_regs *) ((char *) (t) + IA64_STK_OFFSET)) - 1)
256# define ia64_psr(regs) ((struct ia64_psr *) &(regs)->cr_ipsr)
257# define user_mode(regs) (((struct ia64_psr *) &(regs)->cr_ipsr)->cpl != 0)
258# define user_stack(task,regs) ((long) regs - (long) task == IA64_STK_OFFSET - sizeof(*regs))
259# define fsys_mode(task,regs) \
260 ({ \
261 struct task_struct *_task = (task); \
262 struct pt_regs *_regs = (regs); \
263 !user_mode(_regs) && user_stack(_task, _regs); \
264 })
265
266 /*
267 * System call handlers that, upon successful completion, need to return a negative value
268 * should call force_successful_syscall_return() right before returning. On architectures
269 * where the syscall convention provides for a separate error flag (e.g., alpha, ia64,
270 * ppc{,64}, sparc{,64}, possibly others), this macro can be used to ensure that the error
271 * flag will not get set. On architectures which do not support a separate error flag,
272 * the macro is a no-op and the spurious error condition needs to be filtered out by some
273 * other means (e.g., in user-level, by passing an extra argument to the syscall handler,
274 * or something along those lines).
275 *
276 * On ia64, we can clear the user's pt_regs->r8 to force a successful syscall.
277 */
278# define force_successful_syscall_return() (task_pt_regs(current)->r8 = 0)
279
280 struct task_struct; /* forward decl */
281 struct unw_frame_info; /* forward decl */
282
283 extern void show_regs (struct pt_regs *);
284 extern void ia64_do_show_stack (struct unw_frame_info *, void *);
285 extern unsigned long ia64_get_user_rbs_end (struct task_struct *, struct pt_regs *,
286 unsigned long *);
287 extern long ia64_peek (struct task_struct *, struct switch_stack *, unsigned long,
288 unsigned long, long *);
289 extern long ia64_poke (struct task_struct *, struct switch_stack *, unsigned long,
290 unsigned long, long);
291 extern void ia64_flush_fph (struct task_struct *);
292 extern void ia64_sync_fph (struct task_struct *);
293 extern void ia64_sync_krbs(void);
294 extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *,
295 unsigned long, unsigned long);
296
297 /* get nat bits for scratch registers such that bit N==1 iff scratch register rN is a NaT */
298 extern unsigned long ia64_get_scratch_nat_bits (struct pt_regs *pt, unsigned long scratch_unat);
299 /* put nat bits for scratch registers such that scratch register rN is a NaT iff bit N==1 */
300 extern unsigned long ia64_put_scratch_nat_bits (struct pt_regs *pt, unsigned long nat);
301
302 extern void ia64_increment_ip (struct pt_regs *pt);
303 extern void ia64_decrement_ip (struct pt_regs *pt);
304
305 extern void ia64_ptrace_stop(void);
306 #define arch_ptrace_stop(code, info) \
307 ia64_ptrace_stop()
308 #define arch_ptrace_stop_needed(code, info) \
309 (!test_thread_flag(TIF_RESTORE_RSE))
310
311 extern void ptrace_attach_sync_user_rbs (struct task_struct *);
312 #define arch_ptrace_attach(child) \
313 ptrace_attach_sync_user_rbs(child)
314
315 #define arch_has_single_step() (1)
316 extern void user_enable_single_step(struct task_struct *);
317 extern void user_disable_single_step(struct task_struct *);
318
319 #define arch_has_block_step() (1)
320 extern void user_enable_block_step(struct task_struct *);
321
322#endif /* !__KERNEL__ */
323
324/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */
325struct pt_all_user_regs {
326 unsigned long nat;
327 unsigned long cr_iip;
328 unsigned long cfm;
329 unsigned long cr_ipsr;
330 unsigned long pr;
331
332 unsigned long gr[32];
333 unsigned long br[8];
334 unsigned long ar[128];
335 struct ia64_fpreg fr[128];
336};
337
338#endif /* !__ASSEMBLY__ */
339
340/* indices to application-registers array in pt_all_user_regs */
341#define PT_AUR_RSC 16
342#define PT_AUR_BSP 17
343#define PT_AUR_BSPSTORE 18
344#define PT_AUR_RNAT 19
345#define PT_AUR_CCV 32
346#define PT_AUR_UNAT 36
347#define PT_AUR_FPSR 40
348#define PT_AUR_PFS 64
349#define PT_AUR_LC 65
350#define PT_AUR_EC 66
351
352/*
353 * The numbers chosen here are somewhat arbitrary but absolutely MUST
354 * not overlap with any of the number assigned in <linux/ptrace.h>.
355 */
356#define PTRACE_SINGLEBLOCK 12 /* resume execution until next branch */
357#define PTRACE_OLD_GETSIGINFO 13 /* (replaced by PTRACE_GETSIGINFO in <linux/ptrace.h>) */
358#define PTRACE_OLD_SETSIGINFO 14 /* (replaced by PTRACE_SETSIGINFO in <linux/ptrace.h>) */
359#define PTRACE_GETREGS 18 /* get all registers (pt_all_user_regs) in one shot */
360#define PTRACE_SETREGS 19 /* set all registers (pt_all_user_regs) in one shot */
361
362#define PTRACE_OLDSETOPTIONS 21
363
364#endif /* _ASM_IA64_PTRACE_H */
diff --git a/arch/ia64/include/asm/ptrace_offsets.h b/arch/ia64/include/asm/ptrace_offsets.h
new file mode 100644
index 000000000000..b712773c759e
--- /dev/null
+++ b/arch/ia64/include/asm/ptrace_offsets.h
@@ -0,0 +1,268 @@
1#ifndef _ASM_IA64_PTRACE_OFFSETS_H
2#define _ASM_IA64_PTRACE_OFFSETS_H
3
4/*
5 * Copyright (C) 1999, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * The "uarea" that can be accessed via PEEKUSER and POKEUSER is a
10 * virtual structure that would have the following definition:
11 *
12 * struct uarea {
13 * struct ia64_fpreg fph[96]; // f32-f127
14 * unsigned long nat_bits;
15 * unsigned long empty1;
16 * struct ia64_fpreg f2; // f2-f5
17 * :
18 * struct ia64_fpreg f5;
19 * struct ia64_fpreg f10; // f10-f31
20 * :
21 * struct ia64_fpreg f31;
22 * unsigned long r4; // r4-r7
23 * :
24 * unsigned long r7;
25 * unsigned long b1; // b1-b5
26 * :
27 * unsigned long b5;
28 * unsigned long ar_ec;
29 * unsigned long ar_lc;
30 * unsigned long empty2[5];
31 * unsigned long cr_ipsr;
32 * unsigned long cr_iip;
33 * unsigned long cfm;
34 * unsigned long ar_unat;
35 * unsigned long ar_pfs;
36 * unsigned long ar_rsc;
37 * unsigned long ar_rnat;
38 * unsigned long ar_bspstore;
39 * unsigned long pr;
40 * unsigned long b6;
41 * unsigned long ar_bsp;
42 * unsigned long r1;
43 * unsigned long r2;
44 * unsigned long r3;
45 * unsigned long r12;
46 * unsigned long r13;
47 * unsigned long r14;
48 * unsigned long r15;
49 * unsigned long r8;
50 * unsigned long r9;
51 * unsigned long r10;
52 * unsigned long r11;
53 * unsigned long r16;
54 * :
55 * unsigned long r31;
56 * unsigned long ar_ccv;
57 * unsigned long ar_fpsr;
58 * unsigned long b0;
59 * unsigned long b7;
60 * unsigned long f6;
61 * unsigned long f7;
62 * unsigned long f8;
63 * unsigned long f9;
64 * unsigned long ar_csd;
65 * unsigned long ar_ssd;
66 * unsigned long rsvd1[710];
67 * unsigned long dbr[8];
68 * unsigned long rsvd2[504];
69 * unsigned long ibr[8];
70 * unsigned long rsvd3[504];
71 * unsigned long pmd[4];
72 * }
73 */
74
75/* fph: */
76#define PT_F32 0x0000
77#define PT_F33 0x0010
78#define PT_F34 0x0020
79#define PT_F35 0x0030
80#define PT_F36 0x0040
81#define PT_F37 0x0050
82#define PT_F38 0x0060
83#define PT_F39 0x0070
84#define PT_F40 0x0080
85#define PT_F41 0x0090
86#define PT_F42 0x00a0
87#define PT_F43 0x00b0
88#define PT_F44 0x00c0
89#define PT_F45 0x00d0
90#define PT_F46 0x00e0
91#define PT_F47 0x00f0
92#define PT_F48 0x0100
93#define PT_F49 0x0110
94#define PT_F50 0x0120
95#define PT_F51 0x0130
96#define PT_F52 0x0140
97#define PT_F53 0x0150
98#define PT_F54 0x0160
99#define PT_F55 0x0170
100#define PT_F56 0x0180
101#define PT_F57 0x0190
102#define PT_F58 0x01a0
103#define PT_F59 0x01b0
104#define PT_F60 0x01c0
105#define PT_F61 0x01d0
106#define PT_F62 0x01e0
107#define PT_F63 0x01f0
108#define PT_F64 0x0200
109#define PT_F65 0x0210
110#define PT_F66 0x0220
111#define PT_F67 0x0230
112#define PT_F68 0x0240
113#define PT_F69 0x0250
114#define PT_F70 0x0260
115#define PT_F71 0x0270
116#define PT_F72 0x0280
117#define PT_F73 0x0290
118#define PT_F74 0x02a0
119#define PT_F75 0x02b0
120#define PT_F76 0x02c0
121#define PT_F77 0x02d0
122#define PT_F78 0x02e0
123#define PT_F79 0x02f0
124#define PT_F80 0x0300
125#define PT_F81 0x0310
126#define PT_F82 0x0320
127#define PT_F83 0x0330
128#define PT_F84 0x0340
129#define PT_F85 0x0350
130#define PT_F86 0x0360
131#define PT_F87 0x0370
132#define PT_F88 0x0380
133#define PT_F89 0x0390
134#define PT_F90 0x03a0
135#define PT_F91 0x03b0
136#define PT_F92 0x03c0
137#define PT_F93 0x03d0
138#define PT_F94 0x03e0
139#define PT_F95 0x03f0
140#define PT_F96 0x0400
141#define PT_F97 0x0410
142#define PT_F98 0x0420
143#define PT_F99 0x0430
144#define PT_F100 0x0440
145#define PT_F101 0x0450
146#define PT_F102 0x0460
147#define PT_F103 0x0470
148#define PT_F104 0x0480
149#define PT_F105 0x0490
150#define PT_F106 0x04a0
151#define PT_F107 0x04b0
152#define PT_F108 0x04c0
153#define PT_F109 0x04d0
154#define PT_F110 0x04e0
155#define PT_F111 0x04f0
156#define PT_F112 0x0500
157#define PT_F113 0x0510
158#define PT_F114 0x0520
159#define PT_F115 0x0530
160#define PT_F116 0x0540
161#define PT_F117 0x0550
162#define PT_F118 0x0560
163#define PT_F119 0x0570
164#define PT_F120 0x0580
165#define PT_F121 0x0590
166#define PT_F122 0x05a0
167#define PT_F123 0x05b0
168#define PT_F124 0x05c0
169#define PT_F125 0x05d0
170#define PT_F126 0x05e0
171#define PT_F127 0x05f0
172
173#define PT_NAT_BITS 0x0600
174
175#define PT_F2 0x0610
176#define PT_F3 0x0620
177#define PT_F4 0x0630
178#define PT_F5 0x0640
179#define PT_F10 0x0650
180#define PT_F11 0x0660
181#define PT_F12 0x0670
182#define PT_F13 0x0680
183#define PT_F14 0x0690
184#define PT_F15 0x06a0
185#define PT_F16 0x06b0
186#define PT_F17 0x06c0
187#define PT_F18 0x06d0
188#define PT_F19 0x06e0
189#define PT_F20 0x06f0
190#define PT_F21 0x0700
191#define PT_F22 0x0710
192#define PT_F23 0x0720
193#define PT_F24 0x0730
194#define PT_F25 0x0740
195#define PT_F26 0x0750
196#define PT_F27 0x0760
197#define PT_F28 0x0770
198#define PT_F29 0x0780
199#define PT_F30 0x0790
200#define PT_F31 0x07a0
201#define PT_R4 0x07b0
202#define PT_R5 0x07b8
203#define PT_R6 0x07c0
204#define PT_R7 0x07c8
205
206#define PT_B1 0x07d8
207#define PT_B2 0x07e0
208#define PT_B3 0x07e8
209#define PT_B4 0x07f0
210#define PT_B5 0x07f8
211
212#define PT_AR_EC 0x0800
213#define PT_AR_LC 0x0808
214
215#define PT_CR_IPSR 0x0830
216#define PT_CR_IIP 0x0838
217#define PT_CFM 0x0840
218#define PT_AR_UNAT 0x0848
219#define PT_AR_PFS 0x0850
220#define PT_AR_RSC 0x0858
221#define PT_AR_RNAT 0x0860
222#define PT_AR_BSPSTORE 0x0868
223#define PT_PR 0x0870
224#define PT_B6 0x0878
225#define PT_AR_BSP 0x0880 /* note: this points to the *end* of the backing store! */
226#define PT_R1 0x0888
227#define PT_R2 0x0890
228#define PT_R3 0x0898
229#define PT_R12 0x08a0
230#define PT_R13 0x08a8
231#define PT_R14 0x08b0
232#define PT_R15 0x08b8
233#define PT_R8 0x08c0
234#define PT_R9 0x08c8
235#define PT_R10 0x08d0
236#define PT_R11 0x08d8
237#define PT_R16 0x08e0
238#define PT_R17 0x08e8
239#define PT_R18 0x08f0
240#define PT_R19 0x08f8
241#define PT_R20 0x0900
242#define PT_R21 0x0908
243#define PT_R22 0x0910
244#define PT_R23 0x0918
245#define PT_R24 0x0920
246#define PT_R25 0x0928
247#define PT_R26 0x0930
248#define PT_R27 0x0938
249#define PT_R28 0x0940
250#define PT_R29 0x0948
251#define PT_R30 0x0950
252#define PT_R31 0x0958
253#define PT_AR_CCV 0x0960
254#define PT_AR_FPSR 0x0968
255#define PT_B0 0x0970
256#define PT_B7 0x0978
257#define PT_F6 0x0980
258#define PT_F7 0x0990
259#define PT_F8 0x09a0
260#define PT_F9 0x09b0
261#define PT_AR_CSD 0x09c0
262#define PT_AR_SSD 0x09c8
263
264#define PT_DBR 0x2000 /* data breakpoint registers */
265#define PT_IBR 0x3000 /* instruction breakpoint registers */
266#define PT_PMD 0x4000 /* performance monitoring counters */
267
268#endif /* _ASM_IA64_PTRACE_OFFSETS_H */
diff --git a/arch/ia64/include/asm/resource.h b/arch/ia64/include/asm/resource.h
new file mode 100644
index 000000000000..ba2272a87fc7
--- /dev/null
+++ b/arch/ia64/include/asm/resource.h
@@ -0,0 +1,7 @@
1#ifndef _ASM_IA64_RESOURCE_H
2#define _ASM_IA64_RESOURCE_H
3
4#include <asm/ustack.h>
5#include <asm-generic/resource.h>
6
7#endif /* _ASM_IA64_RESOURCE_H */
diff --git a/arch/ia64/include/asm/rse.h b/arch/ia64/include/asm/rse.h
new file mode 100644
index 000000000000..02830a3b0196
--- /dev/null
+++ b/arch/ia64/include/asm/rse.h
@@ -0,0 +1,66 @@
1#ifndef _ASM_IA64_RSE_H
2#define _ASM_IA64_RSE_H
3
4/*
5 * Copyright (C) 1998, 1999 Hewlett-Packard Co
6 * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * Register stack engine related helper functions. This file may be
9 * used in applications, so be careful about the name-space and give
10 * some consideration to non-GNU C compilers (though __inline__ is
11 * fine).
12 */
13
14static __inline__ unsigned long
15ia64_rse_slot_num (unsigned long *addr)
16{
17 return (((unsigned long) addr) >> 3) & 0x3f;
18}
19
20/*
21 * Return TRUE if ADDR is the address of an RNAT slot.
22 */
23static __inline__ unsigned long
24ia64_rse_is_rnat_slot (unsigned long *addr)
25{
26 return ia64_rse_slot_num(addr) == 0x3f;
27}
28
29/*
30 * Returns the address of the RNAT slot that covers the slot at
31 * address SLOT_ADDR.
32 */
33static __inline__ unsigned long *
34ia64_rse_rnat_addr (unsigned long *slot_addr)
35{
36 return (unsigned long *) ((unsigned long) slot_addr | (0x3f << 3));
37}
38
39/*
40 * Calculate the number of registers in the dirty partition starting at BSPSTORE and
41 * ending at BSP. This isn't simply (BSP-BSPSTORE)/8 because every 64th slot stores
42 * ar.rnat.
43 */
44static __inline__ unsigned long
45ia64_rse_num_regs (unsigned long *bspstore, unsigned long *bsp)
46{
47 unsigned long slots = (bsp - bspstore);
48
49 return slots - (ia64_rse_slot_num(bspstore) + slots)/0x40;
50}
51
52/*
53 * The inverse of the above: given bspstore and the number of
54 * registers, calculate ar.bsp.
55 */
56static __inline__ unsigned long *
57ia64_rse_skip_regs (unsigned long *addr, long num_regs)
58{
59 long delta = ia64_rse_slot_num(addr) + num_regs;
60
61 if (num_regs < 0)
62 delta -= 0x3e;
63 return addr + num_regs + delta/0x3f;
64}
65
66#endif /* _ASM_IA64_RSE_H */
diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h
new file mode 100644
index 000000000000..fbee74b15782
--- /dev/null
+++ b/arch/ia64/include/asm/rwsem.h
@@ -0,0 +1,182 @@
1/*
2 * R/W semaphores for ia64
3 *
4 * Copyright (C) 2003 Ken Chen <kenneth.w.chen@intel.com>
5 * Copyright (C) 2003 Asit Mallick <asit.k.mallick@intel.com>
6 * Copyright (C) 2005 Christoph Lameter <clameter@sgi.com>
7 *
8 * Based on asm-i386/rwsem.h and other architecture implementation.
9 *
10 * The MSW of the count is the negated number of active writers and
11 * waiting lockers, and the LSW is the total number of active locks.
12 *
13 * The lock count is initialized to 0 (no active and no waiting lockers).
14 *
15 * When a writer subtracts WRITE_BIAS, it'll get 0xffffffff00000001 for
16 * the case of an uncontended lock. Readers increment by 1 and see a positive
17 * value when uncontended, negative if there are writers (and maybe) readers
18 * waiting (in which case it goes to sleep).
19 */
20
21#ifndef _ASM_IA64_RWSEM_H
22#define _ASM_IA64_RWSEM_H
23
24#ifndef _LINUX_RWSEM_H
25#error "Please don't include <asm/rwsem.h> directly, use <linux/rwsem.h> instead."
26#endif
27
28#include <linux/list.h>
29#include <linux/spinlock.h>
30
31#include <asm/intrinsics.h>
32
33/*
34 * the semaphore definition
35 */
36struct rw_semaphore {
37 signed long count;
38 spinlock_t wait_lock;
39 struct list_head wait_list;
40};
41
42#define RWSEM_UNLOCKED_VALUE __IA64_UL_CONST(0x0000000000000000)
43#define RWSEM_ACTIVE_BIAS __IA64_UL_CONST(0x0000000000000001)
44#define RWSEM_ACTIVE_MASK __IA64_UL_CONST(0x00000000ffffffff)
45#define RWSEM_WAITING_BIAS -__IA64_UL_CONST(0x0000000100000000)
46#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
47#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
48
49#define __RWSEM_INITIALIZER(name) \
50 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
51 LIST_HEAD_INIT((name).wait_list) }
52
53#define DECLARE_RWSEM(name) \
54 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
55
56extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
57extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
58extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
59extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
60
61static inline void
62init_rwsem (struct rw_semaphore *sem)
63{
64 sem->count = RWSEM_UNLOCKED_VALUE;
65 spin_lock_init(&sem->wait_lock);
66 INIT_LIST_HEAD(&sem->wait_list);
67}
68
69/*
70 * lock for reading
71 */
72static inline void
73__down_read (struct rw_semaphore *sem)
74{
75 long result = ia64_fetchadd8_acq((unsigned long *)&sem->count, 1);
76
77 if (result < 0)
78 rwsem_down_read_failed(sem);
79}
80
81/*
82 * lock for writing
83 */
84static inline void
85__down_write (struct rw_semaphore *sem)
86{
87 long old, new;
88
89 do {
90 old = sem->count;
91 new = old + RWSEM_ACTIVE_WRITE_BIAS;
92 } while (cmpxchg_acq(&sem->count, old, new) != old);
93
94 if (old != 0)
95 rwsem_down_write_failed(sem);
96}
97
98/*
99 * unlock after reading
100 */
101static inline void
102__up_read (struct rw_semaphore *sem)
103{
104 long result = ia64_fetchadd8_rel((unsigned long *)&sem->count, -1);
105
106 if (result < 0 && (--result & RWSEM_ACTIVE_MASK) == 0)
107 rwsem_wake(sem);
108}
109
110/*
111 * unlock after writing
112 */
113static inline void
114__up_write (struct rw_semaphore *sem)
115{
116 long old, new;
117
118 do {
119 old = sem->count;
120 new = old - RWSEM_ACTIVE_WRITE_BIAS;
121 } while (cmpxchg_rel(&sem->count, old, new) != old);
122
123 if (new < 0 && (new & RWSEM_ACTIVE_MASK) == 0)
124 rwsem_wake(sem);
125}
126
127/*
128 * trylock for reading -- returns 1 if successful, 0 if contention
129 */
130static inline int
131__down_read_trylock (struct rw_semaphore *sem)
132{
133 long tmp;
134 while ((tmp = sem->count) >= 0) {
135 if (tmp == cmpxchg_acq(&sem->count, tmp, tmp+1)) {
136 return 1;
137 }
138 }
139 return 0;
140}
141
142/*
143 * trylock for writing -- returns 1 if successful, 0 if contention
144 */
145static inline int
146__down_write_trylock (struct rw_semaphore *sem)
147{
148 long tmp = cmpxchg_acq(&sem->count, RWSEM_UNLOCKED_VALUE,
149 RWSEM_ACTIVE_WRITE_BIAS);
150 return tmp == RWSEM_UNLOCKED_VALUE;
151}
152
153/*
154 * downgrade write lock to read lock
155 */
156static inline void
157__downgrade_write (struct rw_semaphore *sem)
158{
159 long old, new;
160
161 do {
162 old = sem->count;
163 new = old - RWSEM_WAITING_BIAS;
164 } while (cmpxchg_rel(&sem->count, old, new) != old);
165
166 if (old < 0)
167 rwsem_downgrade_wake(sem);
168}
169
170/*
171 * Implement atomic add functionality. These used to be "inline" functions, but GCC v3.1
172 * doesn't quite optimize this stuff right and ends up with bad calls to fetchandadd.
173 */
174#define rwsem_atomic_add(delta, sem) atomic64_add(delta, (atomic64_t *)(&(sem)->count))
175#define rwsem_atomic_update(delta, sem) atomic64_add_return(delta, (atomic64_t *)(&(sem)->count))
176
177static inline int rwsem_is_locked(struct rw_semaphore *sem)
178{
179 return (sem->count != 0);
180}
181
182#endif /* _ASM_IA64_RWSEM_H */
diff --git a/arch/ia64/include/asm/sal.h b/arch/ia64/include/asm/sal.h
new file mode 100644
index 000000000000..89594b442f83
--- /dev/null
+++ b/arch/ia64/include/asm/sal.h
@@ -0,0 +1,905 @@
1#ifndef _ASM_IA64_SAL_H
2#define _ASM_IA64_SAL_H
3
4/*
5 * System Abstraction Layer definitions.
6 *
7 * This is based on version 2.5 of the manual "IA-64 System
8 * Abstraction Layer".
9 *
10 * Copyright (C) 2001 Intel
11 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
12 * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
13 * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
14 * David Mosberger-Tang <davidm@hpl.hp.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
18 * revision of the SAL spec.
19 * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
20 * revision of the SAL spec.
21 * 99/09/29 davidm Updated for SAL 2.6.
22 * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
23 * (plus examples of platform error info structures from smariset @ Intel)
24 */
25
26#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0
27#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1
28#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2
29#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3
30
31#define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
32#define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
33#define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
34#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
35
36#ifndef __ASSEMBLY__
37
38#include <linux/bcd.h>
39#include <linux/spinlock.h>
40#include <linux/efi.h>
41
42#include <asm/pal.h>
43#include <asm/system.h>
44#include <asm/fpu.h>
45
46extern spinlock_t sal_lock;
47
48/* SAL spec _requires_ eight args for each call. */
49#define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7) \
50 result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7)
51
52# define IA64_FW_CALL(entry,result,args...) do { \
53 unsigned long __ia64_sc_flags; \
54 struct ia64_fpreg __ia64_sc_fr[6]; \
55 ia64_save_scratch_fpregs(__ia64_sc_fr); \
56 spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
57 __IA64_FW_CALL(entry, result, args); \
58 spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
59 ia64_load_scratch_fpregs(__ia64_sc_fr); \
60} while (0)
61
62# define SAL_CALL(result,args...) \
63 IA64_FW_CALL(ia64_sal, result, args);
64
65# define SAL_CALL_NOLOCK(result,args...) do { \
66 unsigned long __ia64_scn_flags; \
67 struct ia64_fpreg __ia64_scn_fr[6]; \
68 ia64_save_scratch_fpregs(__ia64_scn_fr); \
69 local_irq_save(__ia64_scn_flags); \
70 __IA64_FW_CALL(ia64_sal, result, args); \
71 local_irq_restore(__ia64_scn_flags); \
72 ia64_load_scratch_fpregs(__ia64_scn_fr); \
73} while (0)
74
75# define SAL_CALL_REENTRANT(result,args...) do { \
76 struct ia64_fpreg __ia64_scs_fr[6]; \
77 ia64_save_scratch_fpregs(__ia64_scs_fr); \
78 preempt_disable(); \
79 __IA64_FW_CALL(ia64_sal, result, args); \
80 preempt_enable(); \
81 ia64_load_scratch_fpregs(__ia64_scs_fr); \
82} while (0)
83
84#define SAL_SET_VECTORS 0x01000000
85#define SAL_GET_STATE_INFO 0x01000001
86#define SAL_GET_STATE_INFO_SIZE 0x01000002
87#define SAL_CLEAR_STATE_INFO 0x01000003
88#define SAL_MC_RENDEZ 0x01000004
89#define SAL_MC_SET_PARAMS 0x01000005
90#define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
91
92#define SAL_CACHE_FLUSH 0x01000008
93#define SAL_CACHE_INIT 0x01000009
94#define SAL_PCI_CONFIG_READ 0x01000010
95#define SAL_PCI_CONFIG_WRITE 0x01000011
96#define SAL_FREQ_BASE 0x01000012
97#define SAL_PHYSICAL_ID_INFO 0x01000013
98
99#define SAL_UPDATE_PAL 0x01000020
100
101struct ia64_sal_retval {
102 /*
103 * A zero status value indicates call completed without error.
104 * A negative status value indicates reason of call failure.
105 * A positive status value indicates success but an
106 * informational value should be printed (e.g., "reboot for
107 * change to take effect").
108 */
109 s64 status;
110 u64 v0;
111 u64 v1;
112 u64 v2;
113};
114
115typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
116
117enum {
118 SAL_FREQ_BASE_PLATFORM = 0,
119 SAL_FREQ_BASE_INTERVAL_TIMER = 1,
120 SAL_FREQ_BASE_REALTIME_CLOCK = 2
121};
122
123/*
124 * The SAL system table is followed by a variable number of variable
125 * length descriptors. The structure of these descriptors follows
126 * below.
127 * The defininition follows SAL specs from July 2000
128 */
129struct ia64_sal_systab {
130 u8 signature[4]; /* should be "SST_" */
131 u32 size; /* size of this table in bytes */
132 u8 sal_rev_minor;
133 u8 sal_rev_major;
134 u16 entry_count; /* # of entries in variable portion */
135 u8 checksum;
136 u8 reserved1[7];
137 u8 sal_a_rev_minor;
138 u8 sal_a_rev_major;
139 u8 sal_b_rev_minor;
140 u8 sal_b_rev_major;
141 /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
142 u8 oem_id[32];
143 u8 product_id[32]; /* ASCII product id */
144 u8 reserved2[8];
145};
146
147enum sal_systab_entry_type {
148 SAL_DESC_ENTRY_POINT = 0,
149 SAL_DESC_MEMORY = 1,
150 SAL_DESC_PLATFORM_FEATURE = 2,
151 SAL_DESC_TR = 3,
152 SAL_DESC_PTC = 4,
153 SAL_DESC_AP_WAKEUP = 5
154};
155
156/*
157 * Entry type: Size:
158 * 0 48
159 * 1 32
160 * 2 16
161 * 3 32
162 * 4 16
163 * 5 16
164 */
165#define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
166
167typedef struct ia64_sal_desc_entry_point {
168 u8 type;
169 u8 reserved1[7];
170 u64 pal_proc;
171 u64 sal_proc;
172 u64 gp;
173 u8 reserved2[16];
174}ia64_sal_desc_entry_point_t;
175
176typedef struct ia64_sal_desc_memory {
177 u8 type;
178 u8 used_by_sal; /* needs to be mapped for SAL? */
179 u8 mem_attr; /* current memory attribute setting */
180 u8 access_rights; /* access rights set up by SAL */
181 u8 mem_attr_mask; /* mask of supported memory attributes */
182 u8 reserved1;
183 u8 mem_type; /* memory type */
184 u8 mem_usage; /* memory usage */
185 u64 addr; /* physical address of memory */
186 u32 length; /* length (multiple of 4KB pages) */
187 u32 reserved2;
188 u8 oem_reserved[8];
189} ia64_sal_desc_memory_t;
190
191typedef struct ia64_sal_desc_platform_feature {
192 u8 type;
193 u8 feature_mask;
194 u8 reserved1[14];
195} ia64_sal_desc_platform_feature_t;
196
197typedef struct ia64_sal_desc_tr {
198 u8 type;
199 u8 tr_type; /* 0 == instruction, 1 == data */
200 u8 regnum; /* translation register number */
201 u8 reserved1[5];
202 u64 addr; /* virtual address of area covered */
203 u64 page_size; /* encoded page size */
204 u8 reserved2[8];
205} ia64_sal_desc_tr_t;
206
207typedef struct ia64_sal_desc_ptc {
208 u8 type;
209 u8 reserved1[3];
210 u32 num_domains; /* # of coherence domains */
211 u64 domain_info; /* physical address of domain info table */
212} ia64_sal_desc_ptc_t;
213
214typedef struct ia64_sal_ptc_domain_info {
215 u64 proc_count; /* number of processors in domain */
216 u64 proc_list; /* physical address of LID array */
217} ia64_sal_ptc_domain_info_t;
218
219typedef struct ia64_sal_ptc_domain_proc_entry {
220 u64 id : 8; /* id of processor */
221 u64 eid : 8; /* eid of processor */
222} ia64_sal_ptc_domain_proc_entry_t;
223
224
225#define IA64_SAL_AP_EXTERNAL_INT 0
226
227typedef struct ia64_sal_desc_ap_wakeup {
228 u8 type;
229 u8 mechanism; /* 0 == external interrupt */
230 u8 reserved1[6];
231 u64 vector; /* interrupt vector in range 0x10-0xff */
232} ia64_sal_desc_ap_wakeup_t ;
233
234extern ia64_sal_handler ia64_sal;
235extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
236
237extern unsigned short sal_revision; /* supported SAL spec revision */
238extern unsigned short sal_version; /* SAL version; OEM dependent */
239#define SAL_VERSION_CODE(major, minor) ((BIN2BCD(major) << 8) | BIN2BCD(minor))
240
241extern const char *ia64_sal_strerror (long status);
242extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
243
244/* SAL information type encodings */
245enum {
246 SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
247 SAL_INFO_TYPE_INIT = 1, /* Init information */
248 SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
249 SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
250};
251
252/* Encodings for machine check parameter types */
253enum {
254 SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
255 SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
256 SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
257};
258
259/* Encodings for rendezvous mechanisms */
260enum {
261 SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
262 SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
263};
264
265/* Encodings for vectors which can be registered by the OS with SAL */
266enum {
267 SAL_VECTOR_OS_MCA = 0,
268 SAL_VECTOR_OS_INIT = 1,
269 SAL_VECTOR_OS_BOOT_RENDEZ = 2
270};
271
272/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
273#define SAL_MC_PARAM_RZ_ALWAYS 0x1
274#define SAL_MC_PARAM_BINIT_ESCALATE 0x10
275
276/*
277 * Definition of the SAL Error Log from the SAL spec
278 */
279
280/* SAL Error Record Section GUID Definitions */
281#define SAL_PROC_DEV_ERR_SECT_GUID \
282 EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
283#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
284 EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
285#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
286 EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
287#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
288 EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
289#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
290 EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
291#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
292 EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
293#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
294 EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
295#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
296 EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
297#define SAL_PLAT_BUS_ERR_SECT_GUID \
298 EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
299#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
300 EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
301 0xca, 0x4d)
302
303#define MAX_CACHE_ERRORS 6
304#define MAX_TLB_ERRORS 6
305#define MAX_BUS_ERRORS 1
306
307/* Definition of version according to SAL spec for logging purposes */
308typedef struct sal_log_revision {
309 u8 minor; /* BCD (0..99) */
310 u8 major; /* BCD (0..99) */
311} sal_log_revision_t;
312
313/* Definition of timestamp according to SAL spec for logging purposes */
314typedef struct sal_log_timestamp {
315 u8 slh_second; /* Second (0..59) */
316 u8 slh_minute; /* Minute (0..59) */
317 u8 slh_hour; /* Hour (0..23) */
318 u8 slh_reserved;
319 u8 slh_day; /* Day (1..31) */
320 u8 slh_month; /* Month (1..12) */
321 u8 slh_year; /* Year (00..99) */
322 u8 slh_century; /* Century (19, 20, 21, ...) */
323} sal_log_timestamp_t;
324
325/* Definition of log record header structures */
326typedef struct sal_log_record_header {
327 u64 id; /* Unique monotonically increasing ID */
328 sal_log_revision_t revision; /* Major and Minor revision of header */
329 u8 severity; /* Error Severity */
330 u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
331 u32 len; /* Length of this error log in bytes */
332 sal_log_timestamp_t timestamp; /* Timestamp */
333 efi_guid_t platform_guid; /* Unique OEM Platform ID */
334} sal_log_record_header_t;
335
336#define sal_log_severity_recoverable 0
337#define sal_log_severity_fatal 1
338#define sal_log_severity_corrected 2
339
340/* Definition of log section header structures */
341typedef struct sal_log_sec_header {
342 efi_guid_t guid; /* Unique Section ID */
343 sal_log_revision_t revision; /* Major and Minor revision of Section */
344 u16 reserved;
345 u32 len; /* Section length */
346} sal_log_section_hdr_t;
347
348typedef struct sal_log_mod_error_info {
349 struct {
350 u64 check_info : 1,
351 requestor_identifier : 1,
352 responder_identifier : 1,
353 target_identifier : 1,
354 precise_ip : 1,
355 reserved : 59;
356 } valid;
357 u64 check_info;
358 u64 requestor_identifier;
359 u64 responder_identifier;
360 u64 target_identifier;
361 u64 precise_ip;
362} sal_log_mod_error_info_t;
363
364typedef struct sal_processor_static_info {
365 struct {
366 u64 minstate : 1,
367 br : 1,
368 cr : 1,
369 ar : 1,
370 rr : 1,
371 fr : 1,
372 reserved : 58;
373 } valid;
374 pal_min_state_area_t min_state_area;
375 u64 br[8];
376 u64 cr[128];
377 u64 ar[128];
378 u64 rr[8];
379 struct ia64_fpreg __attribute__ ((packed)) fr[128];
380} sal_processor_static_info_t;
381
382struct sal_cpuid_info {
383 u64 regs[5];
384 u64 reserved;
385};
386
387typedef struct sal_log_processor_info {
388 sal_log_section_hdr_t header;
389 struct {
390 u64 proc_error_map : 1,
391 proc_state_param : 1,
392 proc_cr_lid : 1,
393 psi_static_struct : 1,
394 num_cache_check : 4,
395 num_tlb_check : 4,
396 num_bus_check : 4,
397 num_reg_file_check : 4,
398 num_ms_check : 4,
399 cpuid_info : 1,
400 reserved1 : 39;
401 } valid;
402 u64 proc_error_map;
403 u64 proc_state_parameter;
404 u64 proc_cr_lid;
405 /*
406 * The rest of this structure consists of variable-length arrays, which can't be
407 * expressed in C.
408 */
409 sal_log_mod_error_info_t info[0];
410 /*
411 * This is what the rest looked like if C supported variable-length arrays:
412 *
413 * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
414 * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
415 * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
416 * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
417 * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
418 * struct sal_cpuid_info cpuid_info;
419 * sal_processor_static_info_t processor_static_info;
420 */
421} sal_log_processor_info_t;
422
423/* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
424#define SAL_LPI_PSI_INFO(l) \
425({ sal_log_processor_info_t *_l = (l); \
426 ((sal_processor_static_info_t *) \
427 ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
428 + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
429 + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
430 + sizeof(struct sal_cpuid_info)))); \
431})
432
433/* platform error log structures */
434
435typedef struct sal_log_mem_dev_err_info {
436 sal_log_section_hdr_t header;
437 struct {
438 u64 error_status : 1,
439 physical_addr : 1,
440 addr_mask : 1,
441 node : 1,
442 card : 1,
443 module : 1,
444 bank : 1,
445 device : 1,
446 row : 1,
447 column : 1,
448 bit_position : 1,
449 requestor_id : 1,
450 responder_id : 1,
451 target_id : 1,
452 bus_spec_data : 1,
453 oem_id : 1,
454 oem_data : 1,
455 reserved : 47;
456 } valid;
457 u64 error_status;
458 u64 physical_addr;
459 u64 addr_mask;
460 u16 node;
461 u16 card;
462 u16 module;
463 u16 bank;
464 u16 device;
465 u16 row;
466 u16 column;
467 u16 bit_position;
468 u64 requestor_id;
469 u64 responder_id;
470 u64 target_id;
471 u64 bus_spec_data;
472 u8 oem_id[16];
473 u8 oem_data[1]; /* Variable length data */
474} sal_log_mem_dev_err_info_t;
475
476typedef struct sal_log_sel_dev_err_info {
477 sal_log_section_hdr_t header;
478 struct {
479 u64 record_id : 1,
480 record_type : 1,
481 generator_id : 1,
482 evm_rev : 1,
483 sensor_type : 1,
484 sensor_num : 1,
485 event_dir : 1,
486 event_data1 : 1,
487 event_data2 : 1,
488 event_data3 : 1,
489 reserved : 54;
490 } valid;
491 u16 record_id;
492 u8 record_type;
493 u8 timestamp[4];
494 u16 generator_id;
495 u8 evm_rev;
496 u8 sensor_type;
497 u8 sensor_num;
498 u8 event_dir;
499 u8 event_data1;
500 u8 event_data2;
501 u8 event_data3;
502} sal_log_sel_dev_err_info_t;
503
504typedef struct sal_log_pci_bus_err_info {
505 sal_log_section_hdr_t header;
506 struct {
507 u64 err_status : 1,
508 err_type : 1,
509 bus_id : 1,
510 bus_address : 1,
511 bus_data : 1,
512 bus_cmd : 1,
513 requestor_id : 1,
514 responder_id : 1,
515 target_id : 1,
516 oem_data : 1,
517 reserved : 54;
518 } valid;
519 u64 err_status;
520 u16 err_type;
521 u16 bus_id;
522 u32 reserved;
523 u64 bus_address;
524 u64 bus_data;
525 u64 bus_cmd;
526 u64 requestor_id;
527 u64 responder_id;
528 u64 target_id;
529 u8 oem_data[1]; /* Variable length data */
530} sal_log_pci_bus_err_info_t;
531
532typedef struct sal_log_smbios_dev_err_info {
533 sal_log_section_hdr_t header;
534 struct {
535 u64 event_type : 1,
536 length : 1,
537 time_stamp : 1,
538 data : 1,
539 reserved1 : 60;
540 } valid;
541 u8 event_type;
542 u8 length;
543 u8 time_stamp[6];
544 u8 data[1]; /* data of variable length, length == slsmb_length */
545} sal_log_smbios_dev_err_info_t;
546
547typedef struct sal_log_pci_comp_err_info {
548 sal_log_section_hdr_t header;
549 struct {
550 u64 err_status : 1,
551 comp_info : 1,
552 num_mem_regs : 1,
553 num_io_regs : 1,
554 reg_data_pairs : 1,
555 oem_data : 1,
556 reserved : 58;
557 } valid;
558 u64 err_status;
559 struct {
560 u16 vendor_id;
561 u16 device_id;
562 u8 class_code[3];
563 u8 func_num;
564 u8 dev_num;
565 u8 bus_num;
566 u8 seg_num;
567 u8 reserved[5];
568 } comp_info;
569 u32 num_mem_regs;
570 u32 num_io_regs;
571 u64 reg_data_pairs[1];
572 /*
573 * array of address/data register pairs is num_mem_regs + num_io_regs elements
574 * long. Each array element consists of a u64 address followed by a u64 data
575 * value. The oem_data array immediately follows the reg_data_pairs array
576 */
577 u8 oem_data[1]; /* Variable length data */
578} sal_log_pci_comp_err_info_t;
579
580typedef struct sal_log_plat_specific_err_info {
581 sal_log_section_hdr_t header;
582 struct {
583 u64 err_status : 1,
584 guid : 1,
585 oem_data : 1,
586 reserved : 61;
587 } valid;
588 u64 err_status;
589 efi_guid_t guid;
590 u8 oem_data[1]; /* platform specific variable length data */
591} sal_log_plat_specific_err_info_t;
592
593typedef struct sal_log_host_ctlr_err_info {
594 sal_log_section_hdr_t header;
595 struct {
596 u64 err_status : 1,
597 requestor_id : 1,
598 responder_id : 1,
599 target_id : 1,
600 bus_spec_data : 1,
601 oem_data : 1,
602 reserved : 58;
603 } valid;
604 u64 err_status;
605 u64 requestor_id;
606 u64 responder_id;
607 u64 target_id;
608 u64 bus_spec_data;
609 u8 oem_data[1]; /* Variable length OEM data */
610} sal_log_host_ctlr_err_info_t;
611
612typedef struct sal_log_plat_bus_err_info {
613 sal_log_section_hdr_t header;
614 struct {
615 u64 err_status : 1,
616 requestor_id : 1,
617 responder_id : 1,
618 target_id : 1,
619 bus_spec_data : 1,
620 oem_data : 1,
621 reserved : 58;
622 } valid;
623 u64 err_status;
624 u64 requestor_id;
625 u64 responder_id;
626 u64 target_id;
627 u64 bus_spec_data;
628 u8 oem_data[1]; /* Variable length OEM data */
629} sal_log_plat_bus_err_info_t;
630
631/* Overall platform error section structure */
632typedef union sal_log_platform_err_info {
633 sal_log_mem_dev_err_info_t mem_dev_err;
634 sal_log_sel_dev_err_info_t sel_dev_err;
635 sal_log_pci_bus_err_info_t pci_bus_err;
636 sal_log_smbios_dev_err_info_t smbios_dev_err;
637 sal_log_pci_comp_err_info_t pci_comp_err;
638 sal_log_plat_specific_err_info_t plat_specific_err;
639 sal_log_host_ctlr_err_info_t host_ctlr_err;
640 sal_log_plat_bus_err_info_t plat_bus_err;
641} sal_log_platform_err_info_t;
642
643/* SAL log over-all, multi-section error record structure (processor+platform) */
644typedef struct err_rec {
645 sal_log_record_header_t sal_elog_header;
646 sal_log_processor_info_t proc_err;
647 sal_log_platform_err_info_t plat_err;
648 u8 oem_data_pad[1024];
649} ia64_err_rec_t;
650
651/*
652 * Now define a couple of inline functions for improved type checking
653 * and convenience.
654 */
655
656extern s64 ia64_sal_cache_flush (u64 cache_type);
657extern void __init check_sal_cache_flush (void);
658
659/* Initialize all the processor and platform level instruction and data caches */
660static inline s64
661ia64_sal_cache_init (void)
662{
663 struct ia64_sal_retval isrv;
664 SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
665 return isrv.status;
666}
667
668/*
669 * Clear the processor and platform information logged by SAL with respect to the machine
670 * state at the time of MCA's, INITs, CMCs, or CPEs.
671 */
672static inline s64
673ia64_sal_clear_state_info (u64 sal_info_type)
674{
675 struct ia64_sal_retval isrv;
676 SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
677 0, 0, 0, 0, 0);
678 return isrv.status;
679}
680
681
682/* Get the processor and platform information logged by SAL with respect to the machine
683 * state at the time of the MCAs, INITs, CMCs, or CPEs.
684 */
685static inline u64
686ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
687{
688 struct ia64_sal_retval isrv;
689 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
690 sal_info, 0, 0, 0, 0);
691 if (isrv.status)
692 return 0;
693
694 return isrv.v0;
695}
696
697/*
698 * Get the maximum size of the information logged by SAL with respect to the machine state
699 * at the time of MCAs, INITs, CMCs, or CPEs.
700 */
701static inline u64
702ia64_sal_get_state_info_size (u64 sal_info_type)
703{
704 struct ia64_sal_retval isrv;
705 SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
706 0, 0, 0, 0, 0);
707 if (isrv.status)
708 return 0;
709 return isrv.v0;
710}
711
712/*
713 * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
714 * the monarch processor. Must not lock, because it will not return on any cpu until the
715 * monarch processor sends a wake up.
716 */
717static inline s64
718ia64_sal_mc_rendez (void)
719{
720 struct ia64_sal_retval isrv;
721 SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
722 return isrv.status;
723}
724
725/*
726 * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
727 * the machine check rendezvous sequence as well as the mechanism to wake up the
728 * non-monarch processor at the end of machine check processing.
729 * Returns the complete ia64_sal_retval because some calls return more than just a status
730 * value.
731 */
732static inline struct ia64_sal_retval
733ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
734{
735 struct ia64_sal_retval isrv;
736 SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
737 timeout, rz_always, 0, 0);
738 return isrv;
739}
740
741/* Read from PCI configuration space */
742static inline s64
743ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
744{
745 struct ia64_sal_retval isrv;
746 SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
747 if (value)
748 *value = isrv.v0;
749 return isrv.status;
750}
751
752/* Write to PCI configuration space */
753static inline s64
754ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
755{
756 struct ia64_sal_retval isrv;
757 SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
758 type, 0, 0, 0);
759 return isrv.status;
760}
761
762/*
763 * Register physical addresses of locations needed by SAL when SAL procedures are invoked
764 * in virtual mode.
765 */
766static inline s64
767ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
768{
769 struct ia64_sal_retval isrv;
770 SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
771 0, 0, 0, 0, 0);
772 return isrv.status;
773}
774
775/*
776 * Register software dependent code locations within SAL. These locations are handlers or
777 * entry points where SAL will pass control for the specified event. These event handlers
778 * are for the bott rendezvous, MCAs and INIT scenarios.
779 */
780static inline s64
781ia64_sal_set_vectors (u64 vector_type,
782 u64 handler_addr1, u64 gp1, u64 handler_len1,
783 u64 handler_addr2, u64 gp2, u64 handler_len2)
784{
785 struct ia64_sal_retval isrv;
786 SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
787 handler_addr1, gp1, handler_len1,
788 handler_addr2, gp2, handler_len2);
789
790 return isrv.status;
791}
792
793/* Update the contents of PAL block in the non-volatile storage device */
794static inline s64
795ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
796 u64 *error_code, u64 *scratch_buf_size_needed)
797{
798 struct ia64_sal_retval isrv;
799 SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
800 0, 0, 0, 0);
801 if (error_code)
802 *error_code = isrv.v0;
803 if (scratch_buf_size_needed)
804 *scratch_buf_size_needed = isrv.v1;
805 return isrv.status;
806}
807
808/* Get physical processor die mapping in the platform. */
809static inline s64
810ia64_sal_physical_id_info(u16 *splid)
811{
812 struct ia64_sal_retval isrv;
813
814 if (sal_revision < SAL_VERSION_CODE(3,2))
815 return -1;
816
817 SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
818 if (splid)
819 *splid = isrv.v0;
820 return isrv.status;
821}
822
823extern unsigned long sal_platform_features;
824
825extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
826
827struct sal_ret_values {
828 long r8; long r9; long r10; long r11;
829};
830
831#define IA64_SAL_OEMFUNC_MIN 0x02000000
832#define IA64_SAL_OEMFUNC_MAX 0x03ffffff
833
834extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
835 u64, u64, u64);
836extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
837 u64, u64, u64, u64, u64);
838extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
839 u64, u64, u64, u64, u64);
840extern long
841ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
842 unsigned long *drift_info);
843#ifdef CONFIG_HOTPLUG_CPU
844/*
845 * System Abstraction Layer Specification
846 * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
847 * Note: region regs are stored first in head.S _start. Hence they must
848 * stay up front.
849 */
850struct sal_to_os_boot {
851 u64 rr[8]; /* Region Registers */
852 u64 br[6]; /* br0:
853 * return addr into SAL boot rendez routine */
854 u64 gr1; /* SAL:GP */
855 u64 gr12; /* SAL:SP */
856 u64 gr13; /* SAL: Task Pointer */
857 u64 fpsr;
858 u64 pfs;
859 u64 rnat;
860 u64 unat;
861 u64 bspstore;
862 u64 dcr; /* Default Control Register */
863 u64 iva;
864 u64 pta;
865 u64 itv;
866 u64 pmv;
867 u64 cmcv;
868 u64 lrr[2];
869 u64 gr[4];
870 u64 pr; /* Predicate registers */
871 u64 lc; /* Loop Count */
872 struct ia64_fpreg fp[20];
873};
874
875/*
876 * Global array allocated for NR_CPUS at boot time
877 */
878extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
879
880extern void ia64_jump_to_sal(struct sal_to_os_boot *);
881#endif
882
883extern void ia64_sal_handler_init(void *entry_point, void *gpval);
884
885#define PALO_MAX_TLB_PURGES 0xFFFF
886#define PALO_SIG "PALO"
887
888struct palo_table {
889 u8 signature[4]; /* Should be "PALO" */
890 u32 length;
891 u8 minor_revision;
892 u8 major_revision;
893 u8 checksum;
894 u8 reserved1[5];
895 u16 max_tlb_purges;
896 u8 reserved2[6];
897};
898
899#define NPTCG_FROM_PAL 0
900#define NPTCG_FROM_PALO 1
901#define NPTCG_FROM_KERNEL_PARAMETER 2
902
903#endif /* __ASSEMBLY__ */
904
905#endif /* _ASM_IA64_SAL_H */
diff --git a/arch/ia64/include/asm/scatterlist.h b/arch/ia64/include/asm/scatterlist.h
new file mode 100644
index 000000000000..d6f57874041d
--- /dev/null
+++ b/arch/ia64/include/asm/scatterlist.h
@@ -0,0 +1,38 @@
1#ifndef _ASM_IA64_SCATTERLIST_H
2#define _ASM_IA64_SCATTERLIST_H
3
4/*
5 * Modified 1998-1999, 2001-2002, 2004
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9#include <asm/types.h>
10
11struct scatterlist {
12#ifdef CONFIG_DEBUG_SG
13 unsigned long sg_magic;
14#endif
15 unsigned long page_link;
16 unsigned int offset;
17 unsigned int length; /* buffer length */
18
19 dma_addr_t dma_address;
20 unsigned int dma_length;
21};
22
23/*
24 * It used to be that ISA_DMA_THRESHOLD had something to do with the
25 * DMA-limits of ISA-devices. Nowadays, its only remaining use (apart
26 * from the aha1542.c driver, which isn't 64-bit clean anyhow) is to
27 * tell the block-layer (via BLK_BOUNCE_ISA) what the max. physical
28 * address of a page is that is allocated with GFP_DMA. On IA-64,
29 * that's 4GB - 1.
30 */
31#define ISA_DMA_THRESHOLD 0xffffffff
32
33#define sg_dma_len(sg) ((sg)->dma_length)
34#define sg_dma_address(sg) ((sg)->dma_address)
35
36#define ARCH_HAS_SG_CHAIN
37
38#endif /* _ASM_IA64_SCATTERLIST_H */
diff --git a/arch/ia64/include/asm/sections.h b/arch/ia64/include/asm/sections.h
new file mode 100644
index 000000000000..7286e4a9fe84
--- /dev/null
+++ b/arch/ia64/include/asm/sections.h
@@ -0,0 +1,25 @@
1#ifndef _ASM_IA64_SECTIONS_H
2#define _ASM_IA64_SECTIONS_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm-generic/sections.h>
10
11extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
12extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
13extern char __start___rse_patchlist[], __end___rse_patchlist[];
14extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
15extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
16extern char __start_gate_section[];
17extern char __start_gate_mckinley_e9_patchlist[], __end_gate_mckinley_e9_patchlist[];
18extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[];
19extern char __start_gate_fsyscall_patchlist[], __end_gate_fsyscall_patchlist[];
20extern char __start_gate_brl_fsys_bubble_down_patchlist[], __end_gate_brl_fsys_bubble_down_patchlist[];
21extern char __start_unwind[], __end_unwind[];
22extern char __start_ivt_text[], __end_ivt_text[];
23
24#endif /* _ASM_IA64_SECTIONS_H */
25
diff --git a/arch/ia64/include/asm/segment.h b/arch/ia64/include/asm/segment.h
new file mode 100644
index 000000000000..b89e2b3d648f
--- /dev/null
+++ b/arch/ia64/include/asm/segment.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_IA64_SEGMENT_H
2#define _ASM_IA64_SEGMENT_H
3
4/* Only here because we have some old header files that expect it.. */
5
6#endif /* _ASM_IA64_SEGMENT_H */
diff --git a/arch/ia64/include/asm/sembuf.h b/arch/ia64/include/asm/sembuf.h
new file mode 100644
index 000000000000..1340fbc04d3e
--- /dev/null
+++ b/arch/ia64/include/asm/sembuf.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_IA64_SEMBUF_H
2#define _ASM_IA64_SEMBUF_H
3
4/*
5 * The semid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct semid64_ds {
14 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
15 __kernel_time_t sem_otime; /* last semop time */
16 __kernel_time_t sem_ctime; /* last change time */
17 unsigned long sem_nsems; /* no. of semaphores in array */
18 unsigned long __unused1;
19 unsigned long __unused2;
20};
21
22#endif /* _ASM_IA64_SEMBUF_H */
diff --git a/arch/ia64/include/asm/serial.h b/arch/ia64/include/asm/serial.h
new file mode 100644
index 000000000000..068be11583df
--- /dev/null
+++ b/arch/ia64/include/asm/serial.h
@@ -0,0 +1,17 @@
1/*
2 * Derived from the i386 version.
3 */
4
5/*
6 * This assumes you have a 1.8432 MHz clock for your UART.
7 *
8 * It'd be nice if someone built a serial card with a 24.576 MHz
9 * clock, since the 16550A is capable of handling a top speed of 1.5
10 * megabits/second; but this requires the faster clock.
11 */
12#define BASE_BAUD ( 1843200 / 16 )
13
14/*
15 * All legacy serial ports should be enumerated via ACPI namespace, so
16 * we need not list them here.
17 */
diff --git a/arch/ia64/include/asm/setup.h b/arch/ia64/include/asm/setup.h
new file mode 100644
index 000000000000..4399a44355b3
--- /dev/null
+++ b/arch/ia64/include/asm/setup.h
@@ -0,0 +1,6 @@
1#ifndef __IA64_SETUP_H
2#define __IA64_SETUP_H
3
4#define COMMAND_LINE_SIZE 2048
5
6#endif
diff --git a/arch/ia64/include/asm/shmbuf.h b/arch/ia64/include/asm/shmbuf.h
new file mode 100644
index 000000000000..585002a77acd
--- /dev/null
+++ b/arch/ia64/include/asm/shmbuf.h
@@ -0,0 +1,38 @@
1#ifndef _ASM_IA64_SHMBUF_H
2#define _ASM_IA64_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for IA-64 architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct shmid64_ds {
14 struct ipc64_perm shm_perm; /* operation perms */
15 size_t shm_segsz; /* size of segment (bytes) */
16 __kernel_time_t shm_atime; /* last attach time */
17 __kernel_time_t shm_dtime; /* last detach time */
18 __kernel_time_t shm_ctime; /* last change time */
19 __kernel_pid_t shm_cpid; /* pid of creator */
20 __kernel_pid_t shm_lpid; /* pid of last operator */
21 unsigned long shm_nattch; /* no. of current attaches */
22 unsigned long __unused1;
23 unsigned long __unused2;
24};
25
26struct shminfo64 {
27 unsigned long shmmax;
28 unsigned long shmmin;
29 unsigned long shmmni;
30 unsigned long shmseg;
31 unsigned long shmall;
32 unsigned long __unused1;
33 unsigned long __unused2;
34 unsigned long __unused3;
35 unsigned long __unused4;
36};
37
38#endif /* _ASM_IA64_SHMBUF_H */
diff --git a/arch/ia64/include/asm/shmparam.h b/arch/ia64/include/asm/shmparam.h
new file mode 100644
index 000000000000..d07508dc54ae
--- /dev/null
+++ b/arch/ia64/include/asm/shmparam.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_IA64_SHMPARAM_H
2#define _ASM_IA64_SHMPARAM_H
3
4/*
5 * SHMLBA controls minimum alignment at which shared memory segments
6 * get attached. The IA-64 architecture says that there may be a
7 * performance degradation when there are virtual aliases within 1MB.
8 * To reduce the chance of this, we set SHMLBA to 1MB. --davidm 00/12/20
9 */
10#define SHMLBA (1024*1024)
11
12#endif /* _ASM_IA64_SHMPARAM_H */
diff --git a/arch/ia64/include/asm/sigcontext.h b/arch/ia64/include/asm/sigcontext.h
new file mode 100644
index 000000000000..57ff777bcc40
--- /dev/null
+++ b/arch/ia64/include/asm/sigcontext.h
@@ -0,0 +1,70 @@
1#ifndef _ASM_IA64_SIGCONTEXT_H
2#define _ASM_IA64_SIGCONTEXT_H
3
4/*
5 * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
6 * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9#include <asm/fpu.h>
10
11#define IA64_SC_FLAG_ONSTACK_BIT 0 /* is handler running on signal stack? */
12#define IA64_SC_FLAG_IN_SYSCALL_BIT 1 /* did signal interrupt a syscall? */
13#define IA64_SC_FLAG_FPH_VALID_BIT 2 /* is state in f[32]-f[127] valid? */
14
15#define IA64_SC_FLAG_ONSTACK (1 << IA64_SC_FLAG_ONSTACK_BIT)
16#define IA64_SC_FLAG_IN_SYSCALL (1 << IA64_SC_FLAG_IN_SYSCALL_BIT)
17#define IA64_SC_FLAG_FPH_VALID (1 << IA64_SC_FLAG_FPH_VALID_BIT)
18
19# ifndef __ASSEMBLY__
20
21/*
22 * Note on handling of register backing store: sc_ar_bsp contains the address that would
23 * be found in ar.bsp after executing a "cover" instruction the context in which the
24 * signal was raised. If signal delivery required switching to an alternate signal stack
25 * (sc_rbs_base is not NULL), the "dirty" partition (as it would exist after executing the
26 * imaginary "cover" instruction) is backed by the *alternate* signal stack, not the
27 * original one. In this case, sc_rbs_base contains the base address of the new register
28 * backing store. The number of registers in the dirty partition can be calculated as:
29 *
30 * ndirty = ia64_rse_num_regs(sc_rbs_base, sc_rbs_base + (sc_loadrs >> 16))
31 *
32 */
33
34struct sigcontext {
35 unsigned long sc_flags; /* see manifest constants above */
36 unsigned long sc_nat; /* bit i == 1 iff scratch reg gr[i] is a NaT */
37 stack_t sc_stack; /* previously active stack */
38
39 unsigned long sc_ip; /* instruction pointer */
40 unsigned long sc_cfm; /* current frame marker */
41 unsigned long sc_um; /* user mask bits */
42 unsigned long sc_ar_rsc; /* register stack configuration register */
43 unsigned long sc_ar_bsp; /* backing store pointer */
44 unsigned long sc_ar_rnat; /* RSE NaT collection register */
45 unsigned long sc_ar_ccv; /* compare and exchange compare value register */
46 unsigned long sc_ar_unat; /* ar.unat of interrupted context */
47 unsigned long sc_ar_fpsr; /* floating-point status register */
48 unsigned long sc_ar_pfs; /* previous function state */
49 unsigned long sc_ar_lc; /* loop count register */
50 unsigned long sc_pr; /* predicate registers */
51 unsigned long sc_br[8]; /* branch registers */
52 /* Note: sc_gr[0] is used as the "uc_link" member of ucontext_t */
53 unsigned long sc_gr[32]; /* general registers (static partition) */
54 struct ia64_fpreg sc_fr[128]; /* floating-point registers */
55
56 unsigned long sc_rbs_base; /* NULL or new base of sighandler's rbs */
57 unsigned long sc_loadrs; /* see description above */
58
59 unsigned long sc_ar25; /* cmp8xchg16 uses this */
60 unsigned long sc_ar26; /* rsvd for scratch use */
61 unsigned long sc_rsvd[12]; /* reserved for future use */
62 /*
63 * The mask must come last so we can increase _NSIG_WORDS
64 * without breaking binary compatibility.
65 */
66 sigset_t sc_mask; /* signal mask to restore after handler returns */
67};
68
69# endif /* __ASSEMBLY__ */
70#endif /* _ASM_IA64_SIGCONTEXT_H */
diff --git a/arch/ia64/include/asm/siginfo.h b/arch/ia64/include/asm/siginfo.h
new file mode 100644
index 000000000000..9294e4b0c8bc
--- /dev/null
+++ b/arch/ia64/include/asm/siginfo.h
@@ -0,0 +1,139 @@
1#ifndef _ASM_IA64_SIGINFO_H
2#define _ASM_IA64_SIGINFO_H
3
4/*
5 * Based on <asm-i386/siginfo.h>.
6 *
7 * Modified 1998-2002
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
12
13#define HAVE_ARCH_SIGINFO_T
14#define HAVE_ARCH_COPY_SIGINFO
15#define HAVE_ARCH_COPY_SIGINFO_TO_USER
16
17#include <asm-generic/siginfo.h>
18
19typedef struct siginfo {
20 int si_signo;
21 int si_errno;
22 int si_code;
23 int __pad0;
24
25 union {
26 int _pad[SI_PAD_SIZE];
27
28 /* kill() */
29 struct {
30 pid_t _pid; /* sender's pid */
31 uid_t _uid; /* sender's uid */
32 } _kill;
33
34 /* POSIX.1b timers */
35 struct {
36 timer_t _tid; /* timer id */
37 int _overrun; /* overrun count */
38 char _pad[sizeof(__ARCH_SI_UID_T) - sizeof(int)];
39 sigval_t _sigval; /* must overlay ._rt._sigval! */
40 int _sys_private; /* not to be passed to user */
41 } _timer;
42
43 /* POSIX.1b signals */
44 struct {
45 pid_t _pid; /* sender's pid */
46 uid_t _uid; /* sender's uid */
47 sigval_t _sigval;
48 } _rt;
49
50 /* SIGCHLD */
51 struct {
52 pid_t _pid; /* which child */
53 uid_t _uid; /* sender's uid */
54 int _status; /* exit code */
55 clock_t _utime;
56 clock_t _stime;
57 } _sigchld;
58
59 /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
60 struct {
61 void __user *_addr; /* faulting insn/memory ref. */
62 int _imm; /* immediate value for "break" */
63 unsigned int _flags; /* see below */
64 unsigned long _isr; /* isr */
65 } _sigfault;
66
67 /* SIGPOLL */
68 struct {
69 long _band; /* POLL_IN, POLL_OUT, POLL_MSG (XPG requires a "long") */
70 int _fd;
71 } _sigpoll;
72 } _sifields;
73} siginfo_t;
74
75#define si_imm _sifields._sigfault._imm /* as per UNIX SysV ABI spec */
76#define si_flags _sifields._sigfault._flags
77/*
78 * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that
79 * si_code is non-zero and __ISR_VALID is set in si_flags.
80 */
81#define si_isr _sifields._sigfault._isr
82
83/*
84 * Flag values for si_flags:
85 */
86#define __ISR_VALID_BIT 0
87#define __ISR_VALID (1 << __ISR_VALID_BIT)
88
89/*
90 * SIGILL si_codes
91 */
92#define ILL_BADIADDR (__SI_FAULT|9) /* unimplemented instruction address */
93#define __ILL_BREAK (__SI_FAULT|10) /* illegal break */
94#define __ILL_BNDMOD (__SI_FAULT|11) /* bundle-update (modification) in progress */
95#undef NSIGILL
96#define NSIGILL 11
97
98/*
99 * SIGFPE si_codes
100 */
101#define __FPE_DECOVF (__SI_FAULT|9) /* decimal overflow */
102#define __FPE_DECDIV (__SI_FAULT|10) /* decimal division by zero */
103#define __FPE_DECERR (__SI_FAULT|11) /* packed decimal error */
104#define __FPE_INVASC (__SI_FAULT|12) /* invalid ASCII digit */
105#define __FPE_INVDEC (__SI_FAULT|13) /* invalid decimal digit */
106#undef NSIGFPE
107#define NSIGFPE 13
108
109/*
110 * SIGSEGV si_codes
111 */
112#define __SEGV_PSTKOVF (__SI_FAULT|3) /* paragraph stack overflow */
113#undef NSIGSEGV
114#define NSIGSEGV 3
115
116/*
117 * SIGTRAP si_codes
118 */
119#define TRAP_BRANCH (__SI_FAULT|3) /* process taken branch trap */
120#define TRAP_HWBKPT (__SI_FAULT|4) /* hardware breakpoint or watchpoint */
121#undef NSIGTRAP
122#define NSIGTRAP 4
123
124#ifdef __KERNEL__
125#include <linux/string.h>
126
127static inline void
128copy_siginfo (siginfo_t *to, siginfo_t *from)
129{
130 if (from->si_code < 0)
131 memcpy(to, from, sizeof(siginfo_t));
132 else
133 /* _sigchld is currently the largest know union member */
134 memcpy(to, from, 4*sizeof(int) + sizeof(from->_sifields._sigchld));
135}
136
137#endif /* __KERNEL__ */
138
139#endif /* _ASM_IA64_SIGINFO_H */
diff --git a/arch/ia64/include/asm/signal.h b/arch/ia64/include/asm/signal.h
new file mode 100644
index 000000000000..4f5ca5643cb1
--- /dev/null
+++ b/arch/ia64/include/asm/signal.h
@@ -0,0 +1,160 @@
1#ifndef _ASM_IA64_SIGNAL_H
2#define _ASM_IA64_SIGNAL_H
3
4/*
5 * Modified 1998-2001, 2003
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 *
8 * Unfortunately, this file is being included by bits/signal.h in
9 * glibc-2.x. Hence the #ifdef __KERNEL__ ugliness.
10 */
11
12#define SIGHUP 1
13#define SIGINT 2
14#define SIGQUIT 3
15#define SIGILL 4
16#define SIGTRAP 5
17#define SIGABRT 6
18#define SIGIOT 6
19#define SIGBUS 7
20#define SIGFPE 8
21#define SIGKILL 9
22#define SIGUSR1 10
23#define SIGSEGV 11
24#define SIGUSR2 12
25#define SIGPIPE 13
26#define SIGALRM 14
27#define SIGTERM 15
28#define SIGSTKFLT 16
29#define SIGCHLD 17
30#define SIGCONT 18
31#define SIGSTOP 19
32#define SIGTSTP 20
33#define SIGTTIN 21
34#define SIGTTOU 22
35#define SIGURG 23
36#define SIGXCPU 24
37#define SIGXFSZ 25
38#define SIGVTALRM 26
39#define SIGPROF 27
40#define SIGWINCH 28
41#define SIGIO 29
42#define SIGPOLL SIGIO
43/*
44#define SIGLOST 29
45*/
46#define SIGPWR 30
47#define SIGSYS 31
48/* signal 31 is no longer "unused", but the SIGUNUSED macro remains for backwards compatibility */
49#define SIGUNUSED 31
50
51/* These should not be considered constants from userland. */
52#define SIGRTMIN 32
53#define SIGRTMAX _NSIG
54
55/*
56 * SA_FLAGS values:
57 *
58 * SA_ONSTACK indicates that a registered stack_t will be used.
59 * SA_RESTART flag to get restarting signals (which were the default long ago)
60 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
61 * SA_RESETHAND clears the handler when the signal is delivered.
62 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
63 * SA_NODEFER prevents the current signal from being masked in the handler.
64 *
65 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
66 * Unix names RESETHAND and NODEFER respectively.
67 */
68#define SA_NOCLDSTOP 0x00000001
69#define SA_NOCLDWAIT 0x00000002
70#define SA_SIGINFO 0x00000004
71#define SA_ONSTACK 0x08000000
72#define SA_RESTART 0x10000000
73#define SA_NODEFER 0x40000000
74#define SA_RESETHAND 0x80000000
75
76#define SA_NOMASK SA_NODEFER
77#define SA_ONESHOT SA_RESETHAND
78
79#define SA_RESTORER 0x04000000
80
81/*
82 * sigaltstack controls
83 */
84#define SS_ONSTACK 1
85#define SS_DISABLE 2
86
87/*
88 * The minimum stack size needs to be fairly large because we want to
89 * be sure that an app compiled for today's CPUs will continue to run
90 * on all future CPU models. The CPU model matters because the signal
91 * frame needs to have space for the complete machine state, including
92 * all physical stacked registers. The number of physical stacked
93 * registers is CPU model dependent, but given that the width of
94 * ar.rsc.loadrs is 14 bits, we can assume that they'll never take up
95 * more than 16KB of space.
96 */
97#if 1
98 /*
99 * This is a stupid typo: the value was _meant_ to be 131072 (0x20000), but I typed it
100 * in wrong. ;-( To preserve backwards compatibility, we leave the kernel at the
101 * incorrect value and fix libc only.
102 */
103# define MINSIGSTKSZ 131027 /* min. stack size for sigaltstack() */
104#else
105# define MINSIGSTKSZ 131072 /* min. stack size for sigaltstack() */
106#endif
107#define SIGSTKSZ 262144 /* default stack size for sigaltstack() */
108
109#ifdef __KERNEL__
110
111#define _NSIG 64
112#define _NSIG_BPW 64
113#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
114
115#endif /* __KERNEL__ */
116
117#include <asm-generic/signal.h>
118
119# ifndef __ASSEMBLY__
120
121# include <linux/types.h>
122
123/* Avoid too many header ordering problems. */
124struct siginfo;
125
126typedef struct sigaltstack {
127 void __user *ss_sp;
128 int ss_flags;
129 size_t ss_size;
130} stack_t;
131
132#ifdef __KERNEL__
133
134/* Most things should be clean enough to redefine this at will, if care
135 is taken to make libc match. */
136
137typedef unsigned long old_sigset_t;
138
139typedef struct {
140 unsigned long sig[_NSIG_WORDS];
141} sigset_t;
142
143struct sigaction {
144 __sighandler_t sa_handler;
145 unsigned long sa_flags;
146 sigset_t sa_mask; /* mask last for extensibility */
147};
148
149struct k_sigaction {
150 struct sigaction sa;
151};
152
153# include <asm/sigcontext.h>
154
155#define ptrace_signal_deliver(regs, cookie) do { } while (0)
156
157#endif /* __KERNEL__ */
158
159# endif /* !__ASSEMBLY__ */
160#endif /* _ASM_IA64_SIGNAL_H */
diff --git a/arch/ia64/include/asm/smp.h b/arch/ia64/include/asm/smp.h
new file mode 100644
index 000000000000..12d96e0cd513
--- /dev/null
+++ b/arch/ia64/include/asm/smp.h
@@ -0,0 +1,138 @@
1/*
2 * SMP Support
3 *
4 * Copyright (C) 1999 VA Linux Systems
5 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
6 * (c) Copyright 2001-2003, 2005 Hewlett-Packard Development Company, L.P.
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * Bjorn Helgaas <bjorn.helgaas@hp.com>
9 */
10#ifndef _ASM_IA64_SMP_H
11#define _ASM_IA64_SMP_H
12
13#include <linux/init.h>
14#include <linux/threads.h>
15#include <linux/kernel.h>
16#include <linux/cpumask.h>
17#include <linux/bitops.h>
18#include <linux/irqreturn.h>
19
20#include <asm/io.h>
21#include <asm/param.h>
22#include <asm/processor.h>
23#include <asm/ptrace.h>
24
25static inline unsigned int
26ia64_get_lid (void)
27{
28 union {
29 struct {
30 unsigned long reserved : 16;
31 unsigned long eid : 8;
32 unsigned long id : 8;
33 unsigned long ignored : 32;
34 } f;
35 unsigned long bits;
36 } lid;
37
38 lid.bits = ia64_getreg(_IA64_REG_CR_LID);
39 return lid.f.id << 8 | lid.f.eid;
40}
41
42#define hard_smp_processor_id() ia64_get_lid()
43
44#ifdef CONFIG_SMP
45
46#define XTP_OFFSET 0x1e0008
47
48#define SMP_IRQ_REDIRECTION (1 << 0)
49#define SMP_IPI_REDIRECTION (1 << 1)
50
51#define raw_smp_processor_id() (current_thread_info()->cpu)
52
53extern struct smp_boot_data {
54 int cpu_count;
55 int cpu_phys_id[NR_CPUS];
56} smp_boot_data __initdata;
57
58extern char no_int_routing __devinitdata;
59
60extern cpumask_t cpu_online_map;
61extern cpumask_t cpu_core_map[NR_CPUS];
62DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
63extern int smp_num_siblings;
64extern void __iomem *ipi_base_addr;
65extern unsigned char smp_int_redirect;
66
67extern volatile int ia64_cpu_to_sapicid[];
68#define cpu_physical_id(i) ia64_cpu_to_sapicid[i]
69
70extern unsigned long ap_wakeup_vector;
71
72/*
73 * Function to map hard smp processor id to logical id. Slow, so don't use this in
74 * performance-critical code.
75 */
76static inline int
77cpu_logical_id (int cpuid)
78{
79 int i;
80
81 for (i = 0; i < NR_CPUS; ++i)
82 if (cpu_physical_id(i) == cpuid)
83 break;
84 return i;
85}
86
87/*
88 * XTP control functions:
89 * min_xtp : route all interrupts to this CPU
90 * normal_xtp: nominal XTP value
91 * max_xtp : never deliver interrupts to this CPU.
92 */
93
94static inline void
95min_xtp (void)
96{
97 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
98 writeb(0x00, ipi_base_addr + XTP_OFFSET); /* XTP to min */
99}
100
101static inline void
102normal_xtp (void)
103{
104 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
105 writeb(0x08, ipi_base_addr + XTP_OFFSET); /* XTP normal */
106}
107
108static inline void
109max_xtp (void)
110{
111 if (smp_int_redirect & SMP_IRQ_REDIRECTION)
112 writeb(0x0f, ipi_base_addr + XTP_OFFSET); /* Set XTP to max */
113}
114
115/* Upping and downing of CPUs */
116extern int __cpu_disable (void);
117extern void __cpu_die (unsigned int cpu);
118extern void cpu_die (void) __attribute__ ((noreturn));
119extern void __init smp_build_cpu_map(void);
120
121extern void __init init_smp_config (void);
122extern void smp_do_timer (struct pt_regs *regs);
123
124extern irqreturn_t handle_IPI(int irq, void *dev_id);
125extern void smp_send_reschedule (int cpu);
126extern void identify_siblings (struct cpuinfo_ia64 *);
127extern int is_multithreading_enabled(void);
128
129extern void arch_send_call_function_single_ipi(int cpu);
130extern void arch_send_call_function_ipi(cpumask_t mask);
131
132#else /* CONFIG_SMP */
133
134#define cpu_logical_id(i) 0
135#define cpu_physical_id(i) ia64_get_lid()
136
137#endif /* CONFIG_SMP */
138#endif /* _ASM_IA64_SMP_H */
diff --git a/arch/ia64/include/asm/sn/acpi.h b/arch/ia64/include/asm/sn/acpi.h
new file mode 100644
index 000000000000..9ce2801cbd57
--- /dev/null
+++ b/arch/ia64/include/asm/sn/acpi.h
@@ -0,0 +1,17 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ACPI_H
10#define _ASM_IA64_SN_ACPI_H
11
12#include "acpi/acglobal.h"
13
14extern int sn_acpi_rev;
15#define SN_ACPI_BASE_SUPPORT() (sn_acpi_rev >= 0x20101)
16
17#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/arch/ia64/include/asm/sn/addrs.h b/arch/ia64/include/asm/sn/addrs.h
new file mode 100644
index 000000000000..e715c794b186
--- /dev/null
+++ b/arch/ia64/include/asm/sn/addrs.h
@@ -0,0 +1,299 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_ADDRS_H
10#define _ASM_IA64_SN_ADDRS_H
11
12#include <asm/percpu.h>
13#include <asm/sn/types.h>
14#include <asm/sn/arch.h>
15#include <asm/sn/pda.h>
16
17/*
18 * Memory/SHUB Address Format:
19 * +-+---------+--+--------------+
20 * |0| NASID |AS| NodeOffset |
21 * +-+---------+--+--------------+
22 *
23 * NASID: (low NASID bit is 0) Memory and SHUB MMRs
24 * AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
25 * 00: Local Resources and MMR space
26 * Top bit of NodeOffset
27 * 0: Local resources space
28 * node id:
29 * 0: IA64/NT compatibility space
30 * 2: Local MMR Space
31 * 4: Local memory, regardless of local node id
32 * 1: Global MMR space
33 * 01: GET space.
34 * 10: AMO space.
35 * 11: Cacheable memory space.
36 *
37 * NodeOffset: byte offset
38 *
39 *
40 * TIO address format:
41 * +-+----------+--+--------------+
42 * |0| NASID |AS| Nodeoffset |
43 * +-+----------+--+--------------+
44 *
45 * NASID: (low NASID bit is 1) TIO
46 * AS: 2-bit Chiplet Identifier
47 * 00: TIO LB (Indicates TIO MMR access.)
48 * 01: TIO ICE (indicates coretalk space access.)
49 *
50 * NodeOffset: top bit must be set.
51 *
52 *
53 * Note that in both of the above address formats, the low
54 * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
55 */
56
57
58/*
59 * Define basic shift & mask constants for manipulating NASIDs and AS values.
60 */
61#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
62#define NASID_SHIFT (sn_hub_info->nasid_shift)
63#define AS_SHIFT (sn_hub_info->as_shift)
64#define AS_BITMASK 0x3UL
65
66#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
67#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
68
69
70/*
71 * AS values. These are the same on both SHUB1 & SHUB2.
72 */
73#define AS_GET_VAL 1UL
74#define AS_AMO_VAL 2UL
75#define AS_CAC_VAL 3UL
76#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
77#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
78#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
79
80
81/*
82 * Virtual Mode Local & Global MMR space.
83 */
84#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
85#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
86#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
87#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
88#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
89
90#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
91#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
92#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
93#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
94
95/*
96 * Physical mode addresses
97 */
98#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
99
100
101/*
102 * Clear region & AS bits.
103 */
104#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
105
106
107/*
108 * Misc NASID manipulation.
109 */
110#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
111#define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
112#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
113#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
114#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
115#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
116#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
117#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
118#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
119#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
120#define IS_TIO_NASID(n) ((n) & 1)
121
122
123/* non-II mmr's start at top of big window space (4G) */
124#define BWIN_TOP 0x0000000100000000UL
125
126/*
127 * general address defines
128 */
129#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
130#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
131#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
132#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
133
134/*
135 * Convert Memory addresses between various addressing modes.
136 */
137#define TO_PHYS(x) (TO_PHYS_MASK & (x))
138#define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
139#ifdef CONFIG_SGI_SN
140#define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
141#define TO_GET(x) (GET_BASE | TO_PHYS(x))
142#else
143#define TO_AMO(x) ({ BUG(); x; })
144#define TO_GET(x) ({ BUG(); x; })
145#endif
146
147/*
148 * Covert from processor physical address to II/TIO physical address:
149 * II - squeeze out the AS bits
150 * TIO- requires a chiplet id in bits 38-39. For DMA to memory,
151 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
152 * to insert a chiplet id into this macro. However, it is our belief
153 * right now that this chiplet id will be ICE, which is also zero.
154 */
155#define SH1_TIO_PHYS_TO_DMA(x) \
156 ((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
157
158#define SH2_NETWORK_BANK_OFFSET(x) \
159 ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
160
161#define SH2_NETWORK_BANK_SELECT(x) \
162 ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
163 >> (sn_hub_info->nasid_shift - 4)) << 36)
164
165#define SH2_NETWORK_ADDRESS(x) \
166 (SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
167
168#define SH2_TIO_PHYS_TO_DMA(x) \
169 (((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
170
171#define PHYS_TO_TIODMA(x) \
172 (is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
173
174#define PHYS_TO_DMA(x) \
175 ((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
176
177
178/*
179 * Macros to test for address type.
180 */
181#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
182#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
183
184
185/*
186 * The following definitions pertain to the IO special address
187 * space. They define the location of the big and little windows
188 * of any given node.
189 */
190#define BWIN_SIZE_BITS 29 /* big window size: 512M */
191#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
192#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
193 : RAW_NODE_SWIN_BASE(n, w))
194#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
195 ((u64) (w) << TIO_SWIN_SIZE_BITS))
196#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
197#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
198#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
199#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
200#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
201#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
202#define BWIN_WIDGET_MASK 0x7
203#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
204#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
205
206#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
207#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
208
209#define TIO_HWIN_SHIFT_BITS 33
210#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
211
212/*
213 * The following definitions pertain to the IO special address
214 * space. They define the location of the big and little windows
215 * of any given node.
216 */
217
218#define SWIN_SIZE_BITS 24
219#define SWIN_WIDGET_MASK 0xF
220
221#define TIO_SWIN_SIZE_BITS 28
222#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
223#define TIO_SWIN_WIDGET_MASK 0x3
224
225/*
226 * Convert smallwindow address to xtalk address.
227 *
228 * 'addr' can be physical or virtual address, but will be converted
229 * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
230 */
231#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
232#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
233
234
235/*
236 * The following macros produce the correct base virtual address for
237 * the hub registers. The REMOTE_HUB_* macro produce
238 * the address for the specified hub's registers. The intent is
239 * that the appropriate PI, MD, NI, or II register would be substituted
240 * for x.
241 *
242 * WARNING:
243 * When certain Hub chip workaround are defined, it's not sufficient
244 * to dereference the *_HUB_ADDR() macros. You should instead use
245 * HUB_L() and HUB_S() if you must deal with pointers to hub registers.
246 * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
247 * They're always safe.
248 */
249/* Shub1 TIO & MMR addressing macros */
250#define SH1_TIO_IOSPACE_ADDR(n,x) \
251 GLOBAL_MMR_ADDR(n,x)
252
253#define SH1_REMOTE_BWIN_MMR(n,x) \
254 GLOBAL_MMR_ADDR(n,x)
255
256#define SH1_REMOTE_SWIN_MMR(n,x) \
257 (NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
258
259#define SH1_REMOTE_MMR(n,x) \
260 (SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
261 SH1_REMOTE_SWIN_MMR(n,x))
262
263/* Shub1 TIO & MMR addressing macros */
264#define SH2_TIO_IOSPACE_ADDR(n,x) \
265 ((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
266
267#define SH2_REMOTE_MMR(n,x) \
268 GLOBAL_MMR_ADDR(n,x)
269
270
271/* TIO & MMR addressing macros that work on both shub1 & shub2 */
272#define TIO_IOSPACE_ADDR(n,x) \
273 ((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
274 SH2_TIO_IOSPACE_ADDR(n,x)))
275
276#define SH_REMOTE_MMR(n,x) \
277 (is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
278
279#define REMOTE_HUB_ADDR(n,x) \
280 (IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
281 ((volatile u64*)SH_REMOTE_MMR(n,x)))
282
283
284#define HUB_L(x) (*((volatile typeof(*x) *)x))
285#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
286
287#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
288#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
289
290/*
291 * Coretalk address breakdown
292 */
293#define CTALK_NASID_SHFT 40
294#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
295#define CTALK_CID_SHFT 38
296#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
297#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
298
299#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/arch/ia64/include/asm/sn/arch.h b/arch/ia64/include/asm/sn/arch.h
new file mode 100644
index 000000000000..7caa1f44cd95
--- /dev/null
+++ b/arch/ia64/include/asm/sn/arch.h
@@ -0,0 +1,86 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI specific setup.
7 *
8 * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
10 */
11#ifndef _ASM_IA64_SN_ARCH_H
12#define _ASM_IA64_SN_ARCH_H
13
14#include <linux/numa.h>
15#include <asm/types.h>
16#include <asm/percpu.h>
17#include <asm/sn/types.h>
18#include <asm/sn/sn_cpuid.h>
19
20/*
21 * This is the maximum number of NUMALINK nodes that can be part of a single
22 * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
23 * remote partitions are NOT included in this number.
24 * The number of compact nodes cannot exceed size of a coherency domain.
25 * The purpose of this define is to specify a node count that includes
26 * all C/M/TIO nodes in an SSI system.
27 *
28 * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
29 *
30 * Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
31 * to ACPI3.0, this limit will be removed. The notion of "compact nodes"
32 * should be deleted and TIOs should be included in MAX_NUMNODES.
33 */
34#define MAX_TIO_NODES MAX_NUMNODES
35#define MAX_COMPACT_NODES (MAX_NUMNODES + MAX_TIO_NODES)
36
37/*
38 * Maximum number of nodes in all partitions and in all coherency domains.
39 * This is the total number of nodes accessible in the numalink fabric. It
40 * includes all C & M bricks, plus all TIOs.
41 *
42 * This value is also the value of the maximum number of NASIDs in the numalink
43 * fabric.
44 */
45#define MAX_NUMALINK_NODES 16384
46
47/*
48 * The following defines attributes of the HUB chip. These attributes are
49 * frequently referenced. They are kept in the per-cpu data areas of each cpu.
50 * They are kept together in a struct to minimize cache misses.
51 */
52struct sn_hub_info_s {
53 u8 shub2;
54 u8 nasid_shift;
55 u8 as_shift;
56 u8 shub_1_1_found;
57 u16 nasid_bitmask;
58};
59DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
60#define sn_hub_info (&__get_cpu_var(__sn_hub_info))
61#define is_shub2() (sn_hub_info->shub2)
62#define is_shub1() (sn_hub_info->shub2 == 0)
63
64/*
65 * Use this macro to test if shub 1.1 wars should be enabled
66 */
67#define enable_shub_wars_1_1() (sn_hub_info->shub_1_1_found)
68
69
70/*
71 * Compact node ID to nasid mappings kept in the per-cpu data areas of each
72 * cpu.
73 */
74DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
75#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
76
77
78extern u8 sn_partition_id;
79extern u8 sn_system_size;
80extern u8 sn_sharing_domain_size;
81extern u8 sn_region_size;
82
83extern void sn_flush_all_caches(long addr, long bytes);
84extern bool sn_cpu_disable_allowed(int cpu);
85
86#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
new file mode 100644
index 000000000000..a0d214f43115
--- /dev/null
+++ b/arch/ia64/include/asm/sn/bte.h
@@ -0,0 +1,233 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9
10#ifndef _ASM_IA64_SN_BTE_H
11#define _ASM_IA64_SN_BTE_H
12
13#include <linux/timer.h>
14#include <linux/spinlock.h>
15#include <linux/cache.h>
16#include <asm/sn/pda.h>
17#include <asm/sn/types.h>
18#include <asm/sn/shub_mmr.h>
19
20#define IBCT_NOTIFY (0x1UL << 4)
21#define IBCT_ZFIL_MODE (0x1UL << 0)
22
23/* #define BTE_DEBUG */
24/* #define BTE_DEBUG_VERBOSE */
25
26#ifdef BTE_DEBUG
27# define BTE_PRINTK(x) printk x /* Terse */
28# ifdef BTE_DEBUG_VERBOSE
29# define BTE_PRINTKV(x) printk x /* Verbose */
30# else
31# define BTE_PRINTKV(x)
32# endif /* BTE_DEBUG_VERBOSE */
33#else
34# define BTE_PRINTK(x)
35# define BTE_PRINTKV(x)
36#endif /* BTE_DEBUG */
37
38
39/* BTE status register only supports 16 bits for length field */
40#define BTE_LEN_BITS (16)
41#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
42#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES)
43
44
45/* Define hardware */
46#define BTES_PER_NODE (is_shub2() ? 4 : 2)
47#define MAX_BTES_PER_NODE 4
48
49#define BTE2OFF_CTRL 0
50#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
51#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
52#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
53
54#define BTE_BASE_ADDR(interface) \
55 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
56 (interface == 1) ? SH2_BT_ENG_CSR_1 : \
57 (interface == 2) ? SH2_BT_ENG_CSR_2 : \
58 SH2_BT_ENG_CSR_3 \
59 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
60
61#define BTE_SOURCE_ADDR(base) \
62 (is_shub2() ? base + (BTE2OFF_SRC/8) \
63 : base + (BTEOFF_SRC/8))
64
65#define BTE_DEST_ADDR(base) \
66 (is_shub2() ? base + (BTE2OFF_DEST/8) \
67 : base + (BTEOFF_DEST/8))
68
69#define BTE_CTRL_ADDR(base) \
70 (is_shub2() ? base + (BTE2OFF_CTRL/8) \
71 : base + (BTEOFF_CTRL/8))
72
73#define BTE_NOTIF_ADDR(base) \
74 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
75 : base + (BTEOFF_NOTIFY/8))
76
77/* Define hardware modes */
78#define BTE_NOTIFY IBCT_NOTIFY
79#define BTE_NORMAL BTE_NOTIFY
80#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
81/* Use a reserved bit to let the caller specify a wait for any BTE */
82#define BTE_WACQUIRE 0x4000
83/* Use the BTE on the node with the destination memory */
84#define BTE_USE_DEST (BTE_WACQUIRE << 1)
85/* Use any available BTE interface on any node for the transfer */
86#define BTE_USE_ANY (BTE_USE_DEST << 1)
87/* macro to force the IBCT0 value valid */
88#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
89
90#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
91#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
92#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
93
94/*
95 * Some macros to simplify reading.
96 * Start with macros to locate the BTE control registers.
97 */
98#define BTE_LNSTAT_LOAD(_bte) \
99 HUB_L(_bte->bte_base_addr)
100#define BTE_LNSTAT_STORE(_bte, _x) \
101 HUB_S(_bte->bte_base_addr, (_x))
102#define BTE_SRC_STORE(_bte, _x) \
103({ \
104 u64 __addr = ((_x) & ~AS_MASK); \
105 if (is_shub2()) \
106 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
107 HUB_S(_bte->bte_source_addr, __addr); \
108})
109#define BTE_DEST_STORE(_bte, _x) \
110({ \
111 u64 __addr = ((_x) & ~AS_MASK); \
112 if (is_shub2()) \
113 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
114 HUB_S(_bte->bte_destination_addr, __addr); \
115})
116#define BTE_CTRL_STORE(_bte, _x) \
117 HUB_S(_bte->bte_control_addr, (_x))
118#define BTE_NOTIF_STORE(_bte, _x) \
119({ \
120 u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
121 if (is_shub2()) \
122 __addr = SH2_TIO_PHYS_TO_DMA(__addr); \
123 HUB_S(_bte->bte_notify_addr, __addr); \
124})
125
126#define BTE_START_TRANSFER(_bte, _len, _mode) \
127 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
128 : BTE_LNSTAT_STORE(_bte, _len); \
129 BTE_CTRL_STORE(_bte, _mode)
130
131/* Possible results from bte_copy and bte_unaligned_copy */
132/* The following error codes map into the BTE hardware codes
133 * IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
134 * an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
135 * to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
136 * codes to give the following error codes.
137 */
138#define BTEFAIL_OFFSET 1
139
140typedef enum {
141 BTE_SUCCESS, /* 0 is success */
142 BTEFAIL_DIR, /* Directory error due to IIO access*/
143 BTEFAIL_POISON, /* poison error on IO access (write to poison page) */
144 BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */
145 BTEFAIL_ACCESS, /* access error (protection violation) */
146 BTEFAIL_PWERR, /* Partial Write Error */
147 BTEFAIL_PRERR, /* Partial Read Error */
148 BTEFAIL_TOUT, /* CRB Time out */
149 BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */
150 BTEFAIL_NOTAVAIL, /* BTE not available */
151} bte_result_t;
152
153#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
154#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
155#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
156#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
157#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
158#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
159#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
160
161#define BTE_ERR_BITS 0x3FUL
162#define BTE_ERR_SHIFT 36
163#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
164
165#define BTE_ERROR_RETRY(value) \
166 (is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
167 : (value != BTEFAIL_TOUT))
168
169/*
170 * On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
171 */
172#define BTE_SHUB2_ERROR(_status) \
173 ((_status & BTE_ERR_MASK) \
174 ? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
175 : _status)
176
177#define BTE_GET_ERROR_STATUS(_status) \
178 (BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
179
180#define BTE_VALID_SH2_ERROR(value) \
181 ((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
182
183/*
184 * Structure defining a bte. An instance of this
185 * structure is created in the nodepda for each
186 * bte on that node (as defined by BTES_PER_NODE)
187 * This structure contains everything necessary
188 * to work with a BTE.
189 */
190struct bteinfo_s {
191 volatile u64 notify ____cacheline_aligned;
192 u64 *bte_base_addr ____cacheline_aligned;
193 u64 *bte_source_addr;
194 u64 *bte_destination_addr;
195 u64 *bte_control_addr;
196 u64 *bte_notify_addr;
197 spinlock_t spinlock;
198 cnodeid_t bte_cnode; /* cnode */
199 int bte_error_count; /* Number of errors encountered */
200 int bte_num; /* 0 --> BTE0, 1 --> BTE1 */
201 int cleanup_active; /* Interface is locked for cleanup */
202 volatile bte_result_t bh_error; /* error while processing */
203 volatile u64 *most_rcnt_na;
204 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
205};
206
207
208/*
209 * Function prototypes (functions defined in bte.c, used elsewhere)
210 */
211extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
212extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
213extern void bte_error_handler(unsigned long);
214
215#define bte_zero(dest, len, mode, notification) \
216 bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
217
218/*
219 * The following is the prefered way of calling bte_unaligned_copy
220 * If the copy is fully cache line aligned, then bte_copy is
221 * used instead. Since bte_copy is inlined, this saves a call
222 * stack. NOTE: bte_copy is called synchronously and does block
223 * until the transfer is complete. In order to get the asynch
224 * version of bte_copy, you must perform this check yourself.
225 */
226#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
227 (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \
228 (dest & L1_CACHE_MASK)) ? \
229 bte_unaligned_copy(src, dest, len, mode) : \
230 bte_copy(src, dest, len, mode, NULL))
231
232
233#endif /* _ASM_IA64_SN_BTE_H */
diff --git a/arch/ia64/include/asm/sn/clksupport.h b/arch/ia64/include/asm/sn/clksupport.h
new file mode 100644
index 000000000000..d340c365a824
--- /dev/null
+++ b/arch/ia64/include/asm/sn/clksupport.h
@@ -0,0 +1,28 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9/*
10 * This file contains definitions for accessing a platform supported high resolution
11 * clock. The clock is monitonically increasing and can be accessed from any node
12 * in the system. The clock is synchronized across nodes - all nodes see the
13 * same value.
14 *
15 * RTC_COUNTER_ADDR - contains the address of the counter
16 *
17 */
18
19#ifndef _ASM_IA64_SN_CLKSUPPORT_H
20#define _ASM_IA64_SN_CLKSUPPORT_H
21
22extern unsigned long sn_rtc_cycles_per_second;
23
24#define RTC_COUNTER_ADDR ((long *)LOCAL_MMR_ADDR(SH_RTC))
25
26#define rtc_time() (*RTC_COUNTER_ADDR)
27
28#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff --git a/arch/ia64/include/asm/sn/geo.h b/arch/ia64/include/asm/sn/geo.h
new file mode 100644
index 000000000000..f083c9434066
--- /dev/null
+++ b/arch/ia64/include/asm/sn/geo.h
@@ -0,0 +1,132 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_GEO_H
10#define _ASM_IA64_SN_GEO_H
11
12/* The geoid_t implementation below is based loosely on the pcfg_t
13 implementation in sys/SN/promcfg.h. */
14
15/* Type declaractions */
16
17/* Size of a geoid_t structure (must be before decl. of geoid_u) */
18#define GEOID_SIZE 8 /* Would 16 be better? The size can
19 be different on different platforms. */
20
21#define MAX_SLOTS 0xf /* slots per module */
22#define MAX_SLABS 0xf /* slabs per slot */
23
24typedef unsigned char geo_type_t;
25
26/* Fields common to all substructures */
27typedef struct geo_common_s {
28 moduleid_t module; /* The module (box) this h/w lives in */
29 geo_type_t type; /* What type of h/w is named by this geoid_t */
30 slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
31 slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
32} geo_common_t;
33
34/* Additional fields for particular types of hardware */
35typedef struct geo_node_s {
36 geo_common_t common; /* No additional fields needed */
37} geo_node_t;
38
39typedef struct geo_rtr_s {
40 geo_common_t common; /* No additional fields needed */
41} geo_rtr_t;
42
43typedef struct geo_iocntl_s {
44 geo_common_t common; /* No additional fields needed */
45} geo_iocntl_t;
46
47typedef struct geo_pcicard_s {
48 geo_iocntl_t common;
49 char bus; /* Bus/widget number */
50 char slot; /* PCI slot number */
51} geo_pcicard_t;
52
53/* Subcomponents of a node */
54typedef struct geo_cpu_s {
55 geo_node_t node;
56 char slice; /* Which CPU on the node */
57} geo_cpu_t;
58
59typedef struct geo_mem_s {
60 geo_node_t node;
61 char membus; /* The memory bus on the node */
62 char memslot; /* The memory slot on the bus */
63} geo_mem_t;
64
65
66typedef union geoid_u {
67 geo_common_t common;
68 geo_node_t node;
69 geo_iocntl_t iocntl;
70 geo_pcicard_t pcicard;
71 geo_rtr_t rtr;
72 geo_cpu_t cpu;
73 geo_mem_t mem;
74 char padsize[GEOID_SIZE];
75} geoid_t;
76
77
78/* Preprocessor macros */
79
80#define GEO_MAX_LEN 48 /* max. formatted length, plus some pad:
81 module/001c07/slab/5/node/memory/2/slot/4 */
82
83/* Values for geo_type_t */
84#define GEO_TYPE_INVALID 0
85#define GEO_TYPE_MODULE 1
86#define GEO_TYPE_NODE 2
87#define GEO_TYPE_RTR 3
88#define GEO_TYPE_IOCNTL 4
89#define GEO_TYPE_IOCARD 5
90#define GEO_TYPE_CPU 6
91#define GEO_TYPE_MEM 7
92#define GEO_TYPE_MAX (GEO_TYPE_MEM+1)
93
94/* Parameter for hwcfg_format_geoid_compt() */
95#define GEO_COMPT_MODULE 1
96#define GEO_COMPT_SLAB 2
97#define GEO_COMPT_IOBUS 3
98#define GEO_COMPT_IOSLOT 4
99#define GEO_COMPT_CPU 5
100#define GEO_COMPT_MEMBUS 6
101#define GEO_COMPT_MEMSLOT 7
102
103#define GEO_INVALID_STR "<invalid>"
104
105#define INVALID_NASID ((nasid_t)-1)
106#define INVALID_CNODEID ((cnodeid_t)-1)
107#define INVALID_PNODEID ((pnodeid_t)-1)
108#define INVALID_SLAB (slabid_t)-1
109#define INVALID_SLOT (slotid_t)-1
110#define INVALID_MODULE ((moduleid_t)-1)
111
112static inline slabid_t geo_slab(geoid_t g)
113{
114 return (g.common.type == GEO_TYPE_INVALID) ?
115 INVALID_SLAB : g.common.slab;
116}
117
118static inline slotid_t geo_slot(geoid_t g)
119{
120 return (g.common.type == GEO_TYPE_INVALID) ?
121 INVALID_SLOT : g.common.slot;
122}
123
124static inline moduleid_t geo_module(geoid_t g)
125{
126 return (g.common.type == GEO_TYPE_INVALID) ?
127 INVALID_MODULE : g.common.module;
128}
129
130extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
131
132#endif /* _ASM_IA64_SN_GEO_H */
diff --git a/arch/ia64/include/asm/sn/intr.h b/arch/ia64/include/asm/sn/intr.h
new file mode 100644
index 000000000000..e0487aa97418
--- /dev/null
+++ b/arch/ia64/include/asm/sn/intr.h
@@ -0,0 +1,68 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_INTR_H
10#define _ASM_IA64_SN_INTR_H
11
12#include <linux/rcupdate.h>
13#include <asm/sn/types.h>
14
15#define SGI_UART_VECTOR 0xe9
16
17/* Reserved IRQs : Note, not to exceed IA64_SN2_FIRST_DEVICE_VECTOR */
18#define SGI_XPC_ACTIVATE 0x30
19#define SGI_II_ERROR 0x31
20#define SGI_XBOW_ERROR 0x32
21#define SGI_PCIASIC_ERROR 0x33
22#define SGI_ACPI_SCI_INT 0x34
23#define SGI_TIOCA_ERROR 0x35
24#define SGI_TIO_ERROR 0x36
25#define SGI_TIOCX_ERROR 0x37
26#define SGI_MMTIMER_VECTOR 0x38
27#define SGI_XPC_NOTIFY 0xe7
28
29#define IA64_SN2_FIRST_DEVICE_VECTOR 0x3c
30#define IA64_SN2_LAST_DEVICE_VECTOR 0xe6
31
32#define SN2_IRQ_RESERVED 0x1
33#define SN2_IRQ_CONNECTED 0x2
34#define SN2_IRQ_SHARED 0x4
35
36// The SN PROM irq struct
37struct sn_irq_info {
38 struct sn_irq_info *irq_next; /* deprecated DO NOT USE */
39 short irq_nasid; /* Nasid IRQ is assigned to */
40 int irq_slice; /* slice IRQ is assigned to */
41 int irq_cpuid; /* kernel logical cpuid */
42 int irq_irq; /* the IRQ number */
43 int irq_int_bit; /* Bridge interrupt pin */
44 /* <0 means MSI */
45 u64 irq_xtalkaddr; /* xtalkaddr IRQ is sent to */
46 int irq_bridge_type;/* pciio asic type (pciio.h) */
47 void *irq_bridge; /* bridge generating irq */
48 void *irq_pciioinfo; /* associated pciio_info_t */
49 int irq_last_intr; /* For Shub lb lost intr WAR */
50 int irq_cookie; /* unique cookie */
51 int irq_flags; /* flags */
52 int irq_share_cnt; /* num devices sharing IRQ */
53 struct list_head list; /* list of sn_irq_info structs */
54 struct rcu_head rcu; /* rcu callback list */
55};
56
57extern void sn_send_IPI_phys(int, long, int, int);
58extern u64 sn_intr_alloc(nasid_t, int,
59 struct sn_irq_info *,
60 int, nasid_t, int);
61extern void sn_intr_free(nasid_t, int, struct sn_irq_info *);
62extern struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *, nasid_t, int);
63extern void sn_set_err_irq_affinity(unsigned int);
64extern struct list_head **sn_irq_lh;
65
66#define CPU_VECTOR_TO_IRQ(cpuid,vector) (vector)
67
68#endif /* _ASM_IA64_SN_INTR_H */
diff --git a/arch/ia64/include/asm/sn/io.h b/arch/ia64/include/asm/sn/io.h
new file mode 100644
index 000000000000..41c73a735628
--- /dev/null
+++ b/arch/ia64/include/asm/sn/io.h
@@ -0,0 +1,274 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_SN_IO_H
10#define _ASM_SN_IO_H
11#include <linux/compiler.h>
12#include <asm/intrinsics.h>
13
14extern void * sn_io_addr(unsigned long port) __attribute_const__; /* Forward definition */
15extern void __sn_mmiowb(void); /* Forward definition */
16
17extern int num_cnodes;
18
19#define __sn_mf_a() ia64_mfa()
20
21extern void sn_dma_flush(unsigned long);
22
23#define __sn_inb ___sn_inb
24#define __sn_inw ___sn_inw
25#define __sn_inl ___sn_inl
26#define __sn_outb ___sn_outb
27#define __sn_outw ___sn_outw
28#define __sn_outl ___sn_outl
29#define __sn_readb ___sn_readb
30#define __sn_readw ___sn_readw
31#define __sn_readl ___sn_readl
32#define __sn_readq ___sn_readq
33#define __sn_readb_relaxed ___sn_readb_relaxed
34#define __sn_readw_relaxed ___sn_readw_relaxed
35#define __sn_readl_relaxed ___sn_readl_relaxed
36#define __sn_readq_relaxed ___sn_readq_relaxed
37
38/*
39 * Convenience macros for setting/clearing bits using the above accessors
40 */
41
42#define __sn_setq_relaxed(addr, val) \
43 writeq((__sn_readq_relaxed(addr) | (val)), (addr))
44#define __sn_clrq_relaxed(addr, val) \
45 writeq((__sn_readq_relaxed(addr) & ~(val)), (addr))
46
47/*
48 * The following routines are SN Platform specific, called when
49 * a reference is made to inX/outX set macros. SN Platform
50 * inX set of macros ensures that Posted DMA writes on the
51 * Bridge is flushed.
52 *
53 * The routines should be self explainatory.
54 */
55
56static inline unsigned int
57___sn_inb (unsigned long port)
58{
59 volatile unsigned char *addr;
60 unsigned char ret = -1;
61
62 if ((addr = sn_io_addr(port))) {
63 ret = *addr;
64 __sn_mf_a();
65 sn_dma_flush((unsigned long)addr);
66 }
67 return ret;
68}
69
70static inline unsigned int
71___sn_inw (unsigned long port)
72{
73 volatile unsigned short *addr;
74 unsigned short ret = -1;
75
76 if ((addr = sn_io_addr(port))) {
77 ret = *addr;
78 __sn_mf_a();
79 sn_dma_flush((unsigned long)addr);
80 }
81 return ret;
82}
83
84static inline unsigned int
85___sn_inl (unsigned long port)
86{
87 volatile unsigned int *addr;
88 unsigned int ret = -1;
89
90 if ((addr = sn_io_addr(port))) {
91 ret = *addr;
92 __sn_mf_a();
93 sn_dma_flush((unsigned long)addr);
94 }
95 return ret;
96}
97
98static inline void
99___sn_outb (unsigned char val, unsigned long port)
100{
101 volatile unsigned char *addr;
102
103 if ((addr = sn_io_addr(port))) {
104 *addr = val;
105 __sn_mmiowb();
106 }
107}
108
109static inline void
110___sn_outw (unsigned short val, unsigned long port)
111{
112 volatile unsigned short *addr;
113
114 if ((addr = sn_io_addr(port))) {
115 *addr = val;
116 __sn_mmiowb();
117 }
118}
119
120static inline void
121___sn_outl (unsigned int val, unsigned long port)
122{
123 volatile unsigned int *addr;
124
125 if ((addr = sn_io_addr(port))) {
126 *addr = val;
127 __sn_mmiowb();
128 }
129}
130
131/*
132 * The following routines are SN Platform specific, called when
133 * a reference is made to readX/writeX set macros. SN Platform
134 * readX set of macros ensures that Posted DMA writes on the
135 * Bridge is flushed.
136 *
137 * The routines should be self explainatory.
138 */
139
140static inline unsigned char
141___sn_readb (const volatile void __iomem *addr)
142{
143 unsigned char val;
144
145 val = *(volatile unsigned char __force *)addr;
146 __sn_mf_a();
147 sn_dma_flush((unsigned long)addr);
148 return val;
149}
150
151static inline unsigned short
152___sn_readw (const volatile void __iomem *addr)
153{
154 unsigned short val;
155
156 val = *(volatile unsigned short __force *)addr;
157 __sn_mf_a();
158 sn_dma_flush((unsigned long)addr);
159 return val;
160}
161
162static inline unsigned int
163___sn_readl (const volatile void __iomem *addr)
164{
165 unsigned int val;
166
167 val = *(volatile unsigned int __force *)addr;
168 __sn_mf_a();
169 sn_dma_flush((unsigned long)addr);
170 return val;
171}
172
173static inline unsigned long
174___sn_readq (const volatile void __iomem *addr)
175{
176 unsigned long val;
177
178 val = *(volatile unsigned long __force *)addr;
179 __sn_mf_a();
180 sn_dma_flush((unsigned long)addr);
181 return val;
182}
183
184/*
185 * For generic and SN2 kernels, we have a set of fast access
186 * PIO macros. These macros are provided on SN Platform
187 * because the normal inX and readX macros perform an
188 * additional task of flushing Post DMA request on the Bridge.
189 *
190 * These routines should be self explainatory.
191 */
192
193static inline unsigned int
194sn_inb_fast (unsigned long port)
195{
196 volatile unsigned char *addr = (unsigned char *)port;
197 unsigned char ret;
198
199 ret = *addr;
200 __sn_mf_a();
201 return ret;
202}
203
204static inline unsigned int
205sn_inw_fast (unsigned long port)
206{
207 volatile unsigned short *addr = (unsigned short *)port;
208 unsigned short ret;
209
210 ret = *addr;
211 __sn_mf_a();
212 return ret;
213}
214
215static inline unsigned int
216sn_inl_fast (unsigned long port)
217{
218 volatile unsigned int *addr = (unsigned int *)port;
219 unsigned int ret;
220
221 ret = *addr;
222 __sn_mf_a();
223 return ret;
224}
225
226static inline unsigned char
227___sn_readb_relaxed (const volatile void __iomem *addr)
228{
229 return *(volatile unsigned char __force *)addr;
230}
231
232static inline unsigned short
233___sn_readw_relaxed (const volatile void __iomem *addr)
234{
235 return *(volatile unsigned short __force *)addr;
236}
237
238static inline unsigned int
239___sn_readl_relaxed (const volatile void __iomem *addr)
240{
241 return *(volatile unsigned int __force *) addr;
242}
243
244static inline unsigned long
245___sn_readq_relaxed (const volatile void __iomem *addr)
246{
247 return *(volatile unsigned long __force *) addr;
248}
249
250struct pci_dev;
251
252static inline int
253sn_pci_set_vchan(struct pci_dev *pci_dev, unsigned long *addr, int vchan)
254{
255
256 if (vchan > 1) {
257 return -1;
258 }
259
260 if (!(*addr >> 32)) /* Using a mask here would be cleaner */
261 return 0; /* but this generates better code */
262
263 if (vchan == 1) {
264 /* Set Bit 57 */
265 *addr |= (1UL << 57);
266 } else {
267 /* Clear Bit 57 */
268 *addr &= ~(1UL << 57);
269 }
270
271 return 0;
272}
273
274#endif /* _ASM_SN_IO_H */
diff --git a/arch/ia64/include/asm/sn/ioc3.h b/arch/ia64/include/asm/sn/ioc3.h
new file mode 100644
index 000000000000..95ed6cc83cf1
--- /dev/null
+++ b/arch/ia64/include/asm/sn/ioc3.h
@@ -0,0 +1,241 @@
1/*
2 * Copyright (C) 2005 Silicon Graphics, Inc.
3 */
4#ifndef IA64_SN_IOC3_H
5#define IA64_SN_IOC3_H
6
7/* serial port register map */
8struct ioc3_serialregs {
9 uint32_t sscr;
10 uint32_t stpir;
11 uint32_t stcir;
12 uint32_t srpir;
13 uint32_t srcir;
14 uint32_t srtr;
15 uint32_t shadow;
16};
17
18/* SUPERIO uart register map */
19struct ioc3_uartregs {
20 char iu_lcr;
21 union {
22 char iir; /* read only */
23 char fcr; /* write only */
24 } u3;
25 union {
26 char ier; /* DLAB == 0 */
27 char dlm; /* DLAB == 1 */
28 } u2;
29 union {
30 char rbr; /* read only, DLAB == 0 */
31 char thr; /* write only, DLAB == 0 */
32 char dll; /* DLAB == 1 */
33 } u1;
34 char iu_scr;
35 char iu_msr;
36 char iu_lsr;
37 char iu_mcr;
38};
39
40#define iu_rbr u1.rbr
41#define iu_thr u1.thr
42#define iu_dll u1.dll
43#define iu_ier u2.ier
44#define iu_dlm u2.dlm
45#define iu_iir u3.iir
46#define iu_fcr u3.fcr
47
48struct ioc3_sioregs {
49 char fill[0x170];
50 struct ioc3_uartregs uartb;
51 struct ioc3_uartregs uarta;
52};
53
54/* PCI IO/mem space register map */
55struct ioc3 {
56 uint32_t pci_id;
57 uint32_t pci_scr;
58 uint32_t pci_rev;
59 uint32_t pci_lat;
60 uint32_t pci_addr;
61 uint32_t pci_err_addr_l;
62 uint32_t pci_err_addr_h;
63
64 uint32_t sio_ir;
65 /* these registers are read-only for general kernel code. To
66 * modify them use the functions in ioc3.c
67 */
68 uint32_t sio_ies;
69 uint32_t sio_iec;
70 uint32_t sio_cr;
71 uint32_t int_out;
72 uint32_t mcr;
73 uint32_t gpcr_s;
74 uint32_t gpcr_c;
75 uint32_t gpdr;
76 uint32_t gppr[9];
77 char fill[0x4c];
78
79 /* serial port registers */
80 uint32_t sbbr_h;
81 uint32_t sbbr_l;
82
83 struct ioc3_serialregs port_a;
84 struct ioc3_serialregs port_b;
85 char fill1[0x1ff10];
86 /* superio registers */
87 struct ioc3_sioregs sregs;
88};
89
90/* These don't exist on the ioc3 serial card... */
91#define eier fill1[8]
92#define eisr fill1[4]
93
94#define PCI_LAT 0xc /* Latency Timer */
95#define PCI_SCR_DROP_MODE_EN 0x00008000 /* drop pios on parity err */
96#define UARTA_BASE 0x178
97#define UARTB_BASE 0x170
98
99
100/* bitmasks for serial RX status byte */
101#define RXSB_OVERRUN 0x01 /* char(s) lost */
102#define RXSB_PAR_ERR 0x02 /* parity error */
103#define RXSB_FRAME_ERR 0x04 /* framing error */
104#define RXSB_BREAK 0x08 /* break character */
105#define RXSB_CTS 0x10 /* state of CTS */
106#define RXSB_DCD 0x20 /* state of DCD */
107#define RXSB_MODEM_VALID 0x40 /* DCD, CTS and OVERRUN are valid */
108#define RXSB_DATA_VALID 0x80 /* FRAME_ERR PAR_ERR & BREAK valid */
109
110/* bitmasks for serial TX control byte */
111#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
112#define TXCB_INVALID 0x00 /* byte is invalid */
113#define TXCB_VALID 0x40 /* byte is valid */
114#define TXCB_MCR 0x80 /* data<7:0> to modem cntrl register */
115#define TXCB_DELAY 0xc0 /* delay data<7:0> mSec */
116
117/* bitmasks for SBBR_L */
118#define SBBR_L_SIZE 0x00000001 /* 0 1KB rings, 1 4KB rings */
119
120/* bitmasks for SSCR_<A:B> */
121#define SSCR_RX_THRESHOLD 0x000001ff /* hiwater mark */
122#define SSCR_TX_TIMER_BUSY 0x00010000 /* TX timer in progress */
123#define SSCR_HFC_EN 0x00020000 /* h/w flow cntrl enabled */
124#define SSCR_RX_RING_DCD 0x00040000 /* postRX record on delta-DCD */
125#define SSCR_RX_RING_CTS 0x00080000 /* postRX record on delta-CTS */
126#define SSCR_HIGH_SPD 0x00100000 /* 4X speed */
127#define SSCR_DIAG 0x00200000 /* bypass clock divider */
128#define SSCR_RX_DRAIN 0x08000000 /* drain RX buffer to memory */
129#define SSCR_DMA_EN 0x10000000 /* enable ring buffer DMA */
130#define SSCR_DMA_PAUSE 0x20000000 /* pause DMA */
131#define SSCR_PAUSE_STATE 0x40000000 /* set when PAUSE takes effect*/
132#define SSCR_RESET 0x80000000 /* reset DMA channels */
133
134/* all producer/comsumer pointers are the same bitfield */
135#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
136#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
137#define PROD_CONS_PTR_OFF 3
138
139/* bitmasks for SRCIR_<A:B> */
140#define SRCIR_ARM 0x80000000 /* arm RX timer */
141
142/* bitmasks for SHADOW_<A:B> */
143#define SHADOW_DR 0x00000001 /* data ready */
144#define SHADOW_OE 0x00000002 /* overrun error */
145#define SHADOW_PE 0x00000004 /* parity error */
146#define SHADOW_FE 0x00000008 /* framing error */
147#define SHADOW_BI 0x00000010 /* break interrupt */
148#define SHADOW_THRE 0x00000020 /* transmit holding reg empty */
149#define SHADOW_TEMT 0x00000040 /* transmit shift reg empty */
150#define SHADOW_RFCE 0x00000080 /* char in RX fifo has error */
151#define SHADOW_DCTS 0x00010000 /* delta clear to send */
152#define SHADOW_DDCD 0x00080000 /* delta data carrier detect */
153#define SHADOW_CTS 0x00100000 /* clear to send */
154#define SHADOW_DCD 0x00800000 /* data carrier detect */
155#define SHADOW_DTR 0x01000000 /* data terminal ready */
156#define SHADOW_RTS 0x02000000 /* request to send */
157#define SHADOW_OUT1 0x04000000 /* 16550 OUT1 bit */
158#define SHADOW_OUT2 0x08000000 /* 16550 OUT2 bit */
159#define SHADOW_LOOP 0x10000000 /* loopback enabled */
160
161/* bitmasks for SRTR_<A:B> */
162#define SRTR_CNT 0x00000fff /* reload value for RX timer */
163#define SRTR_CNT_VAL 0x0fff0000 /* current value of RX timer */
164#define SRTR_CNT_VAL_SHIFT 16
165#define SRTR_HZ 16000 /* SRTR clock frequency */
166
167/* bitmasks for SIO_IR, SIO_IEC and SIO_IES */
168#define SIO_IR_SA_TX_MT 0x00000001 /* Serial port A TX empty */
169#define SIO_IR_SA_RX_FULL 0x00000002 /* port A RX buf full */
170#define SIO_IR_SA_RX_HIGH 0x00000004 /* port A RX hiwat */
171#define SIO_IR_SA_RX_TIMER 0x00000008 /* port A RX timeout */
172#define SIO_IR_SA_DELTA_DCD 0x00000010 /* port A delta DCD */
173#define SIO_IR_SA_DELTA_CTS 0x00000020 /* port A delta CTS */
174#define SIO_IR_SA_INT 0x00000040 /* port A pass-thru intr */
175#define SIO_IR_SA_TX_EXPLICIT 0x00000080 /* port A explicit TX thru */
176#define SIO_IR_SA_MEMERR 0x00000100 /* port A PCI error */
177#define SIO_IR_SB_TX_MT 0x00000200
178#define SIO_IR_SB_RX_FULL 0x00000400
179#define SIO_IR_SB_RX_HIGH 0x00000800
180#define SIO_IR_SB_RX_TIMER 0x00001000
181#define SIO_IR_SB_DELTA_DCD 0x00002000
182#define SIO_IR_SB_DELTA_CTS 0x00004000
183#define SIO_IR_SB_INT 0x00008000
184#define SIO_IR_SB_TX_EXPLICIT 0x00010000
185#define SIO_IR_SB_MEMERR 0x00020000
186#define SIO_IR_PP_INT 0x00040000 /* P port pass-thru intr */
187#define SIO_IR_PP_INTA 0x00080000 /* PP context A thru */
188#define SIO_IR_PP_INTB 0x00100000 /* PP context B thru */
189#define SIO_IR_PP_MEMERR 0x00200000 /* PP PCI error */
190#define SIO_IR_KBD_INT 0x00400000 /* kbd/mouse intr */
191#define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
192#define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
193#define SIO_IR_GEN_INT_SHIFT 28
194
195/* per device interrupt masks */
196#define SIO_IR_SA (SIO_IR_SA_TX_MT | \
197 SIO_IR_SA_RX_FULL | \
198 SIO_IR_SA_RX_HIGH | \
199 SIO_IR_SA_RX_TIMER | \
200 SIO_IR_SA_DELTA_DCD | \
201 SIO_IR_SA_DELTA_CTS | \
202 SIO_IR_SA_INT | \
203 SIO_IR_SA_TX_EXPLICIT | \
204 SIO_IR_SA_MEMERR)
205
206#define SIO_IR_SB (SIO_IR_SB_TX_MT | \
207 SIO_IR_SB_RX_FULL | \
208 SIO_IR_SB_RX_HIGH | \
209 SIO_IR_SB_RX_TIMER | \
210 SIO_IR_SB_DELTA_DCD | \
211 SIO_IR_SB_DELTA_CTS | \
212 SIO_IR_SB_INT | \
213 SIO_IR_SB_TX_EXPLICIT | \
214 SIO_IR_SB_MEMERR)
215
216#define SIO_IR_PP (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
217 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
218#define SIO_IR_RT (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
219
220/* bitmasks for SIO_CR */
221#define SIO_CR_CMD_PULSE_SHIFT 15
222#define SIO_CR_SER_A_BASE_SHIFT 1
223#define SIO_CR_SER_B_BASE_SHIFT 8
224#define SIO_CR_ARB_DIAG 0x00380000 /* cur !enet PCI requet (ro) */
225#define SIO_CR_ARB_DIAG_TXA 0x00000000
226#define SIO_CR_ARB_DIAG_RXA 0x00080000
227#define SIO_CR_ARB_DIAG_TXB 0x00100000
228#define SIO_CR_ARB_DIAG_RXB 0x00180000
229#define SIO_CR_ARB_DIAG_PP 0x00200000
230#define SIO_CR_ARB_DIAG_IDLE 0x00400000 /* 0 -> active request (ro) */
231
232/* defs for some of the generic I/O pins */
233#define GPCR_PHY_RESET 0x20 /* pin is output to PHY reset */
234#define GPCR_UARTB_MODESEL 0x40 /* pin is output to port B mode sel */
235#define GPCR_UARTA_MODESEL 0x80 /* pin is output to port A mode sel */
236
237#define GPPR_PHY_RESET_PIN 5 /* GIO pin controlling phy reset */
238#define GPPR_UARTB_MODESEL_PIN 6 /* GIO pin cntrling uartb modeselect */
239#define GPPR_UARTA_MODESEL_PIN 7 /* GIO pin cntrling uarta modeselect */
240
241#endif /* IA64_SN_IOC3_H */
diff --git a/arch/ia64/include/asm/sn/klconfig.h b/arch/ia64/include/asm/sn/klconfig.h
new file mode 100644
index 000000000000..bcbf209d63be
--- /dev/null
+++ b/arch/ia64/include/asm/sn/klconfig.h
@@ -0,0 +1,246 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from IRIX <sys/SN/klconfig.h>.
7 *
8 * Copyright (C) 1992-1997,1999,2001-2004 Silicon Graphics, Inc. All Rights Reserved.
9 * Copyright (C) 1999 by Ralf Baechle
10 */
11#ifndef _ASM_IA64_SN_KLCONFIG_H
12#define _ASM_IA64_SN_KLCONFIG_H
13
14/*
15 * The KLCONFIG structures store info about the various BOARDs found
16 * during Hardware Discovery. In addition, it stores info about the
17 * components found on the BOARDs.
18 */
19
20typedef s32 klconf_off_t;
21
22
23/* Functions/macros needed to use this structure */
24
25typedef struct kl_config_hdr {
26 char pad[20];
27 klconf_off_t ch_board_info; /* the link list of boards */
28 char pad0[88];
29} kl_config_hdr_t;
30
31
32#define NODE_OFFSET_TO_LBOARD(nasid,off) (lboard_t*)(GLOBAL_CAC_ADDR((nasid), (off)))
33
34/*
35 * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
36 * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
37 * the LOCAL/current NODE. REMOTE means it is attached to a different
38 * node.(TBD - Need a way to treat ROUTER boards.)
39 *
40 * There are 2 different structures to represent these boards -
41 * lboard - Local board, rboard - remote board. These 2 structures
42 * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
43 * Figure below). The first byte of the rboard or lboard structure
44 * is used to find out its type - no unions are used.
45 * If it is a lboard, then the config info of this board will be found
46 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
47 * the structure.
48 * If it is a rboard, the local structure contains the node number
49 * and the offset of the beginning of the LINKED LIST on the remote node.
50 * The details of the hardware on a remote node can be built locally,
51 * if required, by reading the LINKED LIST on the remote node and
52 * ignoring all the rboards on that node.
53 *
54 * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
55 * First board info on the remote node. The remote node list is
56 * traversed as the local list, using the REMOTE BASE ADDRESS and not
57 * the local base address and ignoring all rboard values.
58 *
59 *
60 KLCONFIG
61
62 +------------+ +------------+ +------------+ +------------+
63 | lboard | +-->| lboard | +-->| rboard | +-->| lboard |
64 +------------+ | +------------+ | +------------+ | +------------+
65 | board info | | | board info | | |errinfo,bptr| | | board info |
66 +------------+ | +------------+ | +------------+ | +------------+
67 | offset |--+ | offset |--+ | offset |--+ |offset=NULL |
68 +------------+ +------------+ +------------+ +------------+
69
70
71 +------------+
72 | board info |
73 +------------+ +--------------------------------+
74 | compt 1 |------>| type, rev, diaginfo, size ... | (CPU)
75 +------------+ +--------------------------------+
76 | compt 2 |--+
77 +------------+ | +--------------------------------+
78 | ... | +--->| type, rev, diaginfo, size ... | (MEM_BANK)
79 +------------+ +--------------------------------+
80 | errinfo |--+
81 +------------+ | +--------------------------------+
82 +--->|r/l brd errinfo,compt err flags |
83 +--------------------------------+
84
85 *
86 * Each BOARD consists of COMPONENTs and the BOARD structure has
87 * pointers (offsets) to its COMPONENT structure.
88 * The COMPONENT structure has version info, size and speed info, revision,
89 * error info and the NIC info. This structure can accommodate any
90 * BOARD with arbitrary COMPONENT composition.
91 *
92 * The ERRORINFO part of each BOARD has error information
93 * that describes errors about the BOARD itself. It also has flags to
94 * indicate the COMPONENT(s) on the board that have errors. The error
95 * information specific to the COMPONENT is present in the respective
96 * COMPONENT structure.
97 *
98 * The ERRORINFO structure is also treated like a COMPONENT, ie. the
99 * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
100 * structure also has a pointer to the ERRORINFO structure. This is
101 * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
102 * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
103 * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
104 * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
105 * which is present on the REMOTE NODE.(TBD)
106 * REMOTE ERRINFO can be stored on any of the nearest nodes
107 * or on all the nearest nodes.(TBD)
108 * Like BOARD structures, REMOTE ERRINFO structures can be built locally
109 * using the rboard errinfo pointer.
110 *
111 * In order to get useful information from this Data organization, a set of
112 * interface routines are provided (TBD). The important thing to remember while
113 * manipulating the structures, is that, the NODE number information should
114 * be used. If the NODE is non-zero (remote) then each offset should
115 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
116 * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
117 *
118 * Note that these structures do not provide much info about connectivity.
119 * That info will be part of HWGRAPH, which is an extension of the cfg_t
120 * data structure. (ref IP27prom/cfg.h) It has to be extended to include
121 * the IO part of the Network(TBD).
122 *
123 * The data structures below define the above concepts.
124 */
125
126
127/*
128 * BOARD classes
129 */
130
131#define KLCLASS_MASK 0xf0
132#define KLCLASS_NONE 0x00
133#define KLCLASS_NODE 0x10 /* CPU, Memory and HUB board */
134#define KLCLASS_CPU KLCLASS_NODE
135#define KLCLASS_IO 0x20 /* BaseIO, 4 ch SCSI, ethernet, FDDI
136 and the non-graphics widget boards */
137#define KLCLASS_ROUTER 0x30 /* Router board */
138#define KLCLASS_MIDPLANE 0x40 /* We need to treat this as a board
139 so that we can record error info */
140#define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */
141#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */
142
143#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
144
145
146/*
147 * board types
148 */
149
150#define KLTYPE_MASK 0x0f
151#define KLTYPE(_x) ((_x) & KLTYPE_MASK)
152
153#define KLTYPE_SNIA (KLCLASS_CPU | 0x1)
154#define KLTYPE_TIO (KLCLASS_CPU | 0x2)
155
156#define KLTYPE_ROUTER (KLCLASS_ROUTER | 0x1)
157#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
158#define KLTYPE_REPEATER_ROUTER (KLCLASS_ROUTER | 0x4)
159
160#define KLTYPE_IOBRICK_XBOW (KLCLASS_MIDPLANE | 0x2)
161
162#define KLTYPE_IOBRICK (KLCLASS_IOBRICK | 0x0)
163#define KLTYPE_NBRICK (KLCLASS_IOBRICK | 0x4)
164#define KLTYPE_PXBRICK (KLCLASS_IOBRICK | 0x6)
165#define KLTYPE_IXBRICK (KLCLASS_IOBRICK | 0x7)
166#define KLTYPE_CGBRICK (KLCLASS_IOBRICK | 0x8)
167#define KLTYPE_OPUSBRICK (KLCLASS_IOBRICK | 0x9)
168#define KLTYPE_SABRICK (KLCLASS_IOBRICK | 0xa)
169#define KLTYPE_IABRICK (KLCLASS_IOBRICK | 0xb)
170#define KLTYPE_PABRICK (KLCLASS_IOBRICK | 0xc)
171#define KLTYPE_GABRICK (KLCLASS_IOBRICK | 0xd)
172
173
174/*
175 * board structures
176 */
177
178#define MAX_COMPTS_PER_BRD 24
179
180typedef struct lboard_s {
181 klconf_off_t brd_next_any; /* Next BOARD */
182 unsigned char struct_type; /* type of structure, local or remote */
183 unsigned char brd_type; /* type+class */
184 unsigned char brd_sversion; /* version of this structure */
185 unsigned char brd_brevision; /* board revision */
186 unsigned char brd_promver; /* board prom version, if any */
187 unsigned char brd_flags; /* Enabled, Disabled etc */
188 unsigned char brd_slot; /* slot number */
189 unsigned short brd_debugsw; /* Debug switches */
190 geoid_t brd_geoid; /* geo id */
191 partid_t brd_partition; /* Partition number */
192 unsigned short brd_diagval; /* diagnostic value */
193 unsigned short brd_diagparm; /* diagnostic parameter */
194 unsigned char brd_inventory; /* inventory history */
195 unsigned char brd_numcompts; /* Number of components */
196 nic_t brd_nic; /* Number in CAN */
197 nasid_t brd_nasid; /* passed parameter */
198 klconf_off_t brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
199 klconf_off_t brd_errinfo; /* Board's error information */
200 struct lboard_s *brd_parent; /* Logical parent for this brd */
201 char pad0[4];
202 unsigned char brd_confidence; /* confidence that the board is bad */
203 nasid_t brd_owner; /* who owns this board */
204 unsigned char brd_nic_flags; /* To handle 8 more NICs */
205 char pad1[24]; /* future expansion */
206 char brd_name[32];
207 nasid_t brd_next_same_host; /* host of next brd w/same nasid */
208 klconf_off_t brd_next_same; /* Next BOARD with same nasid */
209} lboard_t;
210
211/*
212 * Generic info structure. This stores common info about a
213 * component.
214 */
215
216typedef struct klinfo_s { /* Generic info */
217 unsigned char struct_type; /* type of this structure */
218 unsigned char struct_version; /* version of this structure */
219 unsigned char flags; /* Enabled, disabled etc */
220 unsigned char revision; /* component revision */
221 unsigned short diagval; /* result of diagnostics */
222 unsigned short diagparm; /* diagnostic parameter */
223 unsigned char inventory; /* previous inventory status */
224 unsigned short partid; /* widget part number */
225 nic_t nic; /* MUst be aligned properly */
226 unsigned char physid; /* physical id of component */
227 unsigned int virtid; /* virtual id as seen by system */
228 unsigned char widid; /* Widget id - if applicable */
229 nasid_t nasid; /* node number - from parent */
230 char pad1; /* pad out structure. */
231 char pad2; /* pad out structure. */
232 void *data;
233 klconf_off_t errinfo; /* component specific errors */
234 unsigned short pad3; /* pci fields have moved over to */
235 unsigned short pad4; /* klbri_t */
236} klinfo_t ;
237
238
239static inline lboard_t *find_lboard_next(lboard_t * brd)
240{
241 if (brd && brd->brd_next_any)
242 return NODE_OFFSET_TO_LBOARD(NASID_GET(brd), brd->brd_next_any);
243 return NULL;
244}
245
246#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff --git a/arch/ia64/include/asm/sn/l1.h b/arch/ia64/include/asm/sn/l1.h
new file mode 100644
index 000000000000..344bf44bb356
--- /dev/null
+++ b/arch/ia64/include/asm/sn/l1.h
@@ -0,0 +1,51 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All Rights Reserved.
7 */
8
9#ifndef _ASM_IA64_SN_L1_H
10#define _ASM_IA64_SN_L1_H
11
12/* brick type response codes */
13#define L1_BRICKTYPE_PX 0x23 /* # */
14#define L1_BRICKTYPE_PE 0x25 /* % */
15#define L1_BRICKTYPE_N_p0 0x26 /* & */
16#define L1_BRICKTYPE_IP45 0x34 /* 4 */
17#define L1_BRICKTYPE_IP41 0x35 /* 5 */
18#define L1_BRICKTYPE_TWISTER 0x36 /* 6 */ /* IP53 & ROUTER */
19#define L1_BRICKTYPE_IX 0x3d /* = */
20#define L1_BRICKTYPE_IP34 0x61 /* a */
21#define L1_BRICKTYPE_GA 0x62 /* b */
22#define L1_BRICKTYPE_C 0x63 /* c */
23#define L1_BRICKTYPE_OPUS_TIO 0x66 /* f */
24#define L1_BRICKTYPE_I 0x69 /* i */
25#define L1_BRICKTYPE_N 0x6e /* n */
26#define L1_BRICKTYPE_OPUS 0x6f /* o */
27#define L1_BRICKTYPE_P 0x70 /* p */
28#define L1_BRICKTYPE_R 0x72 /* r */
29#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
30#define L1_BRICKTYPE_X 0x78 /* x */
31#define L1_BRICKTYPE_X2 0x79 /* y */
32#define L1_BRICKTYPE_SA 0x5e /* ^ */
33#define L1_BRICKTYPE_PA 0x6a /* j */
34#define L1_BRICKTYPE_IA 0x6b /* k */
35#define L1_BRICKTYPE_ATHENA 0x2b /* + */
36#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
37#define L1_BRICKTYPE_1932 0x2c /* . */
38#define L1_BRICKTYPE_191010 0x2e /* , */
39
40/* board type response codes */
41#define L1_BOARDTYPE_IP69 0x0100 /* CA */
42#define L1_BOARDTYPE_IP63 0x0200 /* CB */
43#define L1_BOARDTYPE_BASEIO 0x0300 /* IB */
44#define L1_BOARDTYPE_PCIE2SLOT 0x0400 /* IC */
45#define L1_BOARDTYPE_PCIX3SLOT 0x0500 /* ID */
46#define L1_BOARDTYPE_PCIXPCIE4SLOT 0x0600 /* IE */
47#define L1_BOARDTYPE_ABACUS 0x0700 /* AB */
48#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
49#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
50
51#endif /* _ASM_IA64_SN_L1_H */
diff --git a/arch/ia64/include/asm/sn/leds.h b/arch/ia64/include/asm/sn/leds.h
new file mode 100644
index 000000000000..66cf8c4d92c9
--- /dev/null
+++ b/arch/ia64/include/asm/sn/leds.h
@@ -0,0 +1,33 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7#ifndef _ASM_IA64_SN_LEDS_H
8#define _ASM_IA64_SN_LEDS_H
9
10#include <asm/sn/addrs.h>
11#include <asm/sn/pda.h>
12#include <asm/sn/shub_mmr.h>
13
14#define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
15#define LED_CPU_SHIFT 16
16
17#define LED_CPU_HEARTBEAT 0x01
18#define LED_CPU_ACTIVITY 0x02
19#define LED_ALWAYS_SET 0x00
20
21/*
22 * Basic macros for flashing the LEDS on an SGI SN.
23 */
24
25static __inline__ void
26set_led_bits(u8 value, u8 mask)
27{
28 pda->led_state = (pda->led_state & ~mask) | (value & mask);
29 *pda->led_address = (short) pda->led_state;
30}
31
32#endif /* _ASM_IA64_SN_LEDS_H */
33
diff --git a/arch/ia64/include/asm/sn/module.h b/arch/ia64/include/asm/sn/module.h
new file mode 100644
index 000000000000..734e980ece2f
--- /dev/null
+++ b/arch/ia64/include/asm/sn/module.h
@@ -0,0 +1,127 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_MODULE_H
9#define _ASM_IA64_SN_MODULE_H
10
11/* parameter for format_module_id() */
12#define MODULE_FORMAT_BRIEF 1
13#define MODULE_FORMAT_LONG 2
14#define MODULE_FORMAT_LCD 3
15
16/*
17 * Module id format
18 *
19 * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int)
20 * 15-8 Brick type (8-bit ascii character)
21 * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int)
22 *
23 */
24
25/*
26 * Macros for getting the brick type
27 */
28#define MODULE_BTYPE_MASK 0xff00
29#define MODULE_BTYPE_SHFT 8
30#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT)
31#define MODULE_BT_TO_CHAR(_b) ((char)(_b))
32#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m)))
33
34/*
35 * Macros for getting the rack ID.
36 */
37#define MODULE_RACK_MASK 0xffff0000
38#define MODULE_RACK_SHFT 16
39#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT)
40
41/*
42 * Macros for getting the brick position
43 */
44#define MODULE_BPOS_MASK 0x00ff
45#define MODULE_BPOS_SHFT 0
46#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT)
47
48/*
49 * Macros for encoding and decoding rack IDs
50 * A rack number consists of three parts:
51 * class (0==CPU/mixed, 1==I/O), group, number
52 *
53 * Rack number is stored just as it is displayed on the screen:
54 * a 3-decimal-digit number.
55 */
56#define RACK_CLASS_DVDR 100
57#define RACK_GROUP_DVDR 10
58#define RACK_NUM_DVDR 1
59
60#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \
61 (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR)
62
63#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR)
64#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \
65 RACK_CLASS_DVDR) / RACK_GROUP_DVDR)
66#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \
67 RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \
68 RACK_GROUP_DVDR) / RACK_NUM_DVDR)
69
70/*
71 * Macros for encoding and decoding rack IDs
72 * A rack number consists of three parts:
73 * class 1 bit, 0==CPU/mixed, 1==I/O
74 * group 2 bits for CPU/mixed, 3 bits for I/O
75 * number 3 bits for CPU/mixed, 2 bits for I/O (1 based)
76 */
77#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2)
78#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3)
79
80#define RACK_CLASS_MASK(_r) 0x20
81#define RACK_CLASS_SHFT(_r) 5
82#define RACK_ADD_CLASS(_r, _c) \
83 ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r))
84
85#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r)
86#define RACK_GROUP_MASK(_r) \
87 ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) )
88#define RACK_ADD_GROUP(_r, _g) \
89 ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r))
90
91#define RACK_NUM_SHFT(_r) 0
92#define RACK_NUM_MASK(_r) \
93 ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) )
94#define RACK_ADD_NUM(_r, _n) \
95 ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r))
96
97
98/*
99 * Brick type definitions
100 */
101#define MAX_BRICK_TYPES 256 /* brick type is stored as uchar */
102
103extern char brick_types[];
104
105#define MODULE_CBRICK 0
106#define MODULE_RBRICK 1
107#define MODULE_IBRICK 2
108#define MODULE_KBRICK 3
109#define MODULE_XBRICK 4
110#define MODULE_DBRICK 5
111#define MODULE_PBRICK 6
112#define MODULE_NBRICK 7
113#define MODULE_PEBRICK 8
114#define MODULE_PXBRICK 9
115#define MODULE_IXBRICK 10
116#define MODULE_CGBRICK 11
117#define MODULE_OPUSBRICK 12
118#define MODULE_SABRICK 13 /* TIO BringUp Brick */
119#define MODULE_IABRICK 14
120#define MODULE_PABRICK 15
121#define MODULE_GABRICK 16
122#define MODULE_OPUS_TIO 17 /* OPUS TIO Riser */
123
124extern char brick_types[];
125extern void format_module_id(char *, moduleid_t, int);
126
127#endif /* _ASM_IA64_SN_MODULE_H */
diff --git a/arch/ia64/include/asm/sn/mspec.h b/arch/ia64/include/asm/sn/mspec.h
new file mode 100644
index 000000000000..c1d3c50c3223
--- /dev/null
+++ b/arch/ia64/include/asm/sn/mspec.h
@@ -0,0 +1,59 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2008 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_MSPEC_H
11#define _ASM_IA64_SN_MSPEC_H
12
13#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
14
15#define FETCHOP_LOAD 0
16#define FETCHOP_INCREMENT 8
17#define FETCHOP_DECREMENT 16
18#define FETCHOP_CLEAR 24
19
20#define FETCHOP_STORE 0
21#define FETCHOP_AND 24
22#define FETCHOP_OR 32
23
24#define FETCHOP_CLEAR_CACHE 56
25
26#define FETCHOP_LOAD_OP(addr, op) ( \
27 *(volatile long *)((char*) (addr) + (op)))
28
29#define FETCHOP_STORE_OP(addr, op, x) ( \
30 *(volatile long *)((char*) (addr) + (op)) = (long) (x))
31
32#ifdef __KERNEL__
33
34/*
35 * Each Atomic Memory Operation (amo, formerly known as fetchop)
36 * variable is 64 bytes long. The first 8 bytes are used. The
37 * remaining 56 bytes are unaddressable due to the operation taking
38 * that portion of the address.
39 *
40 * NOTE: The amo structure _MUST_ be placed in either the first or second
41 * half of the cache line. The cache line _MUST NOT_ be used for anything
42 * other than additional amo entries. This is because there are two
43 * addresses which reference the same physical cache line. One will
44 * be a cached entry with the memory type bits all set. This address
45 * may be loaded into processor cache. The amo will be referenced
46 * uncached via the memory special memory type. If any portion of the
47 * cached cache-line is modified, when that line is flushed, it will
48 * overwrite the uncached value in physical memory and lead to
49 * inconsistency.
50 */
51struct amo {
52 u64 variable;
53 u64 unused[7];
54};
55
56
57#endif /* __KERNEL__ */
58
59#endif /* _ASM_IA64_SN_MSPEC_H */
diff --git a/arch/ia64/include/asm/sn/nodepda.h b/arch/ia64/include/asm/sn/nodepda.h
new file mode 100644
index 000000000000..ee118b901de4
--- /dev/null
+++ b/arch/ia64/include/asm/sn/nodepda.h
@@ -0,0 +1,82 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_NODEPDA_H
9#define _ASM_IA64_SN_NODEPDA_H
10
11
12#include <asm/irq.h>
13#include <asm/sn/arch.h>
14#include <asm/sn/intr.h>
15#include <asm/sn/bte.h>
16
17/*
18 * NUMA Node-Specific Data structures are defined in this file.
19 * In particular, this is the location of the node PDA.
20 * A pointer to the right node PDA is saved in each CPU PDA.
21 */
22
23/*
24 * Node-specific data structure.
25 *
26 * One of these structures is allocated on each node of a NUMA system.
27 *
28 * This structure provides a convenient way of keeping together
29 * all per-node data structures.
30 */
31struct phys_cpuid {
32 short nasid;
33 char subnode;
34 char slice;
35};
36
37struct nodepda_s {
38 void *pdinfo; /* Platform-dependent per-node info */
39
40 /*
41 * The BTEs on this node are shared by the local cpus
42 */
43 struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
44 struct timer_list bte_recovery_timer;
45 spinlock_t bte_recovery_lock;
46
47 /*
48 * Array of pointers to the nodepdas for each node.
49 */
50 struct nodepda_s *pernode_pdaindr[MAX_COMPACT_NODES];
51
52 /*
53 * Array of physical cpu identifiers. Indexed by cpuid.
54 */
55 struct phys_cpuid phys_cpuid[NR_CPUS];
56 spinlock_t ptc_lock ____cacheline_aligned_in_smp;
57};
58
59typedef struct nodepda_s nodepda_t;
60
61/*
62 * Access Functions for node PDA.
63 * Since there is one nodepda for each node, we need a convenient mechanism
64 * to access these nodepdas without cluttering code with #ifdefs.
65 * The next set of definitions provides this.
66 * Routines are expected to use
67 *
68 * sn_nodepda - to access node PDA for the node on which code is running
69 * NODEPDA(cnodeid) - to access node PDA for cnodeid
70 */
71
72DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
73#define sn_nodepda (__get_cpu_var(__sn_nodepda))
74#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid])
75
76/*
77 * Check if given a compact node id the corresponding node has all the
78 * cpus disabled.
79 */
80#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0)
81
82#endif /* _ASM_IA64_SN_NODEPDA_H */
diff --git a/arch/ia64/include/asm/sn/pcibr_provider.h b/arch/ia64/include/asm/sn/pcibr_provider.h
new file mode 100644
index 000000000000..da205b7cdaac
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcibr_provider.h
@@ -0,0 +1,150 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992-1997,2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
10
11#include <asm/sn/intr.h>
12#include <asm/sn/pcibus_provider_defs.h>
13
14/* Workarounds */
15#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
16
17#define BUSTYPE_MASK 0x1
18
19/* Macros given a pcibus structure */
20#define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
21#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
22 asic == PCIIO_ASIC_TYPE_TIOCP)
23#define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
24#define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP)
25
26
27/*
28 * The different PCI Bridge types supported on the SGI Altix platforms
29 */
30#define PCIBR_BRIDGETYPE_UNKNOWN -1
31#define PCIBR_BRIDGETYPE_PIC 2
32#define PCIBR_BRIDGETYPE_TIOCP 3
33
34/*
35 * Bridge 64bit Direct Map Attributes
36 */
37#define PCI64_ATTR_PREF (1ull << 59)
38#define PCI64_ATTR_PREC (1ull << 58)
39#define PCI64_ATTR_VIRTUAL (1ull << 57)
40#define PCI64_ATTR_BAR (1ull << 56)
41#define PCI64_ATTR_SWAP (1ull << 55)
42#define PCI64_ATTR_VIRTUAL1 (1ull << 54)
43
44#define PCI32_LOCAL_BASE 0
45#define PCI32_MAPPED_BASE 0x40000000
46#define PCI32_DIRECT_BASE 0x80000000
47
48#define IS_PCI32_MAPPED(x) ((u64)(x) < PCI32_DIRECT_BASE && \
49 (u64)(x) >= PCI32_MAPPED_BASE)
50#define IS_PCI32_DIRECT(x) ((u64)(x) >= PCI32_MAPPED_BASE)
51
52
53/*
54 * Bridge PMU Address Transaltion Entry Attibutes
55 */
56#define PCI32_ATE_V (0x1 << 0)
57#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */
58#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */
59#define PCI32_ATE_MSI (0x1 << 2)
60#define PCI32_ATE_PREF (0x1 << 3)
61#define PCI32_ATE_BAR (0x1 << 4)
62#define PCI32_ATE_ADDR_SHFT 12
63
64#define MINIMAL_ATES_REQUIRED(addr, size) \
65 (IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
66
67#define MINIMAL_ATE_FLAG(addr, size) \
68 (MINIMAL_ATES_REQUIRED((u64)addr, size) ? 1 : 0)
69
70/* bit 29 of the pci address is the SWAP bit */
71#define ATE_SWAPSHIFT 29
72#define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT))
73#define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT))
74
75/*
76 * I/O page size
77 */
78#if PAGE_SIZE < 16384
79#define IOPFNSHIFT 12 /* 4K per mapped page */
80#else
81#define IOPFNSHIFT 14 /* 16K per mapped page */
82#endif
83
84#define IOPGSIZE (1 << IOPFNSHIFT)
85#define IOPG(x) ((x) >> IOPFNSHIFT)
86#define IOPGOFF(x) ((x) & (IOPGSIZE-1))
87
88#define PCIBR_DEV_SWAP_DIR (1ull << 19)
89#define PCIBR_CTRL_PAGE_SIZE (0x1 << 21)
90
91/*
92 * PMU resources.
93 */
94struct ate_resource{
95 u64 *ate;
96 u64 num_ate;
97 u64 lowest_free_index;
98};
99
100struct pcibus_info {
101 struct pcibus_bussoft pbi_buscommon; /* common header */
102 u32 pbi_moduleid;
103 short pbi_bridge_type;
104 short pbi_bridge_mode;
105
106 struct ate_resource pbi_int_ate_resource;
107 u64 pbi_int_ate_size;
108
109 u64 pbi_dir_xbase;
110 char pbi_hub_xid;
111
112 u64 pbi_devreg[8];
113
114 u32 pbi_valid_devices;
115 u32 pbi_enabled_devices;
116
117 spinlock_t pbi_lock;
118};
119
120extern int pcibr_init_provider(void);
121extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
122extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t, int type);
123extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t, int type);
124extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
125
126/*
127 * prototypes for the bridge asic register access routines in pcibr_reg.c
128 */
129extern void pcireg_control_bit_clr(struct pcibus_info *, u64);
130extern void pcireg_control_bit_set(struct pcibus_info *, u64);
131extern u64 pcireg_tflush_get(struct pcibus_info *);
132extern u64 pcireg_intr_status_get(struct pcibus_info *);
133extern void pcireg_intr_enable_bit_clr(struct pcibus_info *, u64);
134extern void pcireg_intr_enable_bit_set(struct pcibus_info *, u64);
135extern void pcireg_intr_addr_addr_set(struct pcibus_info *, int, u64);
136extern void pcireg_force_intr_set(struct pcibus_info *, int);
137extern u64 pcireg_wrb_flush_get(struct pcibus_info *, int);
138extern void pcireg_int_ate_set(struct pcibus_info *, int, u64);
139extern u64 __iomem * pcireg_int_ate_addr(struct pcibus_info *, int);
140extern void pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
141extern void pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
142extern int pcibr_ate_alloc(struct pcibus_info *, int);
143extern void pcibr_ate_free(struct pcibus_info *, int);
144extern void ate_write(struct pcibus_info *, int, int, u64);
145extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
146 void *resp, char **ssdt);
147extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
148 int action, void *resp);
149extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
150#endif
diff --git a/arch/ia64/include/asm/sn/pcibus_provider_defs.h b/arch/ia64/include/asm/sn/pcibus_provider_defs.h
new file mode 100644
index 000000000000..8f7c83d0f6d3
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcibus_provider_defs.h
@@ -0,0 +1,68 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
10
11/*
12 * SN pci asic types. Do not ever renumber these or reuse values. The
13 * values must agree with what prom thinks they are.
14 */
15
16#define PCIIO_ASIC_TYPE_UNKNOWN 0
17#define PCIIO_ASIC_TYPE_PPB 1
18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4
21#define PCIIO_ASIC_TYPE_TIOCE 5
22
23#define PCIIO_ASIC_MAX_TYPES 6
24
25/*
26 * Common pciio bus provider data. There should be one of these as the
27 * first field in any pciio based provider soft structure (e.g. pcibr_soft
28 * tioca_soft, etc).
29 */
30
31struct pcibus_bussoft {
32 u32 bs_asic_type; /* chipset type */
33 u32 bs_xid; /* xwidget id */
34 u32 bs_persist_busnum; /* Persistent Bus Number */
35 u32 bs_persist_segment; /* Segment Number */
36 u64 bs_legacy_io; /* legacy io pio addr */
37 u64 bs_legacy_mem; /* legacy mem pio addr */
38 u64 bs_base; /* widget base */
39 struct xwidget_info *bs_xwidget_info;
40};
41
42struct pci_controller;
43/*
44 * SN pci bus indirection
45 */
46
47struct sn_pcibus_provider {
48 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t, int flags);
49 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t, int flags);
50 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
51 void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
52 void (*force_interrupt)(struct sn_irq_info *);
53 void (*target_interrupt)(struct sn_irq_info *);
54};
55
56/*
57 * Flags used by the map interfaces
58 * bits 3:0 specifies format of passed in address
59 * bit 4 specifies that address is to be used for MSI
60 */
61
62#define SN_DMA_ADDRTYPE(x) ((x) & 0xf)
63#define SN_DMA_ADDR_PHYS 1 /* address is an xio address. */
64#define SN_DMA_ADDR_XIO 2 /* address is phys memory */
65#define SN_DMA_MSI 0x10 /* Bus address is to be used for MSI */
66
67extern struct sn_pcibus_provider *sn_pci_provider[];
68#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/pcidev.h b/arch/ia64/include/asm/sn/pcidev.h
new file mode 100644
index 000000000000..1c2382cea807
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pcidev.h
@@ -0,0 +1,85 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2006 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
9#define _ASM_IA64_SN_PCI_PCIDEV_H
10
11#include <linux/pci.h>
12
13/*
14 * In ia64, pci_dev->sysdata must be a *pci_controller. To provide access to
15 * the pcidev_info structs for all devices under a controller, we keep a
16 * list of pcidev_info under pci_controller->platform_data.
17 */
18struct sn_platform_data {
19 void *provider_soft;
20 struct list_head pcidev_info;
21};
22
23#define SN_PLATFORM_DATA(busdev) \
24 ((struct sn_platform_data *)(PCI_CONTROLLER(busdev)->platform_data))
25
26#define SN_PCIDEV_INFO(dev) sn_pcidev_info_get(dev)
27
28/*
29 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
30 * this only works for root busses, not for busses represented by PPB's.
31 */
32
33#define SN_PCIBUS_BUSSOFT(pci_bus) \
34 ((struct pcibus_bussoft *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
35
36#define SN_PCIBUS_BUSSOFT_INFO(pci_bus) \
37 ((struct pcibus_info *)(SN_PLATFORM_DATA(pci_bus)->provider_soft))
38/*
39 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
40 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
41 * due to possible PPB's in the path.
42 */
43
44#define SN_PCIDEV_BUSSOFT(pci_dev) \
45 (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
46
47#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
48 (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
49
50#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
51#define PCIIO_SLOT_NONE 255
52#define PCIIO_FUNC_NONE 255
53#define PCIIO_VENDOR_ID_NONE (-1)
54
55struct pcidev_info {
56 u64 pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
57 u64 pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
58
59 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
60 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
61 struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
62
63 struct sn_irq_info *pdi_sn_irq_info;
64 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
65 struct pci_dev *host_pci_dev; /* host bus link */
66 struct list_head pdi_list; /* List of pcidev_info */
67};
68
69extern void sn_irq_fixup(struct pci_dev *pci_dev,
70 struct sn_irq_info *sn_irq_info);
71extern void sn_irq_unfixup(struct pci_dev *pci_dev);
72extern struct pcidev_info * sn_pcidev_info_get(struct pci_dev *);
73extern void sn_bus_fixup(struct pci_bus *);
74extern void sn_acpi_bus_fixup(struct pci_bus *);
75extern void sn_common_bus_fixup(struct pci_bus *, struct pcibus_bussoft *);
76extern void sn_bus_store_sysdata(struct pci_dev *dev);
77extern void sn_bus_free_sysdata(void);
78extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
79extern void sn_io_slot_fixup(struct pci_dev *);
80extern void sn_acpi_slot_fixup(struct pci_dev *);
81extern void sn_pci_fixup_slot(struct pci_dev *dev, struct pcidev_info *,
82 struct sn_irq_info *);
83extern void sn_pci_unfixup_slot(struct pci_dev *dev);
84extern void sn_irq_lh_init(void);
85#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/arch/ia64/include/asm/sn/pda.h b/arch/ia64/include/asm/sn/pda.h
new file mode 100644
index 000000000000..1c5108d44d8b
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pda.h
@@ -0,0 +1,69 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PDA_H
9#define _ASM_IA64_SN_PDA_H
10
11#include <linux/cache.h>
12#include <asm/percpu.h>
13#include <asm/system.h>
14
15
16/*
17 * CPU-specific data structure.
18 *
19 * One of these structures is allocated for each cpu of a NUMA system.
20 *
21 * This structure provides a convenient way of keeping together
22 * all SN per-cpu data structures.
23 */
24
25typedef struct pda_s {
26
27 /*
28 * Support for SN LEDs
29 */
30 volatile short *led_address;
31 u8 led_state;
32 u8 hb_state; /* supports blinking heartbeat leds */
33 unsigned int hb_count;
34
35 unsigned int idle_flag;
36
37 volatile unsigned long *bedrock_rev_id;
38 volatile unsigned long *pio_write_status_addr;
39 unsigned long pio_write_status_val;
40 volatile unsigned long *pio_shub_war_cam_addr;
41
42 unsigned long sn_in_service_ivecs[4];
43 int sn_lb_int_war_ticks;
44 int sn_last_irq;
45 int sn_first_irq;
46} pda_t;
47
48
49#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
50
51/*
52 * PDA
53 * Per-cpu private data area for each cpu. The PDA is located immediately after
54 * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
55 * cpu but only a small amout of the page is actually used. We put the SNIA PDA
56 * in the same page as the cpu_data area. Note that there is a check in the setup
57 * code to verify that we don't overflow the page.
58 *
59 * Seems like we should should cache-line align the pda so that any changes in the
60 * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
61 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
62 */
63DECLARE_PER_CPU(struct pda_s, pda_percpu);
64
65#define pda (&__ia64_per_cpu_var(pda_percpu))
66
67#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu))
68
69#endif /* _ASM_IA64_SN_PDA_H */
diff --git a/arch/ia64/include/asm/sn/pic.h b/arch/ia64/include/asm/sn/pic.h
new file mode 100644
index 000000000000..5f9da5fd6e56
--- /dev/null
+++ b/arch/ia64/include/asm/sn/pic.h
@@ -0,0 +1,261 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PIC_H
9#define _ASM_IA64_SN_PCI_PIC_H
10
11/*
12 * PIC AS DEVICE ZERO
13 * ------------------
14 *
15 * PIC handles PCI/X busses. PCI/X requires that the 'bridge' (i.e. PIC)
16 * be designated as 'device 0'. That is a departure from earlier SGI
17 * PCI bridges. Because of that we use config space 1 to access the
18 * config space of the first actual PCI device on the bus.
19 * Here's what the PIC manual says:
20 *
21 * The current PCI-X bus specification now defines that the parent
22 * hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
23 * reduced the total number of devices from 8 to 4 and removed the
24 * device registers and windows, now only supporting devices 0,1,2, and
25 * 3. PIC did leave all 8 configuration space windows. The reason was
26 * there was nothing to gain by removing them. Here in lies the problem.
27 * The device numbering we do using 0 through 3 is unrelated to the device
28 * numbering which PCI-X requires in configuration space. In the past we
29 * correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
30 * PCI-X requires we start a 1, not 0 and currently the PX brick
31 * does associate our:
32 *
33 * device 0 with configuration space window 1,
34 * device 1 with configuration space window 2,
35 * device 2 with configuration space window 3,
36 * device 3 with configuration space window 4.
37 *
38 * The net effect is that all config space access are off-by-one with
39 * relation to other per-slot accesses on the PIC.
40 * Here is a table that shows some of that:
41 *
42 * Internal Slot#
43 * |
44 * | 0 1 2 3
45 * ----------|---------------------------------------
46 * config | 0x21000 0x22000 0x23000 0x24000
47 * |
48 * even rrb | 0[0] n/a 1[0] n/a [] == implied even/odd
49 * |
50 * odd rrb | n/a 0[1] n/a 1[1]
51 * |
52 * int dev | 00 01 10 11
53 * |
54 * ext slot# | 1 2 3 4
55 * ----------|---------------------------------------
56 */
57
58#define PIC_ATE_TARGETID_SHFT 8
59#define PIC_HOST_INTR_ADDR 0x0000FFFFFFFFFFFFUL
60#define PIC_PCI64_ATTR_TARG_SHFT 60
61
62
63/*****************************************************************************
64 *********************** PIC MMR structure mapping ***************************
65 *****************************************************************************/
66
67/* NOTE: PIC WAR. PV#854697. PIC does not allow writes just to [31:0]
68 * of a 64-bit register. When writing PIC registers, always write the
69 * entire 64 bits.
70 */
71
72struct pic {
73
74 /* 0x000000-0x00FFFF -- Local Registers */
75
76 /* 0x000000-0x000057 -- Standard Widget Configuration */
77 u64 p_wid_id; /* 0x000000 */
78 u64 p_wid_stat; /* 0x000008 */
79 u64 p_wid_err_upper; /* 0x000010 */
80 u64 p_wid_err_lower; /* 0x000018 */
81 #define p_wid_err p_wid_err_lower
82 u64 p_wid_control; /* 0x000020 */
83 u64 p_wid_req_timeout; /* 0x000028 */
84 u64 p_wid_int_upper; /* 0x000030 */
85 u64 p_wid_int_lower; /* 0x000038 */
86 #define p_wid_int p_wid_int_lower
87 u64 p_wid_err_cmdword; /* 0x000040 */
88 u64 p_wid_llp; /* 0x000048 */
89 u64 p_wid_tflush; /* 0x000050 */
90
91 /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
92 u64 p_wid_aux_err; /* 0x000058 */
93 u64 p_wid_resp_upper; /* 0x000060 */
94 u64 p_wid_resp_lower; /* 0x000068 */
95 #define p_wid_resp p_wid_resp_lower
96 u64 p_wid_tst_pin_ctrl; /* 0x000070 */
97 u64 p_wid_addr_lkerr; /* 0x000078 */
98
99 /* 0x000080-0x00008F -- PMU & MAP */
100 u64 p_dir_map; /* 0x000080 */
101 u64 _pad_000088; /* 0x000088 */
102
103 /* 0x000090-0x00009F -- SSRAM */
104 u64 p_map_fault; /* 0x000090 */
105 u64 _pad_000098; /* 0x000098 */
106
107 /* 0x0000A0-0x0000AF -- Arbitration */
108 u64 p_arb; /* 0x0000A0 */
109 u64 _pad_0000A8; /* 0x0000A8 */
110
111 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
112 u64 p_ate_parity_err; /* 0x0000B0 */
113 u64 _pad_0000B8; /* 0x0000B8 */
114
115 /* 0x0000C0-0x0000FF -- PCI/GIO */
116 u64 p_bus_timeout; /* 0x0000C0 */
117 u64 p_pci_cfg; /* 0x0000C8 */
118 u64 p_pci_err_upper; /* 0x0000D0 */
119 u64 p_pci_err_lower; /* 0x0000D8 */
120 #define p_pci_err p_pci_err_lower
121 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
122
123 /* 0x000100-0x0001FF -- Interrupt */
124 u64 p_int_status; /* 0x000100 */
125 u64 p_int_enable; /* 0x000108 */
126 u64 p_int_rst_stat; /* 0x000110 */
127 u64 p_int_mode; /* 0x000118 */
128 u64 p_int_device; /* 0x000120 */
129 u64 p_int_host_err; /* 0x000128 */
130 u64 p_int_addr[8]; /* 0x0001{30,,,68} */
131 u64 p_err_int_view; /* 0x000170 */
132 u64 p_mult_int; /* 0x000178 */
133 u64 p_force_always[8]; /* 0x0001{80,,,B8} */
134 u64 p_force_pin[8]; /* 0x0001{C0,,,F8} */
135
136 /* 0x000200-0x000298 -- Device */
137 u64 p_device[4]; /* 0x0002{00,,,18} */
138 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
139 u64 p_wr_req_buf[4]; /* 0x0002{40,,,58} */
140 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
141 u64 p_rrb_map[2]; /* 0x0002{80,,,88} */
142 #define p_even_resp p_rrb_map[0] /* 0x000280 */
143 #define p_odd_resp p_rrb_map[1] /* 0x000288 */
144 u64 p_resp_status; /* 0x000290 */
145 u64 p_resp_clear; /* 0x000298 */
146
147 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
148
149 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
150 struct {
151 u64 upper; /* 0x0003{00,,,F0} */
152 u64 lower; /* 0x0003{08,,,F8} */
153 } p_buf_addr_match[16];
154
155 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
156 struct {
157 u64 flush_w_touch; /* 0x000{400,,,5C0} */
158 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
159 u64 inflight; /* 0x000{410,,,5D0} */
160 u64 prefetch; /* 0x000{418,,,5D8} */
161 u64 total_pci_retry; /* 0x000{420,,,5E0} */
162 u64 max_pci_retry; /* 0x000{428,,,5E8} */
163 u64 max_latency; /* 0x000{430,,,5F0} */
164 u64 clear_all; /* 0x000{438,,,5F8} */
165 } p_buf_count[8];
166
167
168 /* 0x000600-0x0009FF -- PCI/X registers */
169 u64 p_pcix_bus_err_addr; /* 0x000600 */
170 u64 p_pcix_bus_err_attr; /* 0x000608 */
171 u64 p_pcix_bus_err_data; /* 0x000610 */
172 u64 p_pcix_pio_split_addr; /* 0x000618 */
173 u64 p_pcix_pio_split_attr; /* 0x000620 */
174 u64 p_pcix_dma_req_err_attr; /* 0x000628 */
175 u64 p_pcix_dma_req_err_addr; /* 0x000630 */
176 u64 p_pcix_timeout; /* 0x000638 */
177
178 u64 _pad_000640[120]; /* 0x000{640,,,9F8} */
179
180 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
181 struct {
182 u64 p_buf_addr; /* 0x000{A00,,,AF0} */
183 u64 p_buf_attr; /* 0X000{A08,,,AF8} */
184 } p_pcix_read_buf_64[16];
185
186 struct {
187 u64 p_buf_addr; /* 0x000{B00,,,BE0} */
188 u64 p_buf_attr; /* 0x000{B08,,,BE8} */
189 u64 p_buf_valid; /* 0x000{B10,,,BF0} */
190 u64 __pad1; /* 0x000{B18,,,BF8} */
191 } p_pcix_write_buf_64[8];
192
193 /* End of Local Registers -- Start of Address Map space */
194
195 char _pad_000c00[0x010000 - 0x000c00];
196
197 /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
198 u64 p_int_ate_ram[1024]; /* 0x010000-0x011fff */
199
200 /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
201 u64 p_int_ate_ram_mp[1024]; /* 0x012000-0x013fff */
202
203 char _pad_014000[0x18000 - 0x014000];
204
205 /* 0x18000-0x197F8 -- PIC Write Request Ram */
206 u64 p_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
207 u64 p_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
208 u64 p_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
209
210 char _pad_019800[0x20000 - 0x019800];
211
212 /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
213 union {
214 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
215 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
216 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
217 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
218 union {
219 u8 c[0x100 / 1];
220 u16 s[0x100 / 2];
221 u32 l[0x100 / 4];
222 u64 d[0x100 / 8];
223 } f[8];
224 } p_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */
225
226 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
227 union {
228 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
229 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
230 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
231 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
232 union {
233 u8 c[0x100 / 1];
234 u16 s[0x100 / 2];
235 u32 l[0x100 / 4];
236 u64 d[0x100 / 8];
237 } f[8];
238 } p_type1_cfg; /* 0x028000-0x029000 */
239
240 char _pad_029000[0x030000-0x029000];
241
242 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
243 union {
244 u8 c[8 / 1];
245 u16 s[8 / 2];
246 u32 l[8 / 4];
247 u64 d[8 / 8];
248 } p_pci_iack; /* 0x030000-0x030007 */
249
250 char _pad_030007[0x040000-0x030008];
251
252 /* 0x040000-0x030007 -- PCIX Special Cycle */
253 union {
254 u8 c[8 / 1];
255 u16 s[8 / 2];
256 u32 l[8 / 4];
257 u64 d[8 / 8];
258 } p_pcix_cycle; /* 0x040000-0x040007 */
259};
260
261#endif /* _ASM_IA64_SN_PCI_PIC_H */
diff --git a/arch/ia64/include/asm/sn/rw_mmr.h b/arch/ia64/include/asm/sn/rw_mmr.h
new file mode 100644
index 000000000000..2d78f4c5a45e
--- /dev/null
+++ b/arch/ia64/include/asm/sn/rw_mmr.h
@@ -0,0 +1,28 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002-2006 Silicon Graphics, Inc. All Rights Reserved.
7 */
8#ifndef _ASM_IA64_SN_RW_MMR_H
9#define _ASM_IA64_SN_RW_MMR_H
10
11
12/*
13 * This file that access MMRs via uncached physical addresses.
14 * pio_phys_read_mmr - read an MMR
15 * pio_phys_write_mmr - write an MMR
16 * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
17 * Second MMR will be skipped if address is NULL
18 *
19 * Addresses passed to these routines should be uncached physical addresses
20 * ie., 0x80000....
21 */
22
23
24extern long pio_phys_read_mmr(volatile long *mmr);
25extern void pio_phys_write_mmr(volatile long *mmr, long val);
26extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2);
27
28#endif /* _ASM_IA64_SN_RW_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shub_mmr.h b/arch/ia64/include/asm/sn/shub_mmr.h
new file mode 100644
index 000000000000..7de1d1d4b71a
--- /dev/null
+++ b/arch/ia64/include/asm/sn/shub_mmr.h
@@ -0,0 +1,502 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10#ifndef _ASM_IA64_SN_SHUB_MMR_H
11#define _ASM_IA64_SN_SHUB_MMR_H
12
13/* ==================================================================== */
14/* Register "SH_IPI_INT" */
15/* SHub Inter-Processor Interrupt Registers */
16/* ==================================================================== */
17#define SH1_IPI_INT __IA64_UL_CONST(0x0000000110000380)
18#define SH2_IPI_INT __IA64_UL_CONST(0x0000000010000380)
19
20/* SH_IPI_INT_TYPE */
21/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
22#define SH_IPI_INT_TYPE_SHFT 0
23#define SH_IPI_INT_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
24
25/* SH_IPI_INT_AGT */
26/* Description: Agent, must be 0 for SHub */
27#define SH_IPI_INT_AGT_SHFT 3
28#define SH_IPI_INT_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
29
30/* SH_IPI_INT_PID */
31/* Description: Processor ID, same setting as on targeted McKinley */
32#define SH_IPI_INT_PID_SHFT 4
33#define SH_IPI_INT_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
34
35/* SH_IPI_INT_BASE */
36/* Description: Optional interrupt vector area, 2MB aligned */
37#define SH_IPI_INT_BASE_SHFT 21
38#define SH_IPI_INT_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
39
40/* SH_IPI_INT_IDX */
41/* Description: Targeted McKinley interrupt vector */
42#define SH_IPI_INT_IDX_SHFT 52
43#define SH_IPI_INT_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
44
45/* SH_IPI_INT_SEND */
46/* Description: Send Interrupt Message to PI, This generates a puls */
47#define SH_IPI_INT_SEND_SHFT 63
48#define SH_IPI_INT_SEND_MASK __IA64_UL_CONST(0x8000000000000000)
49
50/* ==================================================================== */
51/* Register "SH_EVENT_OCCURRED" */
52/* SHub Interrupt Event Occurred */
53/* ==================================================================== */
54#define SH1_EVENT_OCCURRED __IA64_UL_CONST(0x0000000110010000)
55#define SH1_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000110010008)
56#define SH2_EVENT_OCCURRED __IA64_UL_CONST(0x0000000010010000)
57#define SH2_EVENT_OCCURRED_ALIAS __IA64_UL_CONST(0x0000000010010008)
58
59/* ==================================================================== */
60/* Register "SH_PI_CAM_CONTROL" */
61/* CRB CAM MMR Access Control */
62/* ==================================================================== */
63#define SH1_PI_CAM_CONTROL __IA64_UL_CONST(0x0000000120050300)
64
65/* ==================================================================== */
66/* Register "SH_SHUB_ID" */
67/* SHub ID Number */
68/* ==================================================================== */
69#define SH1_SHUB_ID __IA64_UL_CONST(0x0000000110060580)
70#define SH1_SHUB_ID_REVISION_SHFT 28
71#define SH1_SHUB_ID_REVISION_MASK __IA64_UL_CONST(0x00000000f0000000)
72
73/* ==================================================================== */
74/* Register "SH_RTC" */
75/* Real-time Clock */
76/* ==================================================================== */
77#define SH1_RTC __IA64_UL_CONST(0x00000001101c0000)
78#define SH2_RTC __IA64_UL_CONST(0x00000002101c0000)
79#define SH_RTC_MASK __IA64_UL_CONST(0x007fffffffffffff)
80
81/* ==================================================================== */
82/* Register "SH_PIO_WRITE_STATUS_0|1" */
83/* PIO Write Status for CPU 0 & 1 */
84/* ==================================================================== */
85#define SH1_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000120070200)
86#define SH1_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000120070280)
87#define SH2_PIO_WRITE_STATUS_0 __IA64_UL_CONST(0x0000000020070200)
88#define SH2_PIO_WRITE_STATUS_1 __IA64_UL_CONST(0x0000000020070280)
89#define SH2_PIO_WRITE_STATUS_2 __IA64_UL_CONST(0x0000000020070300)
90#define SH2_PIO_WRITE_STATUS_3 __IA64_UL_CONST(0x0000000020070380)
91
92/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */
93/* Description: Deadlock response detected */
94#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT 1
95#define SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK \
96 __IA64_UL_CONST(0x0000000000000002)
97
98/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */
99/* Description: Count of currently pending PIO writes */
100#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_SHFT 56
101#define SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK \
102 __IA64_UL_CONST(0x3f00000000000000)
103
104/* ==================================================================== */
105/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */
106/* ==================================================================== */
107#define SH1_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000120070208)
108#define SH2_PIO_WRITE_STATUS_0_ALIAS __IA64_UL_CONST(0x0000000020070208)
109
110/* ==================================================================== */
111/* Register "SH_EVENT_OCCURRED" */
112/* SHub Interrupt Event Occurred */
113/* ==================================================================== */
114/* SH_EVENT_OCCURRED_UART_INT */
115/* Description: Pending Junk Bus UART Interrupt */
116#define SH_EVENT_OCCURRED_UART_INT_SHFT 20
117#define SH_EVENT_OCCURRED_UART_INT_MASK __IA64_UL_CONST(0x0000000000100000)
118
119/* SH_EVENT_OCCURRED_IPI_INT */
120/* Description: Pending IPI Interrupt */
121#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28
122#define SH_EVENT_OCCURRED_IPI_INT_MASK __IA64_UL_CONST(0x0000000010000000)
123
124/* SH_EVENT_OCCURRED_II_INT0 */
125/* Description: Pending II 0 Interrupt */
126#define SH_EVENT_OCCURRED_II_INT0_SHFT 29
127#define SH_EVENT_OCCURRED_II_INT0_MASK __IA64_UL_CONST(0x0000000020000000)
128
129/* SH_EVENT_OCCURRED_II_INT1 */
130/* Description: Pending II 1 Interrupt */
131#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
132#define SH_EVENT_OCCURRED_II_INT1_MASK __IA64_UL_CONST(0x0000000040000000)
133
134/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
135/* Description: Pending SHUB 2 EXT IO INT2 */
136#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
137#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK __IA64_UL_CONST(0x0000000200000000)
138
139/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
140/* Description: Pending SHUB 2 EXT IO INT3 */
141#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
142#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK __IA64_UL_CONST(0x0000000400000000)
143
144#define SH_ALL_INT_MASK \
145 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
146 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
147 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
148 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
149
150
151/* ==================================================================== */
152/* LEDS */
153/* ==================================================================== */
154#define SH1_REAL_JUNK_BUS_LED0 0x7fed00000UL
155#define SH1_REAL_JUNK_BUS_LED1 0x7fed10000UL
156#define SH1_REAL_JUNK_BUS_LED2 0x7fed20000UL
157#define SH1_REAL_JUNK_BUS_LED3 0x7fed30000UL
158
159#define SH2_REAL_JUNK_BUS_LED0 0xf0000000UL
160#define SH2_REAL_JUNK_BUS_LED1 0xf0010000UL
161#define SH2_REAL_JUNK_BUS_LED2 0xf0020000UL
162#define SH2_REAL_JUNK_BUS_LED3 0xf0030000UL
163
164/* ==================================================================== */
165/* Register "SH1_PTC_0" */
166/* Puge Translation Cache Message Configuration Information */
167/* ==================================================================== */
168#define SH1_PTC_0 __IA64_UL_CONST(0x00000001101a0000)
169
170/* SH1_PTC_0_A */
171/* Description: Type */
172#define SH1_PTC_0_A_SHFT 0
173
174/* SH1_PTC_0_PS */
175/* Description: Page Size */
176#define SH1_PTC_0_PS_SHFT 2
177
178/* SH1_PTC_0_RID */
179/* Description: Region ID */
180#define SH1_PTC_0_RID_SHFT 8
181
182/* SH1_PTC_0_START */
183/* Description: Start */
184#define SH1_PTC_0_START_SHFT 63
185
186/* ==================================================================== */
187/* Register "SH1_PTC_1" */
188/* Puge Translation Cache Message Configuration Information */
189/* ==================================================================== */
190#define SH1_PTC_1 __IA64_UL_CONST(0x00000001101a0080)
191
192/* SH1_PTC_1_START */
193/* Description: PTC_1 Start */
194#define SH1_PTC_1_START_SHFT 63
195
196/* ==================================================================== */
197/* Register "SH2_PTC" */
198/* Puge Translation Cache Message Configuration Information */
199/* ==================================================================== */
200#define SH2_PTC __IA64_UL_CONST(0x0000000170000000)
201
202/* SH2_PTC_A */
203/* Description: Type */
204#define SH2_PTC_A_SHFT 0
205
206/* SH2_PTC_PS */
207/* Description: Page Size */
208#define SH2_PTC_PS_SHFT 2
209
210/* SH2_PTC_RID */
211/* Description: Region ID */
212#define SH2_PTC_RID_SHFT 4
213
214/* SH2_PTC_START */
215/* Description: Start */
216#define SH2_PTC_START_SHFT 63
217
218/* SH2_PTC_ADDR_RID */
219/* Description: Region ID */
220#define SH2_PTC_ADDR_SHFT 4
221#define SH2_PTC_ADDR_MASK __IA64_UL_CONST(0x1ffffffffffff000)
222
223/* ==================================================================== */
224/* Register "SH_RTC1_INT_CONFIG" */
225/* SHub RTC 1 Interrupt Config Registers */
226/* ==================================================================== */
227
228#define SH1_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000110001480)
229#define SH2_RTC1_INT_CONFIG __IA64_UL_CONST(0x0000000010001480)
230#define SH_RTC1_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
231#define SH_RTC1_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
232
233/* SH_RTC1_INT_CONFIG_TYPE */
234/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
235#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0
236#define SH_RTC1_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
237
238/* SH_RTC1_INT_CONFIG_AGT */
239/* Description: Agent, must be 0 for SHub */
240#define SH_RTC1_INT_CONFIG_AGT_SHFT 3
241#define SH_RTC1_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
242
243/* SH_RTC1_INT_CONFIG_PID */
244/* Description: Processor ID, same setting as on targeted McKinley */
245#define SH_RTC1_INT_CONFIG_PID_SHFT 4
246#define SH_RTC1_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
247
248/* SH_RTC1_INT_CONFIG_BASE */
249/* Description: Optional interrupt vector area, 2MB aligned */
250#define SH_RTC1_INT_CONFIG_BASE_SHFT 21
251#define SH_RTC1_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
252
253/* SH_RTC1_INT_CONFIG_IDX */
254/* Description: Targeted McKinley interrupt vector */
255#define SH_RTC1_INT_CONFIG_IDX_SHFT 52
256#define SH_RTC1_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
257
258/* ==================================================================== */
259/* Register "SH_RTC1_INT_ENABLE" */
260/* SHub RTC 1 Interrupt Enable Registers */
261/* ==================================================================== */
262
263#define SH1_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000110001500)
264#define SH2_RTC1_INT_ENABLE __IA64_UL_CONST(0x0000000010001500)
265#define SH_RTC1_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
266#define SH_RTC1_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
267
268/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */
269/* Description: Enable RTC 1 Interrupt */
270#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0
271#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK \
272 __IA64_UL_CONST(0x0000000000000001)
273
274/* ==================================================================== */
275/* Register "SH_RTC2_INT_CONFIG" */
276/* SHub RTC 2 Interrupt Config Registers */
277/* ==================================================================== */
278
279#define SH1_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000110001580)
280#define SH2_RTC2_INT_CONFIG __IA64_UL_CONST(0x0000000010001580)
281#define SH_RTC2_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
282#define SH_RTC2_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
283
284/* SH_RTC2_INT_CONFIG_TYPE */
285/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
286#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0
287#define SH_RTC2_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
288
289/* SH_RTC2_INT_CONFIG_AGT */
290/* Description: Agent, must be 0 for SHub */
291#define SH_RTC2_INT_CONFIG_AGT_SHFT 3
292#define SH_RTC2_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
293
294/* SH_RTC2_INT_CONFIG_PID */
295/* Description: Processor ID, same setting as on targeted McKinley */
296#define SH_RTC2_INT_CONFIG_PID_SHFT 4
297#define SH_RTC2_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
298
299/* SH_RTC2_INT_CONFIG_BASE */
300/* Description: Optional interrupt vector area, 2MB aligned */
301#define SH_RTC2_INT_CONFIG_BASE_SHFT 21
302#define SH_RTC2_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
303
304/* SH_RTC2_INT_CONFIG_IDX */
305/* Description: Targeted McKinley interrupt vector */
306#define SH_RTC2_INT_CONFIG_IDX_SHFT 52
307#define SH_RTC2_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
308
309/* ==================================================================== */
310/* Register "SH_RTC2_INT_ENABLE" */
311/* SHub RTC 2 Interrupt Enable Registers */
312/* ==================================================================== */
313
314#define SH1_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000110001600)
315#define SH2_RTC2_INT_ENABLE __IA64_UL_CONST(0x0000000010001600)
316#define SH_RTC2_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
317#define SH_RTC2_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
318
319/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */
320/* Description: Enable RTC 2 Interrupt */
321#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0
322#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK \
323 __IA64_UL_CONST(0x0000000000000001)
324
325/* ==================================================================== */
326/* Register "SH_RTC3_INT_CONFIG" */
327/* SHub RTC 3 Interrupt Config Registers */
328/* ==================================================================== */
329
330#define SH1_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000110001680)
331#define SH2_RTC3_INT_CONFIG __IA64_UL_CONST(0x0000000010001680)
332#define SH_RTC3_INT_CONFIG_MASK __IA64_UL_CONST(0x0ff3ffffffefffff)
333#define SH_RTC3_INT_CONFIG_INIT __IA64_UL_CONST(0x0000000000000000)
334
335/* SH_RTC3_INT_CONFIG_TYPE */
336/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */
337#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0
338#define SH_RTC3_INT_CONFIG_TYPE_MASK __IA64_UL_CONST(0x0000000000000007)
339
340/* SH_RTC3_INT_CONFIG_AGT */
341/* Description: Agent, must be 0 for SHub */
342#define SH_RTC3_INT_CONFIG_AGT_SHFT 3
343#define SH_RTC3_INT_CONFIG_AGT_MASK __IA64_UL_CONST(0x0000000000000008)
344
345/* SH_RTC3_INT_CONFIG_PID */
346/* Description: Processor ID, same setting as on targeted McKinley */
347#define SH_RTC3_INT_CONFIG_PID_SHFT 4
348#define SH_RTC3_INT_CONFIG_PID_MASK __IA64_UL_CONST(0x00000000000ffff0)
349
350/* SH_RTC3_INT_CONFIG_BASE */
351/* Description: Optional interrupt vector area, 2MB aligned */
352#define SH_RTC3_INT_CONFIG_BASE_SHFT 21
353#define SH_RTC3_INT_CONFIG_BASE_MASK __IA64_UL_CONST(0x0003ffffffe00000)
354
355/* SH_RTC3_INT_CONFIG_IDX */
356/* Description: Targeted McKinley interrupt vector */
357#define SH_RTC3_INT_CONFIG_IDX_SHFT 52
358#define SH_RTC3_INT_CONFIG_IDX_MASK __IA64_UL_CONST(0x0ff0000000000000)
359
360/* ==================================================================== */
361/* Register "SH_RTC3_INT_ENABLE" */
362/* SHub RTC 3 Interrupt Enable Registers */
363/* ==================================================================== */
364
365#define SH1_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000110001700)
366#define SH2_RTC3_INT_ENABLE __IA64_UL_CONST(0x0000000010001700)
367#define SH_RTC3_INT_ENABLE_MASK __IA64_UL_CONST(0x0000000000000001)
368#define SH_RTC3_INT_ENABLE_INIT __IA64_UL_CONST(0x0000000000000000)
369
370/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */
371/* Description: Enable RTC 3 Interrupt */
372#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0
373#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK \
374 __IA64_UL_CONST(0x0000000000000001)
375
376/* SH_EVENT_OCCURRED_RTC1_INT */
377/* Description: Pending RTC 1 Interrupt */
378#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24
379#define SH_EVENT_OCCURRED_RTC1_INT_MASK __IA64_UL_CONST(0x0000000001000000)
380
381/* SH_EVENT_OCCURRED_RTC2_INT */
382/* Description: Pending RTC 2 Interrupt */
383#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25
384#define SH_EVENT_OCCURRED_RTC2_INT_MASK __IA64_UL_CONST(0x0000000002000000)
385
386/* SH_EVENT_OCCURRED_RTC3_INT */
387/* Description: Pending RTC 3 Interrupt */
388#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
389#define SH_EVENT_OCCURRED_RTC3_INT_MASK __IA64_UL_CONST(0x0000000004000000)
390
391/* ==================================================================== */
392/* Register "SH_IPI_ACCESS" */
393/* CPU interrupt Access Permission Bits */
394/* ==================================================================== */
395
396#define SH1_IPI_ACCESS __IA64_UL_CONST(0x0000000110060480)
397#define SH2_IPI_ACCESS0 __IA64_UL_CONST(0x0000000010060c00)
398#define SH2_IPI_ACCESS1 __IA64_UL_CONST(0x0000000010060c80)
399#define SH2_IPI_ACCESS2 __IA64_UL_CONST(0x0000000010060d00)
400#define SH2_IPI_ACCESS3 __IA64_UL_CONST(0x0000000010060d80)
401
402/* ==================================================================== */
403/* Register "SH_INT_CMPB" */
404/* RTC Compare Value for Processor B */
405/* ==================================================================== */
406
407#define SH1_INT_CMPB __IA64_UL_CONST(0x00000001101b0080)
408#define SH2_INT_CMPB __IA64_UL_CONST(0x00000000101b0080)
409#define SH_INT_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
410#define SH_INT_CMPB_INIT __IA64_UL_CONST(0x0000000000000000)
411
412/* SH_INT_CMPB_REAL_TIME_CMPB */
413/* Description: Real Time Clock Compare */
414#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
415#define SH_INT_CMPB_REAL_TIME_CMPB_MASK __IA64_UL_CONST(0x007fffffffffffff)
416
417/* ==================================================================== */
418/* Register "SH_INT_CMPC" */
419/* RTC Compare Value for Processor C */
420/* ==================================================================== */
421
422#define SH1_INT_CMPC __IA64_UL_CONST(0x00000001101b0100)
423#define SH2_INT_CMPC __IA64_UL_CONST(0x00000000101b0100)
424#define SH_INT_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
425#define SH_INT_CMPC_INIT __IA64_UL_CONST(0x0000000000000000)
426
427/* SH_INT_CMPC_REAL_TIME_CMPC */
428/* Description: Real Time Clock Compare */
429#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
430#define SH_INT_CMPC_REAL_TIME_CMPC_MASK __IA64_UL_CONST(0x007fffffffffffff)
431
432/* ==================================================================== */
433/* Register "SH_INT_CMPD" */
434/* RTC Compare Value for Processor D */
435/* ==================================================================== */
436
437#define SH1_INT_CMPD __IA64_UL_CONST(0x00000001101b0180)
438#define SH2_INT_CMPD __IA64_UL_CONST(0x00000000101b0180)
439#define SH_INT_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
440#define SH_INT_CMPD_INIT __IA64_UL_CONST(0x0000000000000000)
441
442/* SH_INT_CMPD_REAL_TIME_CMPD */
443/* Description: Real Time Clock Compare */
444#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
445#define SH_INT_CMPD_REAL_TIME_CMPD_MASK __IA64_UL_CONST(0x007fffffffffffff)
446
447/* ==================================================================== */
448/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
449/* privilege vector for acc=0 */
450/* ==================================================================== */
451#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100030300)
452
453/* ==================================================================== */
454/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
455/* privilege vector for acc=0 */
456/* ==================================================================== */
457#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 __IA64_UL_CONST(0x0000000100050300)
458
459/* ==================================================================== */
460/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
461/* and SHUB2 that it makes sense to define a geberic name for the MMR. */
462/* It is acceptible to use (for example) SH_IPI_INT to reference the */
463/* the IPI MMR. The value of SH_IPI_INT is determined at runtime based */
464/* on the type of the SHUB. Do not use these #defines in performance */
465/* critical code or loops - there is a small performance penalty. */
466/* ==================================================================== */
467#define shubmmr(a,b) (is_shub2() ? a##2_##b : a##1_##b)
468
469#define SH_REAL_JUNK_BUS_LED0 shubmmr(SH, REAL_JUNK_BUS_LED0)
470#define SH_IPI_INT shubmmr(SH, IPI_INT)
471#define SH_EVENT_OCCURRED shubmmr(SH, EVENT_OCCURRED)
472#define SH_EVENT_OCCURRED_ALIAS shubmmr(SH, EVENT_OCCURRED_ALIAS)
473#define SH_RTC shubmmr(SH, RTC)
474#define SH_RTC1_INT_CONFIG shubmmr(SH, RTC1_INT_CONFIG)
475#define SH_RTC1_INT_ENABLE shubmmr(SH, RTC1_INT_ENABLE)
476#define SH_RTC2_INT_CONFIG shubmmr(SH, RTC2_INT_CONFIG)
477#define SH_RTC2_INT_ENABLE shubmmr(SH, RTC2_INT_ENABLE)
478#define SH_RTC3_INT_CONFIG shubmmr(SH, RTC3_INT_CONFIG)
479#define SH_RTC3_INT_ENABLE shubmmr(SH, RTC3_INT_ENABLE)
480#define SH_INT_CMPB shubmmr(SH, INT_CMPB)
481#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
482#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
483
484/* ========================================================================== */
485/* Register "SH2_BT_ENG_CSR_0" */
486/* Engine 0 Control and Status Register */
487/* ========================================================================== */
488
489#define SH2_BT_ENG_CSR_0 __IA64_UL_CONST(0x0000000030040000)
490#define SH2_BT_ENG_SRC_ADDR_0 __IA64_UL_CONST(0x0000000030040080)
491#define SH2_BT_ENG_DEST_ADDR_0 __IA64_UL_CONST(0x0000000030040100)
492#define SH2_BT_ENG_NOTIF_ADDR_0 __IA64_UL_CONST(0x0000000030040180)
493
494/* ========================================================================== */
495/* BTE interfaces 1-3 */
496/* ========================================================================== */
497
498#define SH2_BT_ENG_CSR_1 __IA64_UL_CONST(0x0000000030050000)
499#define SH2_BT_ENG_CSR_2 __IA64_UL_CONST(0x0000000030060000)
500#define SH2_BT_ENG_CSR_3 __IA64_UL_CONST(0x0000000030070000)
501
502#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/arch/ia64/include/asm/sn/shubio.h b/arch/ia64/include/asm/sn/shubio.h
new file mode 100644
index 000000000000..22a6f18a5313
--- /dev/null
+++ b/arch/ia64/include/asm/sn/shubio.h
@@ -0,0 +1,3358 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_SHUBIO_H
10#define _ASM_IA64_SN_SHUBIO_H
11
12#define HUB_WIDGET_ID_MAX 0xf
13#define IIO_NUM_ITTES 7
14#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
15
16#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
17 /* This register is also accessible from
18 * Crosstalk at address 0x0. */
19#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
20#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
21#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
22#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
23#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
24#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
25#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
26#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
27#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
28#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
29
30#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
31#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
32
33#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
34#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
35
36#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
37#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
38#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
39#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
40#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
41#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
42#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
43
44#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
45#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
46#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
47#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
48#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
49#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
50#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
51#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
52#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
53
54#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
55#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
56#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
57#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
58#define IIO_IBCR 0x00400200 /* IO BTE Control Register */
59
60#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
61#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
62
63#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
64
65#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
66#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
67
68#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
69#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
70
71#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
72#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
73#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
74#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
75#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
76
77#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
78
79#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
80#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
81#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
82#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
83#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
84#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
85#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
86#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
87
88#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
89#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
90#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
91#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
92#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
93#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
94#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
95#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
96
97#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
98#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
99#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
100#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
101#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
102#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
103#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
104#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
105
106#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
107#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
108#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
109#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
110#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
111
112#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
113#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
114#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
115#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
116#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
117
118#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
119#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
120#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
121#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
122#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
123
124#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
125#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
126#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
127#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
128#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
129
130#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
131#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
132#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
133#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
134#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
135
136#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
137#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
138#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
139#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
140#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
141
142#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
143#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
144#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
145#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
146#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
147
148#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
149#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
150#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
151#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
152#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
153
154#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
155#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
156#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
157#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
158#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
159
160#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
161#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
162#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
163#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
164#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
165
166#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
167#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
168#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
169#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
170#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
171
172#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
173#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
174#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
175#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
176#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
177
178#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
179#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
180#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
181#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
182#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
183
184#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
185#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
186#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
187#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
188#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
189
190#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
191#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
192#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
193#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
194#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
195
196#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
197#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
198#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
199
200#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
201
202#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
203#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
204#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
205#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
206#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
207#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
208#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
209#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
210#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
211#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
212#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
213#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
214
215#define IIO_IPCR 0x00430000 /* IO Performance Control */
216#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
217
218/************************************************************************
219 * *
220 * Description: This register echoes some information from the *
221 * LB_REV_ID register. It is available through Crosstalk as described *
222 * above. The REV_NUM and MFG_NUM fields receive their values from *
223 * the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
224 * The PART_NUM field's value is the Crosstalk device ID number that *
225 * Steve Miller assigned to the SHub chip. *
226 * *
227 ************************************************************************/
228
229typedef union ii_wid_u {
230 u64 ii_wid_regval;
231 struct {
232 u64 w_rsvd_1:1;
233 u64 w_mfg_num:11;
234 u64 w_part_num:16;
235 u64 w_rev_num:4;
236 u64 w_rsvd:32;
237 } ii_wid_fld_s;
238} ii_wid_u_t;
239
240/************************************************************************
241 * *
242 * The fields in this register are set upon detection of an error *
243 * and cleared by various mechanisms, as explained in the *
244 * description. *
245 * *
246 ************************************************************************/
247
248typedef union ii_wstat_u {
249 u64 ii_wstat_regval;
250 struct {
251 u64 w_pending:4;
252 u64 w_xt_crd_to:1;
253 u64 w_xt_tail_to:1;
254 u64 w_rsvd_3:3;
255 u64 w_tx_mx_rty:1;
256 u64 w_rsvd_2:6;
257 u64 w_llp_tx_cnt:8;
258 u64 w_rsvd_1:8;
259 u64 w_crazy:1;
260 u64 w_rsvd:31;
261 } ii_wstat_fld_s;
262} ii_wstat_u_t;
263
264/************************************************************************
265 * *
266 * Description: This is a read-write enabled register. It controls *
267 * various aspects of the Crosstalk flow control. *
268 * *
269 ************************************************************************/
270
271typedef union ii_wcr_u {
272 u64 ii_wcr_regval;
273 struct {
274 u64 w_wid:4;
275 u64 w_tag:1;
276 u64 w_rsvd_1:8;
277 u64 w_dst_crd:3;
278 u64 w_f_bad_pkt:1;
279 u64 w_dir_con:1;
280 u64 w_e_thresh:5;
281 u64 w_rsvd:41;
282 } ii_wcr_fld_s;
283} ii_wcr_u_t;
284
285/************************************************************************
286 * *
287 * Description: This register's value is a bit vector that guards *
288 * access to local registers within the II as well as to external *
289 * Crosstalk widgets. Each bit in the register corresponds to a *
290 * particular region in the system; a region consists of one, two or *
291 * four nodes (depending on the value of the REGION_SIZE field in the *
292 * LB_REV_ID register, which is documented in Section 8.3.1.1). The *
293 * protection provided by this register applies to PIO read *
294 * operations as well as PIO write operations. The II will perform a *
295 * PIO read or write request only if the bit for the requestor's *
296 * region is set; otherwise, the II will not perform the requested *
297 * operation and will return an error response. When a PIO read or *
298 * write request targets an external Crosstalk widget, then not only *
299 * must the bit for the requestor's region be set in the ILAPR, but *
300 * also the target widget's bit in the IOWA register must be set in *
301 * order for the II to perform the requested operation; otherwise, *
302 * the II will return an error response. Hence, the protection *
303 * provided by the IOWA register supplements the protection provided *
304 * by the ILAPR for requests that target external Crosstalk widgets. *
305 * This register itself can be accessed only by the nodes whose *
306 * region ID bits are enabled in this same register. It can also be *
307 * accessed through the IAlias space by the local processors. *
308 * The reset value of this register allows access by all nodes. *
309 * *
310 ************************************************************************/
311
312typedef union ii_ilapr_u {
313 u64 ii_ilapr_regval;
314 struct {
315 u64 i_region:64;
316 } ii_ilapr_fld_s;
317} ii_ilapr_u_t;
318
319/************************************************************************
320 * *
321 * Description: A write to this register of the 64-bit value *
322 * "SGIrules" in ASCII, will cause the bit in the ILAPR register *
323 * corresponding to the region of the requestor to be set (allow *
324 * access). A write of any other value will be ignored. Access *
325 * protection for this register is "SGIrules". *
326 * This register can also be accessed through the IAlias space. *
327 * However, this access will not change the access permissions in the *
328 * ILAPR. *
329 * *
330 ************************************************************************/
331
332typedef union ii_ilapo_u {
333 u64 ii_ilapo_regval;
334 struct {
335 u64 i_io_ovrride:64;
336 } ii_ilapo_fld_s;
337} ii_ilapo_u_t;
338
339/************************************************************************
340 * *
341 * This register qualifies all the PIO and Graphics writes launched *
342 * from the SHUB towards a widget. *
343 * *
344 ************************************************************************/
345
346typedef union ii_iowa_u {
347 u64 ii_iowa_regval;
348 struct {
349 u64 i_w0_oac:1;
350 u64 i_rsvd_1:7;
351 u64 i_wx_oac:8;
352 u64 i_rsvd:48;
353 } ii_iowa_fld_s;
354} ii_iowa_u_t;
355
356/************************************************************************
357 * *
358 * Description: This register qualifies all the requests launched *
359 * from a widget towards the Shub. This register is intended to be *
360 * used by software in case of misbehaving widgets. *
361 * *
362 * *
363 ************************************************************************/
364
365typedef union ii_iiwa_u {
366 u64 ii_iiwa_regval;
367 struct {
368 u64 i_w0_iac:1;
369 u64 i_rsvd_1:7;
370 u64 i_wx_iac:8;
371 u64 i_rsvd:48;
372 } ii_iiwa_fld_s;
373} ii_iiwa_u_t;
374
375/************************************************************************
376 * *
377 * Description: This register qualifies all the operations launched *
378 * from a widget towards the SHub. It allows individual access *
379 * control for up to 8 devices per widget. A device refers to *
380 * individual DMA master hosted by a widget. *
381 * The bits in each field of this register are cleared by the Shub *
382 * upon detection of an error which requires the device to be *
383 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
384 * Crosstalk). Whether or not a device has access rights to this *
385 * Shub is determined by an AND of the device enable bit in the *
386 * appropriate field of this register and the corresponding bit in *
387 * the Wx_IAC field (for the widget which this device belongs to). *
388 * The bits in this field are set by writing a 1 to them. Incoming *
389 * replies from Crosstalk are not subject to this access control *
390 * mechanism. *
391 * *
392 ************************************************************************/
393
394typedef union ii_iidem_u {
395 u64 ii_iidem_regval;
396 struct {
397 u64 i_w8_dxs:8;
398 u64 i_w9_dxs:8;
399 u64 i_wa_dxs:8;
400 u64 i_wb_dxs:8;
401 u64 i_wc_dxs:8;
402 u64 i_wd_dxs:8;
403 u64 i_we_dxs:8;
404 u64 i_wf_dxs:8;
405 } ii_iidem_fld_s;
406} ii_iidem_u_t;
407
408/************************************************************************
409 * *
410 * This register contains the various programmable fields necessary *
411 * for controlling and observing the LLP signals. *
412 * *
413 ************************************************************************/
414
415typedef union ii_ilcsr_u {
416 u64 ii_ilcsr_regval;
417 struct {
418 u64 i_nullto:6;
419 u64 i_rsvd_4:2;
420 u64 i_wrmrst:1;
421 u64 i_rsvd_3:1;
422 u64 i_llp_en:1;
423 u64 i_bm8:1;
424 u64 i_llp_stat:2;
425 u64 i_remote_power:1;
426 u64 i_rsvd_2:1;
427 u64 i_maxrtry:10;
428 u64 i_d_avail_sel:2;
429 u64 i_rsvd_1:4;
430 u64 i_maxbrst:10;
431 u64 i_rsvd:22;
432
433 } ii_ilcsr_fld_s;
434} ii_ilcsr_u_t;
435
436/************************************************************************
437 * *
438 * This is simply a status registers that monitors the LLP error *
439 * rate. *
440 * *
441 ************************************************************************/
442
443typedef union ii_illr_u {
444 u64 ii_illr_regval;
445 struct {
446 u64 i_sn_cnt:16;
447 u64 i_cb_cnt:16;
448 u64 i_rsvd:32;
449 } ii_illr_fld_s;
450} ii_illr_u_t;
451
452/************************************************************************
453 * *
454 * Description: All II-detected non-BTE error interrupts are *
455 * specified via this register. *
456 * NOTE: The PI interrupt register address is hardcoded in the II. If *
457 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
458 * packet) to address offset 0x0180_0090 within the local register *
459 * address space of PI0 on the node specified by the NODE field. If *
460 * PI_ID==1, then the II sends the interrupt request to address *
461 * offset 0x01A0_0090 within the local register address space of PI1 *
462 * on the node specified by the NODE field. *
463 * *
464 ************************************************************************/
465
466typedef union ii_iidsr_u {
467 u64 ii_iidsr_regval;
468 struct {
469 u64 i_level:8;
470 u64 i_pi_id:1;
471 u64 i_node:11;
472 u64 i_rsvd_3:4;
473 u64 i_enable:1;
474 u64 i_rsvd_2:3;
475 u64 i_int_sent:2;
476 u64 i_rsvd_1:2;
477 u64 i_pi0_forward_int:1;
478 u64 i_pi1_forward_int:1;
479 u64 i_rsvd:30;
480 } ii_iidsr_fld_s;
481} ii_iidsr_u_t;
482
483/************************************************************************
484 * *
485 * There are two instances of this register. This register is used *
486 * for matching up the incoming responses from the graphics widget to *
487 * the processor that initiated the graphics operation. The *
488 * write-responses are converted to graphics credits and returned to *
489 * the processor so that the processor interface can manage the flow *
490 * control. *
491 * *
492 ************************************************************************/
493
494typedef union ii_igfx0_u {
495 u64 ii_igfx0_regval;
496 struct {
497 u64 i_w_num:4;
498 u64 i_pi_id:1;
499 u64 i_n_num:12;
500 u64 i_p_num:1;
501 u64 i_rsvd:46;
502 } ii_igfx0_fld_s;
503} ii_igfx0_u_t;
504
505/************************************************************************
506 * *
507 * There are two instances of this register. This register is used *
508 * for matching up the incoming responses from the graphics widget to *
509 * the processor that initiated the graphics operation. The *
510 * write-responses are converted to graphics credits and returned to *
511 * the processor so that the processor interface can manage the flow *
512 * control. *
513 * *
514 ************************************************************************/
515
516typedef union ii_igfx1_u {
517 u64 ii_igfx1_regval;
518 struct {
519 u64 i_w_num:4;
520 u64 i_pi_id:1;
521 u64 i_n_num:12;
522 u64 i_p_num:1;
523 u64 i_rsvd:46;
524 } ii_igfx1_fld_s;
525} ii_igfx1_u_t;
526
527/************************************************************************
528 * *
529 * There are two instances of this registers. These registers are *
530 * used as scratch registers for software use. *
531 * *
532 ************************************************************************/
533
534typedef union ii_iscr0_u {
535 u64 ii_iscr0_regval;
536 struct {
537 u64 i_scratch:64;
538 } ii_iscr0_fld_s;
539} ii_iscr0_u_t;
540
541/************************************************************************
542 * *
543 * There are two instances of this registers. These registers are *
544 * used as scratch registers for software use. *
545 * *
546 ************************************************************************/
547
548typedef union ii_iscr1_u {
549 u64 ii_iscr1_regval;
550 struct {
551 u64 i_scratch:64;
552 } ii_iscr1_fld_s;
553} ii_iscr1_u_t;
554
555/************************************************************************
556 * *
557 * Description: There are seven instances of translation table entry *
558 * registers. Each register maps a Shub Big Window to a 48-bit *
559 * address on Crosstalk. *
560 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
561 * number) are used to select one of these 7 registers. The Widget *
562 * number field is then derived from the W_NUM field for synthesizing *
563 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
564 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
565 * are padded with zeros. Although the maximum Crosstalk space *
566 * addressable by the SHub is thus the lower 16 GBytes per widget *
567 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
568 * space can be accessed. *
569 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
570 * Window number) are used to select one of these 7 registers. The *
571 * Widget number field is then derived from the W_NUM field for *
572 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
573 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
574 * field is used as Crosstalk[47], and remainder of the Crosstalk *
575 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
576 * Crosstalk space addressable by the Shub is thus the lower *
577 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
578 * of this space can be accessed. *
579 * *
580 ************************************************************************/
581
582typedef union ii_itte1_u {
583 u64 ii_itte1_regval;
584 struct {
585 u64 i_offset:5;
586 u64 i_rsvd_1:3;
587 u64 i_w_num:4;
588 u64 i_iosp:1;
589 u64 i_rsvd:51;
590 } ii_itte1_fld_s;
591} ii_itte1_u_t;
592
593/************************************************************************
594 * *
595 * Description: There are seven instances of translation table entry *
596 * registers. Each register maps a Shub Big Window to a 48-bit *
597 * address on Crosstalk. *
598 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
599 * number) are used to select one of these 7 registers. The Widget *
600 * number field is then derived from the W_NUM field for synthesizing *
601 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
602 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
603 * are padded with zeros. Although the maximum Crosstalk space *
604 * addressable by the Shub is thus the lower 16 GBytes per widget *
605 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
606 * space can be accessed. *
607 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
608 * Window number) are used to select one of these 7 registers. The *
609 * Widget number field is then derived from the W_NUM field for *
610 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
611 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
612 * field is used as Crosstalk[47], and remainder of the Crosstalk *
613 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
614 * Crosstalk space addressable by the Shub is thus the lower *
615 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
616 * of this space can be accessed. *
617 * *
618 ************************************************************************/
619
620typedef union ii_itte2_u {
621 u64 ii_itte2_regval;
622 struct {
623 u64 i_offset:5;
624 u64 i_rsvd_1:3;
625 u64 i_w_num:4;
626 u64 i_iosp:1;
627 u64 i_rsvd:51;
628 } ii_itte2_fld_s;
629} ii_itte2_u_t;
630
631/************************************************************************
632 * *
633 * Description: There are seven instances of translation table entry *
634 * registers. Each register maps a Shub Big Window to a 48-bit *
635 * address on Crosstalk. *
636 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
637 * number) are used to select one of these 7 registers. The Widget *
638 * number field is then derived from the W_NUM field for synthesizing *
639 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
640 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
641 * are padded with zeros. Although the maximum Crosstalk space *
642 * addressable by the Shub is thus the lower 16 GBytes per widget *
643 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
644 * space can be accessed. *
645 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
646 * Window number) are used to select one of these 7 registers. The *
647 * Widget number field is then derived from the W_NUM field for *
648 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
649 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
650 * field is used as Crosstalk[47], and remainder of the Crosstalk *
651 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
652 * Crosstalk space addressable by the SHub is thus the lower *
653 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
654 * of this space can be accessed. *
655 * *
656 ************************************************************************/
657
658typedef union ii_itte3_u {
659 u64 ii_itte3_regval;
660 struct {
661 u64 i_offset:5;
662 u64 i_rsvd_1:3;
663 u64 i_w_num:4;
664 u64 i_iosp:1;
665 u64 i_rsvd:51;
666 } ii_itte3_fld_s;
667} ii_itte3_u_t;
668
669/************************************************************************
670 * *
671 * Description: There are seven instances of translation table entry *
672 * registers. Each register maps a SHub Big Window to a 48-bit *
673 * address on Crosstalk. *
674 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
675 * number) are used to select one of these 7 registers. The Widget *
676 * number field is then derived from the W_NUM field for synthesizing *
677 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
678 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
679 * are padded with zeros. Although the maximum Crosstalk space *
680 * addressable by the SHub is thus the lower 16 GBytes per widget *
681 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
682 * space can be accessed. *
683 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
684 * Window number) are used to select one of these 7 registers. The *
685 * Widget number field is then derived from the W_NUM field for *
686 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
687 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
688 * field is used as Crosstalk[47], and remainder of the Crosstalk *
689 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
690 * Crosstalk space addressable by the SHub is thus the lower *
691 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
692 * of this space can be accessed. *
693 * *
694 ************************************************************************/
695
696typedef union ii_itte4_u {
697 u64 ii_itte4_regval;
698 struct {
699 u64 i_offset:5;
700 u64 i_rsvd_1:3;
701 u64 i_w_num:4;
702 u64 i_iosp:1;
703 u64 i_rsvd:51;
704 } ii_itte4_fld_s;
705} ii_itte4_u_t;
706
707/************************************************************************
708 * *
709 * Description: There are seven instances of translation table entry *
710 * registers. Each register maps a SHub Big Window to a 48-bit *
711 * address on Crosstalk. *
712 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
713 * number) are used to select one of these 7 registers. The Widget *
714 * number field is then derived from the W_NUM field for synthesizing *
715 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
716 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
717 * are padded with zeros. Although the maximum Crosstalk space *
718 * addressable by the Shub is thus the lower 16 GBytes per widget *
719 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
720 * space can be accessed. *
721 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
722 * Window number) are used to select one of these 7 registers. The *
723 * Widget number field is then derived from the W_NUM field for *
724 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
725 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
726 * field is used as Crosstalk[47], and remainder of the Crosstalk *
727 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
728 * Crosstalk space addressable by the Shub is thus the lower *
729 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
730 * of this space can be accessed. *
731 * *
732 ************************************************************************/
733
734typedef union ii_itte5_u {
735 u64 ii_itte5_regval;
736 struct {
737 u64 i_offset:5;
738 u64 i_rsvd_1:3;
739 u64 i_w_num:4;
740 u64 i_iosp:1;
741 u64 i_rsvd:51;
742 } ii_itte5_fld_s;
743} ii_itte5_u_t;
744
745/************************************************************************
746 * *
747 * Description: There are seven instances of translation table entry *
748 * registers. Each register maps a Shub Big Window to a 48-bit *
749 * address on Crosstalk. *
750 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
751 * number) are used to select one of these 7 registers. The Widget *
752 * number field is then derived from the W_NUM field for synthesizing *
753 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
754 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
755 * are padded with zeros. Although the maximum Crosstalk space *
756 * addressable by the Shub is thus the lower 16 GBytes per widget *
757 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
758 * space can be accessed. *
759 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
760 * Window number) are used to select one of these 7 registers. The *
761 * Widget number field is then derived from the W_NUM field for *
762 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
763 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
764 * field is used as Crosstalk[47], and remainder of the Crosstalk *
765 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
766 * Crosstalk space addressable by the Shub is thus the lower *
767 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
768 * of this space can be accessed. *
769 * *
770 ************************************************************************/
771
772typedef union ii_itte6_u {
773 u64 ii_itte6_regval;
774 struct {
775 u64 i_offset:5;
776 u64 i_rsvd_1:3;
777 u64 i_w_num:4;
778 u64 i_iosp:1;
779 u64 i_rsvd:51;
780 } ii_itte6_fld_s;
781} ii_itte6_u_t;
782
783/************************************************************************
784 * *
785 * Description: There are seven instances of translation table entry *
786 * registers. Each register maps a Shub Big Window to a 48-bit *
787 * address on Crosstalk. *
788 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
789 * number) are used to select one of these 7 registers. The Widget *
790 * number field is then derived from the W_NUM field for synthesizing *
791 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
792 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
793 * are padded with zeros. Although the maximum Crosstalk space *
794 * addressable by the Shub is thus the lower 16 GBytes per widget *
795 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this *
796 * space can be accessed. *
797 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
798 * Window number) are used to select one of these 7 registers. The *
799 * Widget number field is then derived from the W_NUM field for *
800 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
801 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
802 * field is used as Crosstalk[47], and remainder of the Crosstalk *
803 * address bits (Crosstalk[46:34]) are always zero. While the maximum *
804 * Crosstalk space addressable by the SHub is thus the lower *
805 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> *
806 * of this space can be accessed. *
807 * *
808 ************************************************************************/
809
810typedef union ii_itte7_u {
811 u64 ii_itte7_regval;
812 struct {
813 u64 i_offset:5;
814 u64 i_rsvd_1:3;
815 u64 i_w_num:4;
816 u64 i_iosp:1;
817 u64 i_rsvd:51;
818 } ii_itte7_fld_s;
819} ii_itte7_u_t;
820
821/************************************************************************
822 * *
823 * Description: There are 9 instances of this register, one per *
824 * actual widget in this implementation of SHub and Crossbow. *
825 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
826 * refers to Crossbow's internal space. *
827 * This register contains the state elements per widget that are *
828 * necessary to manage the PIO flow control on Crosstalk and on the *
829 * Router Network. See the PIO Flow Control chapter for a complete *
830 * description of this register *
831 * The SPUR_WR bit requires some explanation. When this register is *
832 * written, the new value of the C field is captured in an internal *
833 * register so the hardware can remember what the programmer wrote *
834 * into the credit counter. The SPUR_WR bit sets whenever the C field *
835 * increments above this stored value, which indicates that there *
836 * have been more responses received than requests sent. The SPUR_WR *
837 * bit cannot be cleared until a value is written to the IPRBx *
838 * register; the write will correct the C field and capture its new *
839 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
840 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
841 * . *
842 * *
843 ************************************************************************/
844
845typedef union ii_iprb0_u {
846 u64 ii_iprb0_regval;
847 struct {
848 u64 i_c:8;
849 u64 i_na:14;
850 u64 i_rsvd_2:2;
851 u64 i_nb:14;
852 u64 i_rsvd_1:2;
853 u64 i_m:2;
854 u64 i_f:1;
855 u64 i_of_cnt:5;
856 u64 i_error:1;
857 u64 i_rd_to:1;
858 u64 i_spur_wr:1;
859 u64 i_spur_rd:1;
860 u64 i_rsvd:11;
861 u64 i_mult_err:1;
862 } ii_iprb0_fld_s;
863} ii_iprb0_u_t;
864
865/************************************************************************
866 * *
867 * Description: There are 9 instances of this register, one per *
868 * actual widget in this implementation of SHub and Crossbow. *
869 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
870 * refers to Crossbow's internal space. *
871 * This register contains the state elements per widget that are *
872 * necessary to manage the PIO flow control on Crosstalk and on the *
873 * Router Network. See the PIO Flow Control chapter for a complete *
874 * description of this register *
875 * The SPUR_WR bit requires some explanation. When this register is *
876 * written, the new value of the C field is captured in an internal *
877 * register so the hardware can remember what the programmer wrote *
878 * into the credit counter. The SPUR_WR bit sets whenever the C field *
879 * increments above this stored value, which indicates that there *
880 * have been more responses received than requests sent. The SPUR_WR *
881 * bit cannot be cleared until a value is written to the IPRBx *
882 * register; the write will correct the C field and capture its new *
883 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
884 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
885 * . *
886 * *
887 ************************************************************************/
888
889typedef union ii_iprb8_u {
890 u64 ii_iprb8_regval;
891 struct {
892 u64 i_c:8;
893 u64 i_na:14;
894 u64 i_rsvd_2:2;
895 u64 i_nb:14;
896 u64 i_rsvd_1:2;
897 u64 i_m:2;
898 u64 i_f:1;
899 u64 i_of_cnt:5;
900 u64 i_error:1;
901 u64 i_rd_to:1;
902 u64 i_spur_wr:1;
903 u64 i_spur_rd:1;
904 u64 i_rsvd:11;
905 u64 i_mult_err:1;
906 } ii_iprb8_fld_s;
907} ii_iprb8_u_t;
908
909/************************************************************************
910 * *
911 * Description: There are 9 instances of this register, one per *
912 * actual widget in this implementation of SHub and Crossbow. *
913 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
914 * refers to Crossbow's internal space. *
915 * This register contains the state elements per widget that are *
916 * necessary to manage the PIO flow control on Crosstalk and on the *
917 * Router Network. See the PIO Flow Control chapter for a complete *
918 * description of this register *
919 * The SPUR_WR bit requires some explanation. When this register is *
920 * written, the new value of the C field is captured in an internal *
921 * register so the hardware can remember what the programmer wrote *
922 * into the credit counter. The SPUR_WR bit sets whenever the C field *
923 * increments above this stored value, which indicates that there *
924 * have been more responses received than requests sent. The SPUR_WR *
925 * bit cannot be cleared until a value is written to the IPRBx *
926 * register; the write will correct the C field and capture its new *
927 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
928 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
929 * . *
930 * *
931 ************************************************************************/
932
933typedef union ii_iprb9_u {
934 u64 ii_iprb9_regval;
935 struct {
936 u64 i_c:8;
937 u64 i_na:14;
938 u64 i_rsvd_2:2;
939 u64 i_nb:14;
940 u64 i_rsvd_1:2;
941 u64 i_m:2;
942 u64 i_f:1;
943 u64 i_of_cnt:5;
944 u64 i_error:1;
945 u64 i_rd_to:1;
946 u64 i_spur_wr:1;
947 u64 i_spur_rd:1;
948 u64 i_rsvd:11;
949 u64 i_mult_err:1;
950 } ii_iprb9_fld_s;
951} ii_iprb9_u_t;
952
953/************************************************************************
954 * *
955 * Description: There are 9 instances of this register, one per *
956 * actual widget in this implementation of SHub and Crossbow. *
957 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
958 * refers to Crossbow's internal space. *
959 * This register contains the state elements per widget that are *
960 * necessary to manage the PIO flow control on Crosstalk and on the *
961 * Router Network. See the PIO Flow Control chapter for a complete *
962 * description of this register *
963 * The SPUR_WR bit requires some explanation. When this register is *
964 * written, the new value of the C field is captured in an internal *
965 * register so the hardware can remember what the programmer wrote *
966 * into the credit counter. The SPUR_WR bit sets whenever the C field *
967 * increments above this stored value, which indicates that there *
968 * have been more responses received than requests sent. The SPUR_WR *
969 * bit cannot be cleared until a value is written to the IPRBx *
970 * register; the write will correct the C field and capture its new *
971 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
972 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
973 * *
974 * *
975 ************************************************************************/
976
977typedef union ii_iprba_u {
978 u64 ii_iprba_regval;
979 struct {
980 u64 i_c:8;
981 u64 i_na:14;
982 u64 i_rsvd_2:2;
983 u64 i_nb:14;
984 u64 i_rsvd_1:2;
985 u64 i_m:2;
986 u64 i_f:1;
987 u64 i_of_cnt:5;
988 u64 i_error:1;
989 u64 i_rd_to:1;
990 u64 i_spur_wr:1;
991 u64 i_spur_rd:1;
992 u64 i_rsvd:11;
993 u64 i_mult_err:1;
994 } ii_iprba_fld_s;
995} ii_iprba_u_t;
996
997/************************************************************************
998 * *
999 * Description: There are 9 instances of this register, one per *
1000 * actual widget in this implementation of SHub and Crossbow. *
1001 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1002 * refers to Crossbow's internal space. *
1003 * This register contains the state elements per widget that are *
1004 * necessary to manage the PIO flow control on Crosstalk and on the *
1005 * Router Network. See the PIO Flow Control chapter for a complete *
1006 * description of this register *
1007 * The SPUR_WR bit requires some explanation. When this register is *
1008 * written, the new value of the C field is captured in an internal *
1009 * register so the hardware can remember what the programmer wrote *
1010 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1011 * increments above this stored value, which indicates that there *
1012 * have been more responses received than requests sent. The SPUR_WR *
1013 * bit cannot be cleared until a value is written to the IPRBx *
1014 * register; the write will correct the C field and capture its new *
1015 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1016 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1017 * . *
1018 * *
1019 ************************************************************************/
1020
1021typedef union ii_iprbb_u {
1022 u64 ii_iprbb_regval;
1023 struct {
1024 u64 i_c:8;
1025 u64 i_na:14;
1026 u64 i_rsvd_2:2;
1027 u64 i_nb:14;
1028 u64 i_rsvd_1:2;
1029 u64 i_m:2;
1030 u64 i_f:1;
1031 u64 i_of_cnt:5;
1032 u64 i_error:1;
1033 u64 i_rd_to:1;
1034 u64 i_spur_wr:1;
1035 u64 i_spur_rd:1;
1036 u64 i_rsvd:11;
1037 u64 i_mult_err:1;
1038 } ii_iprbb_fld_s;
1039} ii_iprbb_u_t;
1040
1041/************************************************************************
1042 * *
1043 * Description: There are 9 instances of this register, one per *
1044 * actual widget in this implementation of SHub and Crossbow. *
1045 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1046 * refers to Crossbow's internal space. *
1047 * This register contains the state elements per widget that are *
1048 * necessary to manage the PIO flow control on Crosstalk and on the *
1049 * Router Network. See the PIO Flow Control chapter for a complete *
1050 * description of this register *
1051 * The SPUR_WR bit requires some explanation. When this register is *
1052 * written, the new value of the C field is captured in an internal *
1053 * register so the hardware can remember what the programmer wrote *
1054 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1055 * increments above this stored value, which indicates that there *
1056 * have been more responses received than requests sent. The SPUR_WR *
1057 * bit cannot be cleared until a value is written to the IPRBx *
1058 * register; the write will correct the C field and capture its new *
1059 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1060 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1061 * . *
1062 * *
1063 ************************************************************************/
1064
1065typedef union ii_iprbc_u {
1066 u64 ii_iprbc_regval;
1067 struct {
1068 u64 i_c:8;
1069 u64 i_na:14;
1070 u64 i_rsvd_2:2;
1071 u64 i_nb:14;
1072 u64 i_rsvd_1:2;
1073 u64 i_m:2;
1074 u64 i_f:1;
1075 u64 i_of_cnt:5;
1076 u64 i_error:1;
1077 u64 i_rd_to:1;
1078 u64 i_spur_wr:1;
1079 u64 i_spur_rd:1;
1080 u64 i_rsvd:11;
1081 u64 i_mult_err:1;
1082 } ii_iprbc_fld_s;
1083} ii_iprbc_u_t;
1084
1085/************************************************************************
1086 * *
1087 * Description: There are 9 instances of this register, one per *
1088 * actual widget in this implementation of SHub and Crossbow. *
1089 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1090 * refers to Crossbow's internal space. *
1091 * This register contains the state elements per widget that are *
1092 * necessary to manage the PIO flow control on Crosstalk and on the *
1093 * Router Network. See the PIO Flow Control chapter for a complete *
1094 * description of this register *
1095 * The SPUR_WR bit requires some explanation. When this register is *
1096 * written, the new value of the C field is captured in an internal *
1097 * register so the hardware can remember what the programmer wrote *
1098 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1099 * increments above this stored value, which indicates that there *
1100 * have been more responses received than requests sent. The SPUR_WR *
1101 * bit cannot be cleared until a value is written to the IPRBx *
1102 * register; the write will correct the C field and capture its new *
1103 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1104 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1105 * . *
1106 * *
1107 ************************************************************************/
1108
1109typedef union ii_iprbd_u {
1110 u64 ii_iprbd_regval;
1111 struct {
1112 u64 i_c:8;
1113 u64 i_na:14;
1114 u64 i_rsvd_2:2;
1115 u64 i_nb:14;
1116 u64 i_rsvd_1:2;
1117 u64 i_m:2;
1118 u64 i_f:1;
1119 u64 i_of_cnt:5;
1120 u64 i_error:1;
1121 u64 i_rd_to:1;
1122 u64 i_spur_wr:1;
1123 u64 i_spur_rd:1;
1124 u64 i_rsvd:11;
1125 u64 i_mult_err:1;
1126 } ii_iprbd_fld_s;
1127} ii_iprbd_u_t;
1128
1129/************************************************************************
1130 * *
1131 * Description: There are 9 instances of this register, one per *
1132 * actual widget in this implementation of SHub and Crossbow. *
1133 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1134 * refers to Crossbow's internal space. *
1135 * This register contains the state elements per widget that are *
1136 * necessary to manage the PIO flow control on Crosstalk and on the *
1137 * Router Network. See the PIO Flow Control chapter for a complete *
1138 * description of this register *
1139 * The SPUR_WR bit requires some explanation. When this register is *
1140 * written, the new value of the C field is captured in an internal *
1141 * register so the hardware can remember what the programmer wrote *
1142 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1143 * increments above this stored value, which indicates that there *
1144 * have been more responses received than requests sent. The SPUR_WR *
1145 * bit cannot be cleared until a value is written to the IPRBx *
1146 * register; the write will correct the C field and capture its new *
1147 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1148 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1149 * . *
1150 * *
1151 ************************************************************************/
1152
1153typedef union ii_iprbe_u {
1154 u64 ii_iprbe_regval;
1155 struct {
1156 u64 i_c:8;
1157 u64 i_na:14;
1158 u64 i_rsvd_2:2;
1159 u64 i_nb:14;
1160 u64 i_rsvd_1:2;
1161 u64 i_m:2;
1162 u64 i_f:1;
1163 u64 i_of_cnt:5;
1164 u64 i_error:1;
1165 u64 i_rd_to:1;
1166 u64 i_spur_wr:1;
1167 u64 i_spur_rd:1;
1168 u64 i_rsvd:11;
1169 u64 i_mult_err:1;
1170 } ii_iprbe_fld_s;
1171} ii_iprbe_u_t;
1172
1173/************************************************************************
1174 * *
1175 * Description: There are 9 instances of this register, one per *
1176 * actual widget in this implementation of Shub and Crossbow. *
1177 * Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
1178 * refers to Crossbow's internal space. *
1179 * This register contains the state elements per widget that are *
1180 * necessary to manage the PIO flow control on Crosstalk and on the *
1181 * Router Network. See the PIO Flow Control chapter for a complete *
1182 * description of this register *
1183 * The SPUR_WR bit requires some explanation. When this register is *
1184 * written, the new value of the C field is captured in an internal *
1185 * register so the hardware can remember what the programmer wrote *
1186 * into the credit counter. The SPUR_WR bit sets whenever the C field *
1187 * increments above this stored value, which indicates that there *
1188 * have been more responses received than requests sent. The SPUR_WR *
1189 * bit cannot be cleared until a value is written to the IPRBx *
1190 * register; the write will correct the C field and capture its new *
1191 * value in the internal register. Even if IECLR[E_PRB_x] is set, the *
1192 * SPUR_WR bit will persist if IPRBx hasn't yet been written. *
1193 * . *
1194 * *
1195 ************************************************************************/
1196
1197typedef union ii_iprbf_u {
1198 u64 ii_iprbf_regval;
1199 struct {
1200 u64 i_c:8;
1201 u64 i_na:14;
1202 u64 i_rsvd_2:2;
1203 u64 i_nb:14;
1204 u64 i_rsvd_1:2;
1205 u64 i_m:2;
1206 u64 i_f:1;
1207 u64 i_of_cnt:5;
1208 u64 i_error:1;
1209 u64 i_rd_to:1;
1210 u64 i_spur_wr:1;
1211 u64 i_spur_rd:1;
1212 u64 i_rsvd:11;
1213 u64 i_mult_err:1;
1214 } ii_iprbe_fld_s;
1215} ii_iprbf_u_t;
1216
1217/************************************************************************
1218 * *
1219 * This register specifies the timeout value to use for monitoring *
1220 * Crosstalk credits which are used outbound to Crosstalk. An *
1221 * internal counter called the Crosstalk Credit Timeout Counter *
1222 * increments every 128 II clocks. The counter starts counting *
1223 * anytime the credit count drops below a threshold, and resets to *
1224 * zero (stops counting) anytime the credit count is at or above the *
1225 * threshold. The threshold is 1 credit in direct connect mode and 2 *
1226 * in Crossbow connect mode. When the internal Crosstalk Credit *
1227 * Timeout Counter reaches the value programmed in this register, a *
1228 * Crosstalk Credit Timeout has occurred. The internal counter is not *
1229 * readable from software, and stops counting at its maximum value, *
1230 * so it cannot cause more than one interrupt. *
1231 * *
1232 ************************************************************************/
1233
1234typedef union ii_ixcc_u {
1235 u64 ii_ixcc_regval;
1236 struct {
1237 u64 i_time_out:26;
1238 u64 i_rsvd:38;
1239 } ii_ixcc_fld_s;
1240} ii_ixcc_u_t;
1241
1242/************************************************************************
1243 * *
1244 * Description: This register qualifies all the PIO and DMA *
1245 * operations launched from widget 0 towards the SHub. In *
1246 * addition, it also qualifies accesses by the BTE streams. *
1247 * The bits in each field of this register are cleared by the SHub *
1248 * upon detection of an error which requires widget 0 or the BTE *
1249 * streams to be terminated. Whether or not widget x has access *
1250 * rights to this SHub is determined by an AND of the device *
1251 * enable bit in the appropriate field of this register and bit 0 in *
1252 * the Wx_IAC field. The bits in this field are set by writing a 1 to *
1253 * them. Incoming replies from Crosstalk are not subject to this *
1254 * access control mechanism. *
1255 * *
1256 ************************************************************************/
1257
1258typedef union ii_imem_u {
1259 u64 ii_imem_regval;
1260 struct {
1261 u64 i_w0_esd:1;
1262 u64 i_rsvd_3:3;
1263 u64 i_b0_esd:1;
1264 u64 i_rsvd_2:3;
1265 u64 i_b1_esd:1;
1266 u64 i_rsvd_1:3;
1267 u64 i_clr_precise:1;
1268 u64 i_rsvd:51;
1269 } ii_imem_fld_s;
1270} ii_imem_u_t;
1271
1272/************************************************************************
1273 * *
1274 * Description: This register specifies the timeout value to use for *
1275 * monitoring Crosstalk tail flits coming into the Shub in the *
1276 * TAIL_TO field. An internal counter associated with this register *
1277 * is incremented every 128 II internal clocks (7 bits). The counter *
1278 * starts counting anytime a header micropacket is received and stops *
1279 * counting (and resets to zero) any time a micropacket with a Tail *
1280 * bit is received. Once the counter reaches the threshold value *
1281 * programmed in this register, it generates an interrupt to the *
1282 * processor that is programmed into the IIDSR. The counter saturates *
1283 * (does not roll over) at its maximum value, so it cannot cause *
1284 * another interrupt until after it is cleared. *
1285 * The register also contains the Read Response Timeout values. The *
1286 * Prescalar is 23 bits, and counts II clocks. An internal counter *
1287 * increments on every II clock and when it reaches the value in the *
1288 * Prescalar field, all IPRTE registers with their valid bits set *
1289 * have their Read Response timers bumped. Whenever any of them match *
1290 * the value in the RRSP_TO field, a Read Response Timeout has *
1291 * occurred, and error handling occurs as described in the Error *
1292 * Handling section of this document. *
1293 * *
1294 ************************************************************************/
1295
1296typedef union ii_ixtt_u {
1297 u64 ii_ixtt_regval;
1298 struct {
1299 u64 i_tail_to:26;
1300 u64 i_rsvd_1:6;
1301 u64 i_rrsp_ps:23;
1302 u64 i_rrsp_to:5;
1303 u64 i_rsvd:4;
1304 } ii_ixtt_fld_s;
1305} ii_ixtt_u_t;
1306
1307/************************************************************************
1308 * *
1309 * Writing a 1 to the fields of this register clears the appropriate *
1310 * error bits in other areas of SHub. Note that when the *
1311 * E_PRB_x bits are used to clear error bits in PRB registers, *
1312 * SPUR_RD and SPUR_WR may persist, because they require additional *
1313 * action to clear them. See the IPRBx and IXSS Register *
1314 * specifications. *
1315 * *
1316 ************************************************************************/
1317
1318typedef union ii_ieclr_u {
1319 u64 ii_ieclr_regval;
1320 struct {
1321 u64 i_e_prb_0:1;
1322 u64 i_rsvd:7;
1323 u64 i_e_prb_8:1;
1324 u64 i_e_prb_9:1;
1325 u64 i_e_prb_a:1;
1326 u64 i_e_prb_b:1;
1327 u64 i_e_prb_c:1;
1328 u64 i_e_prb_d:1;
1329 u64 i_e_prb_e:1;
1330 u64 i_e_prb_f:1;
1331 u64 i_e_crazy:1;
1332 u64 i_e_bte_0:1;
1333 u64 i_e_bte_1:1;
1334 u64 i_reserved_1:10;
1335 u64 i_spur_rd_hdr:1;
1336 u64 i_cam_intr_to:1;
1337 u64 i_cam_overflow:1;
1338 u64 i_cam_read_miss:1;
1339 u64 i_ioq_rep_underflow:1;
1340 u64 i_ioq_req_underflow:1;
1341 u64 i_ioq_rep_overflow:1;
1342 u64 i_ioq_req_overflow:1;
1343 u64 i_iiq_rep_overflow:1;
1344 u64 i_iiq_req_overflow:1;
1345 u64 i_ii_xn_rep_cred_overflow:1;
1346 u64 i_ii_xn_req_cred_overflow:1;
1347 u64 i_ii_xn_invalid_cmd:1;
1348 u64 i_xn_ii_invalid_cmd:1;
1349 u64 i_reserved_2:21;
1350 } ii_ieclr_fld_s;
1351} ii_ieclr_u_t;
1352
1353/************************************************************************
1354 * *
1355 * This register controls both BTEs. SOFT_RESET is intended for *
1356 * recovery after an error. COUNT controls the total number of CRBs *
1357 * that both BTEs (combined) can use, which affects total BTE *
1358 * bandwidth. *
1359 * *
1360 ************************************************************************/
1361
1362typedef union ii_ibcr_u {
1363 u64 ii_ibcr_regval;
1364 struct {
1365 u64 i_count:4;
1366 u64 i_rsvd_1:4;
1367 u64 i_soft_reset:1;
1368 u64 i_rsvd:55;
1369 } ii_ibcr_fld_s;
1370} ii_ibcr_u_t;
1371
1372/************************************************************************
1373 * *
1374 * This register contains the header of a spurious read response *
1375 * received from Crosstalk. A spurious read response is defined as a *
1376 * read response received by II from a widget for which (1) the SIDN *
1377 * has a value between 1 and 7, inclusive (II never sends requests to *
1378 * these widgets (2) there is no valid IPRTE register which *
1379 * corresponds to the TNUM, or (3) the widget indicated in SIDN is *
1380 * not the same as the widget recorded in the IPRTE register *
1381 * referenced by the TNUM. If this condition is true, and if the *
1382 * IXSS[VALID] bit is clear, then the header of the spurious read *
1383 * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
1384 * errant header is thereby captured, and no further spurious read *
1385 * respones are captured until IXSS[VALID] is cleared by setting the *
1386 * appropriate bit in IECLR.Everytime a spurious read response is *
1387 * detected, the SPUR_RD bit of the PRB corresponding to the incoming *
1388 * message's SIDN field is set. This always happens, regarless of *
1389 * whether a header is captured. The programmer should check *
1390 * IXSM[SIDN] to determine which widget sent the spurious response, *
1391 * because there may be more than one SPUR_RD bit set in the PRB *
1392 * registers. The widget indicated by IXSM[SIDN] was the first *
1393 * spurious read response to be received since the last time *
1394 * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
1395 * will be set. Any SPUR_RD bits in any other PRB registers indicate *
1396 * spurious messages from other widets which were detected after the *
1397 * header was captured.. *
1398 * *
1399 ************************************************************************/
1400
1401typedef union ii_ixsm_u {
1402 u64 ii_ixsm_regval;
1403 struct {
1404 u64 i_byte_en:32;
1405 u64 i_reserved:1;
1406 u64 i_tag:3;
1407 u64 i_alt_pactyp:4;
1408 u64 i_bo:1;
1409 u64 i_error:1;
1410 u64 i_vbpm:1;
1411 u64 i_gbr:1;
1412 u64 i_ds:2;
1413 u64 i_ct:1;
1414 u64 i_tnum:5;
1415 u64 i_pactyp:4;
1416 u64 i_sidn:4;
1417 u64 i_didn:4;
1418 } ii_ixsm_fld_s;
1419} ii_ixsm_u_t;
1420
1421/************************************************************************
1422 * *
1423 * This register contains the sideband bits of a spurious read *
1424 * response received from Crosstalk. *
1425 * *
1426 ************************************************************************/
1427
1428typedef union ii_ixss_u {
1429 u64 ii_ixss_regval;
1430 struct {
1431 u64 i_sideband:8;
1432 u64 i_rsvd:55;
1433 u64 i_valid:1;
1434 } ii_ixss_fld_s;
1435} ii_ixss_u_t;
1436
1437/************************************************************************
1438 * *
1439 * This register enables software to access the II LLP's test port. *
1440 * Refer to the LLP 2.5 documentation for an explanation of the test *
1441 * port. Software can write to this register to program the values *
1442 * for the control fields (TestErrCapture, TestClear, TestFlit, *
1443 * TestMask and TestSeed). Similarly, software can read from this *
1444 * register to obtain the values of the test port's status outputs *
1445 * (TestCBerr, TestValid and TestData). *
1446 * *
1447 ************************************************************************/
1448
1449typedef union ii_ilct_u {
1450 u64 ii_ilct_regval;
1451 struct {
1452 u64 i_test_seed:20;
1453 u64 i_test_mask:8;
1454 u64 i_test_data:20;
1455 u64 i_test_valid:1;
1456 u64 i_test_cberr:1;
1457 u64 i_test_flit:3;
1458 u64 i_test_clear:1;
1459 u64 i_test_err_capture:1;
1460 u64 i_rsvd:9;
1461 } ii_ilct_fld_s;
1462} ii_ilct_u_t;
1463
1464/************************************************************************
1465 * *
1466 * If the II detects an illegal incoming Duplonet packet (request or *
1467 * reply) when VALID==0 in the IIEPH1 register, then it saves the *
1468 * contents of the packet's header flit in the IIEPH1 and IIEPH2 *
1469 * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
1470 * and assigns a value to the ERR_TYPE field which indicates the *
1471 * specific nature of the error. The II recognizes four different *
1472 * types of errors: short request packets (ERR_TYPE==2), short reply *
1473 * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
1474 * reply packets (ERR_TYPE==5). The encodings for these types of *
1475 * errors were chosen to be consistent with the same types of errors *
1476 * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
1477 * the LB unit). If the II detects an illegal incoming Duplonet *
1478 * packet when VALID==1 in the IIEPH1 register, then it merely sets *
1479 * the OVERRUN bit to indicate that a subsequent error has happened, *
1480 * and does nothing further. *
1481 * *
1482 ************************************************************************/
1483
1484typedef union ii_iieph1_u {
1485 u64 ii_iieph1_regval;
1486 struct {
1487 u64 i_command:7;
1488 u64 i_rsvd_5:1;
1489 u64 i_suppl:14;
1490 u64 i_rsvd_4:1;
1491 u64 i_source:14;
1492 u64 i_rsvd_3:1;
1493 u64 i_err_type:4;
1494 u64 i_rsvd_2:4;
1495 u64 i_overrun:1;
1496 u64 i_rsvd_1:3;
1497 u64 i_valid:1;
1498 u64 i_rsvd:13;
1499 } ii_iieph1_fld_s;
1500} ii_iieph1_u_t;
1501
1502/************************************************************************
1503 * *
1504 * This register holds the Address field from the header flit of an *
1505 * incoming erroneous Duplonet packet, along with the tail bit which *
1506 * accompanied this header flit. This register is essentially an *
1507 * extension of IIEPH1. Two registers were necessary because the 64 *
1508 * bits available in only a single register were insufficient to *
1509 * capture the entire header flit of an erroneous packet. *
1510 * *
1511 ************************************************************************/
1512
1513typedef union ii_iieph2_u {
1514 u64 ii_iieph2_regval;
1515 struct {
1516 u64 i_rsvd_0:3;
1517 u64 i_address:47;
1518 u64 i_rsvd_1:10;
1519 u64 i_tail:1;
1520 u64 i_rsvd:3;
1521 } ii_iieph2_fld_s;
1522} ii_iieph2_u_t;
1523
1524/******************************/
1525
1526/************************************************************************
1527 * *
1528 * This register's value is a bit vector that guards access from SXBs *
1529 * to local registers within the II as well as to external Crosstalk *
1530 * widgets *
1531 * *
1532 ************************************************************************/
1533
1534typedef union ii_islapr_u {
1535 u64 ii_islapr_regval;
1536 struct {
1537 u64 i_region:64;
1538 } ii_islapr_fld_s;
1539} ii_islapr_u_t;
1540
1541/************************************************************************
1542 * *
1543 * A write to this register of the 56-bit value "Pup+Bun" will cause *
1544 * the bit in the ISLAPR register corresponding to the region of the *
1545 * requestor to be set (access allowed). (
1546 * *
1547 ************************************************************************/
1548
1549typedef union ii_islapo_u {
1550 u64 ii_islapo_regval;
1551 struct {
1552 u64 i_io_sbx_ovrride:56;
1553 u64 i_rsvd:8;
1554 } ii_islapo_fld_s;
1555} ii_islapo_u_t;
1556
1557/************************************************************************
1558 * *
1559 * Determines how long the wrapper will wait aftr an interrupt is *
1560 * initially issued from the II before it times out the outstanding *
1561 * interrupt and drops it from the interrupt queue. *
1562 * *
1563 ************************************************************************/
1564
1565typedef union ii_iwi_u {
1566 u64 ii_iwi_regval;
1567 struct {
1568 u64 i_prescale:24;
1569 u64 i_rsvd:8;
1570 u64 i_timeout:8;
1571 u64 i_rsvd1:8;
1572 u64 i_intrpt_retry_period:8;
1573 u64 i_rsvd2:8;
1574 } ii_iwi_fld_s;
1575} ii_iwi_u_t;
1576
1577/************************************************************************
1578 * *
1579 * Log errors which have occurred in the II wrapper. The errors are *
1580 * cleared by writing to the IECLR register. *
1581 * *
1582 ************************************************************************/
1583
1584typedef union ii_iwel_u {
1585 u64 ii_iwel_regval;
1586 struct {
1587 u64 i_intr_timed_out:1;
1588 u64 i_rsvd:7;
1589 u64 i_cam_overflow:1;
1590 u64 i_cam_read_miss:1;
1591 u64 i_rsvd1:2;
1592 u64 i_ioq_rep_underflow:1;
1593 u64 i_ioq_req_underflow:1;
1594 u64 i_ioq_rep_overflow:1;
1595 u64 i_ioq_req_overflow:1;
1596 u64 i_iiq_rep_overflow:1;
1597 u64 i_iiq_req_overflow:1;
1598 u64 i_rsvd2:6;
1599 u64 i_ii_xn_rep_cred_over_under:1;
1600 u64 i_ii_xn_req_cred_over_under:1;
1601 u64 i_rsvd3:6;
1602 u64 i_ii_xn_invalid_cmd:1;
1603 u64 i_xn_ii_invalid_cmd:1;
1604 u64 i_rsvd4:30;
1605 } ii_iwel_fld_s;
1606} ii_iwel_u_t;
1607
1608/************************************************************************
1609 * *
1610 * Controls the II wrapper. *
1611 * *
1612 ************************************************************************/
1613
1614typedef union ii_iwc_u {
1615 u64 ii_iwc_regval;
1616 struct {
1617 u64 i_dma_byte_swap:1;
1618 u64 i_rsvd:3;
1619 u64 i_cam_read_lines_reset:1;
1620 u64 i_rsvd1:3;
1621 u64 i_ii_xn_cred_over_under_log:1;
1622 u64 i_rsvd2:19;
1623 u64 i_xn_rep_iq_depth:5;
1624 u64 i_rsvd3:3;
1625 u64 i_xn_req_iq_depth:5;
1626 u64 i_rsvd4:3;
1627 u64 i_iiq_depth:6;
1628 u64 i_rsvd5:12;
1629 u64 i_force_rep_cred:1;
1630 u64 i_force_req_cred:1;
1631 } ii_iwc_fld_s;
1632} ii_iwc_u_t;
1633
1634/************************************************************************
1635 * *
1636 * Status in the II wrapper. *
1637 * *
1638 ************************************************************************/
1639
1640typedef union ii_iws_u {
1641 u64 ii_iws_regval;
1642 struct {
1643 u64 i_xn_rep_iq_credits:5;
1644 u64 i_rsvd:3;
1645 u64 i_xn_req_iq_credits:5;
1646 u64 i_rsvd1:51;
1647 } ii_iws_fld_s;
1648} ii_iws_u_t;
1649
1650/************************************************************************
1651 * *
1652 * Masks errors in the IWEL register. *
1653 * *
1654 ************************************************************************/
1655
1656typedef union ii_iweim_u {
1657 u64 ii_iweim_regval;
1658 struct {
1659 u64 i_intr_timed_out:1;
1660 u64 i_rsvd:7;
1661 u64 i_cam_overflow:1;
1662 u64 i_cam_read_miss:1;
1663 u64 i_rsvd1:2;
1664 u64 i_ioq_rep_underflow:1;
1665 u64 i_ioq_req_underflow:1;
1666 u64 i_ioq_rep_overflow:1;
1667 u64 i_ioq_req_overflow:1;
1668 u64 i_iiq_rep_overflow:1;
1669 u64 i_iiq_req_overflow:1;
1670 u64 i_rsvd2:6;
1671 u64 i_ii_xn_rep_cred_overflow:1;
1672 u64 i_ii_xn_req_cred_overflow:1;
1673 u64 i_rsvd3:6;
1674 u64 i_ii_xn_invalid_cmd:1;
1675 u64 i_xn_ii_invalid_cmd:1;
1676 u64 i_rsvd4:30;
1677 } ii_iweim_fld_s;
1678} ii_iweim_u_t;
1679
1680/************************************************************************
1681 * *
1682 * A write to this register causes a particular field in the *
1683 * corresponding widget's PRB entry to be adjusted up or down by 1. *
1684 * This counter should be used when recovering from error and reset *
1685 * conditions. Note that software would be capable of causing *
1686 * inadvertent overflow or underflow of these counters. *
1687 * *
1688 ************************************************************************/
1689
1690typedef union ii_ipca_u {
1691 u64 ii_ipca_regval;
1692 struct {
1693 u64 i_wid:4;
1694 u64 i_adjust:1;
1695 u64 i_rsvd_1:3;
1696 u64 i_field:2;
1697 u64 i_rsvd:54;
1698 } ii_ipca_fld_s;
1699} ii_ipca_u_t;
1700
1701/************************************************************************
1702 * *
1703 * There are 8 instances of this register. This register contains *
1704 * the information that the II has to remember once it has launched a *
1705 * PIO Read operation. The contents are used to form the correct *
1706 * Router Network packet and direct the Crosstalk reply to the *
1707 * appropriate processor. *
1708 * *
1709 ************************************************************************/
1710
1711typedef union ii_iprte0a_u {
1712 u64 ii_iprte0a_regval;
1713 struct {
1714 u64 i_rsvd_1:54;
1715 u64 i_widget:4;
1716 u64 i_to_cnt:5;
1717 u64 i_vld:1;
1718 } ii_iprte0a_fld_s;
1719} ii_iprte0a_u_t;
1720
1721/************************************************************************
1722 * *
1723 * There are 8 instances of this register. This register contains *
1724 * the information that the II has to remember once it has launched a *
1725 * PIO Read operation. The contents are used to form the correct *
1726 * Router Network packet and direct the Crosstalk reply to the *
1727 * appropriate processor. *
1728 * *
1729 ************************************************************************/
1730
1731typedef union ii_iprte1a_u {
1732 u64 ii_iprte1a_regval;
1733 struct {
1734 u64 i_rsvd_1:54;
1735 u64 i_widget:4;
1736 u64 i_to_cnt:5;
1737 u64 i_vld:1;
1738 } ii_iprte1a_fld_s;
1739} ii_iprte1a_u_t;
1740
1741/************************************************************************
1742 * *
1743 * There are 8 instances of this register. This register contains *
1744 * the information that the II has to remember once it has launched a *
1745 * PIO Read operation. The contents are used to form the correct *
1746 * Router Network packet and direct the Crosstalk reply to the *
1747 * appropriate processor. *
1748 * *
1749 ************************************************************************/
1750
1751typedef union ii_iprte2a_u {
1752 u64 ii_iprte2a_regval;
1753 struct {
1754 u64 i_rsvd_1:54;
1755 u64 i_widget:4;
1756 u64 i_to_cnt:5;
1757 u64 i_vld:1;
1758 } ii_iprte2a_fld_s;
1759} ii_iprte2a_u_t;
1760
1761/************************************************************************
1762 * *
1763 * There are 8 instances of this register. This register contains *
1764 * the information that the II has to remember once it has launched a *
1765 * PIO Read operation. The contents are used to form the correct *
1766 * Router Network packet and direct the Crosstalk reply to the *
1767 * appropriate processor. *
1768 * *
1769 ************************************************************************/
1770
1771typedef union ii_iprte3a_u {
1772 u64 ii_iprte3a_regval;
1773 struct {
1774 u64 i_rsvd_1:54;
1775 u64 i_widget:4;
1776 u64 i_to_cnt:5;
1777 u64 i_vld:1;
1778 } ii_iprte3a_fld_s;
1779} ii_iprte3a_u_t;
1780
1781/************************************************************************
1782 * *
1783 * There are 8 instances of this register. This register contains *
1784 * the information that the II has to remember once it has launched a *
1785 * PIO Read operation. The contents are used to form the correct *
1786 * Router Network packet and direct the Crosstalk reply to the *
1787 * appropriate processor. *
1788 * *
1789 ************************************************************************/
1790
1791typedef union ii_iprte4a_u {
1792 u64 ii_iprte4a_regval;
1793 struct {
1794 u64 i_rsvd_1:54;
1795 u64 i_widget:4;
1796 u64 i_to_cnt:5;
1797 u64 i_vld:1;
1798 } ii_iprte4a_fld_s;
1799} ii_iprte4a_u_t;
1800
1801/************************************************************************
1802 * *
1803 * There are 8 instances of this register. This register contains *
1804 * the information that the II has to remember once it has launched a *
1805 * PIO Read operation. The contents are used to form the correct *
1806 * Router Network packet and direct the Crosstalk reply to the *
1807 * appropriate processor. *
1808 * *
1809 ************************************************************************/
1810
1811typedef union ii_iprte5a_u {
1812 u64 ii_iprte5a_regval;
1813 struct {
1814 u64 i_rsvd_1:54;
1815 u64 i_widget:4;
1816 u64 i_to_cnt:5;
1817 u64 i_vld:1;
1818 } ii_iprte5a_fld_s;
1819} ii_iprte5a_u_t;
1820
1821/************************************************************************
1822 * *
1823 * There are 8 instances of this register. This register contains *
1824 * the information that the II has to remember once it has launched a *
1825 * PIO Read operation. The contents are used to form the correct *
1826 * Router Network packet and direct the Crosstalk reply to the *
1827 * appropriate processor. *
1828 * *
1829 ************************************************************************/
1830
1831typedef union ii_iprte6a_u {
1832 u64 ii_iprte6a_regval;
1833 struct {
1834 u64 i_rsvd_1:54;
1835 u64 i_widget:4;
1836 u64 i_to_cnt:5;
1837 u64 i_vld:1;
1838 } ii_iprte6a_fld_s;
1839} ii_iprte6a_u_t;
1840
1841/************************************************************************
1842 * *
1843 * There are 8 instances of this register. This register contains *
1844 * the information that the II has to remember once it has launched a *
1845 * PIO Read operation. The contents are used to form the correct *
1846 * Router Network packet and direct the Crosstalk reply to the *
1847 * appropriate processor. *
1848 * *
1849 ************************************************************************/
1850
1851typedef union ii_iprte7a_u {
1852 u64 ii_iprte7a_regval;
1853 struct {
1854 u64 i_rsvd_1:54;
1855 u64 i_widget:4;
1856 u64 i_to_cnt:5;
1857 u64 i_vld:1;
1858 } ii_iprtea7_fld_s;
1859} ii_iprte7a_u_t;
1860
1861/************************************************************************
1862 * *
1863 * There are 8 instances of this register. This register contains *
1864 * the information that the II has to remember once it has launched a *
1865 * PIO Read operation. The contents are used to form the correct *
1866 * Router Network packet and direct the Crosstalk reply to the *
1867 * appropriate processor. *
1868 * *
1869 ************************************************************************/
1870
1871typedef union ii_iprte0b_u {
1872 u64 ii_iprte0b_regval;
1873 struct {
1874 u64 i_rsvd_1:3;
1875 u64 i_address:47;
1876 u64 i_init:3;
1877 u64 i_source:11;
1878 } ii_iprte0b_fld_s;
1879} ii_iprte0b_u_t;
1880
1881/************************************************************************
1882 * *
1883 * There are 8 instances of this register. This register contains *
1884 * the information that the II has to remember once it has launched a *
1885 * PIO Read operation. The contents are used to form the correct *
1886 * Router Network packet and direct the Crosstalk reply to the *
1887 * appropriate processor. *
1888 * *
1889 ************************************************************************/
1890
1891typedef union ii_iprte1b_u {
1892 u64 ii_iprte1b_regval;
1893 struct {
1894 u64 i_rsvd_1:3;
1895 u64 i_address:47;
1896 u64 i_init:3;
1897 u64 i_source:11;
1898 } ii_iprte1b_fld_s;
1899} ii_iprte1b_u_t;
1900
1901/************************************************************************
1902 * *
1903 * There are 8 instances of this register. This register contains *
1904 * the information that the II has to remember once it has launched a *
1905 * PIO Read operation. The contents are used to form the correct *
1906 * Router Network packet and direct the Crosstalk reply to the *
1907 * appropriate processor. *
1908 * *
1909 ************************************************************************/
1910
1911typedef union ii_iprte2b_u {
1912 u64 ii_iprte2b_regval;
1913 struct {
1914 u64 i_rsvd_1:3;
1915 u64 i_address:47;
1916 u64 i_init:3;
1917 u64 i_source:11;
1918 } ii_iprte2b_fld_s;
1919} ii_iprte2b_u_t;
1920
1921/************************************************************************
1922 * *
1923 * There are 8 instances of this register. This register contains *
1924 * the information that the II has to remember once it has launched a *
1925 * PIO Read operation. The contents are used to form the correct *
1926 * Router Network packet and direct the Crosstalk reply to the *
1927 * appropriate processor. *
1928 * *
1929 ************************************************************************/
1930
1931typedef union ii_iprte3b_u {
1932 u64 ii_iprte3b_regval;
1933 struct {
1934 u64 i_rsvd_1:3;
1935 u64 i_address:47;
1936 u64 i_init:3;
1937 u64 i_source:11;
1938 } ii_iprte3b_fld_s;
1939} ii_iprte3b_u_t;
1940
1941/************************************************************************
1942 * *
1943 * There are 8 instances of this register. This register contains *
1944 * the information that the II has to remember once it has launched a *
1945 * PIO Read operation. The contents are used to form the correct *
1946 * Router Network packet and direct the Crosstalk reply to the *
1947 * appropriate processor. *
1948 * *
1949 ************************************************************************/
1950
1951typedef union ii_iprte4b_u {
1952 u64 ii_iprte4b_regval;
1953 struct {
1954 u64 i_rsvd_1:3;
1955 u64 i_address:47;
1956 u64 i_init:3;
1957 u64 i_source:11;
1958 } ii_iprte4b_fld_s;
1959} ii_iprte4b_u_t;
1960
1961/************************************************************************
1962 * *
1963 * There are 8 instances of this register. This register contains *
1964 * the information that the II has to remember once it has launched a *
1965 * PIO Read operation. The contents are used to form the correct *
1966 * Router Network packet and direct the Crosstalk reply to the *
1967 * appropriate processor. *
1968 * *
1969 ************************************************************************/
1970
1971typedef union ii_iprte5b_u {
1972 u64 ii_iprte5b_regval;
1973 struct {
1974 u64 i_rsvd_1:3;
1975 u64 i_address:47;
1976 u64 i_init:3;
1977 u64 i_source:11;
1978 } ii_iprte5b_fld_s;
1979} ii_iprte5b_u_t;
1980
1981/************************************************************************
1982 * *
1983 * There are 8 instances of this register. This register contains *
1984 * the information that the II has to remember once it has launched a *
1985 * PIO Read operation. The contents are used to form the correct *
1986 * Router Network packet and direct the Crosstalk reply to the *
1987 * appropriate processor. *
1988 * *
1989 ************************************************************************/
1990
1991typedef union ii_iprte6b_u {
1992 u64 ii_iprte6b_regval;
1993 struct {
1994 u64 i_rsvd_1:3;
1995 u64 i_address:47;
1996 u64 i_init:3;
1997 u64 i_source:11;
1998
1999 } ii_iprte6b_fld_s;
2000} ii_iprte6b_u_t;
2001
2002/************************************************************************
2003 * *
2004 * There are 8 instances of this register. This register contains *
2005 * the information that the II has to remember once it has launched a *
2006 * PIO Read operation. The contents are used to form the correct *
2007 * Router Network packet and direct the Crosstalk reply to the *
2008 * appropriate processor. *
2009 * *
2010 ************************************************************************/
2011
2012typedef union ii_iprte7b_u {
2013 u64 ii_iprte7b_regval;
2014 struct {
2015 u64 i_rsvd_1:3;
2016 u64 i_address:47;
2017 u64 i_init:3;
2018 u64 i_source:11;
2019 } ii_iprte7b_fld_s;
2020} ii_iprte7b_u_t;
2021
2022/************************************************************************
2023 * *
2024 * Description: SHub II contains a feature which did not exist in *
2025 * the Hub which automatically cleans up after a Read Response *
2026 * timeout, including deallocation of the IPRTE and recovery of IBuf *
2027 * space. The inclusion of this register in SHub is for backward *
2028 * compatibility *
2029 * A write to this register causes an entry from the table of *
2030 * outstanding PIO Read Requests to be freed and returned to the *
2031 * stack of free entries. This register is used in handling the *
2032 * timeout errors that result in a PIO Reply never returning from *
2033 * Crosstalk. *
2034 * Note that this register does not affect the contents of the IPRTE *
2035 * registers. The Valid bits in those registers have to be *
2036 * specifically turned off by software. *
2037 * *
2038 ************************************************************************/
2039
2040typedef union ii_ipdr_u {
2041 u64 ii_ipdr_regval;
2042 struct {
2043 u64 i_te:3;
2044 u64 i_rsvd_1:1;
2045 u64 i_pnd:1;
2046 u64 i_init_rpcnt:1;
2047 u64 i_rsvd:58;
2048 } ii_ipdr_fld_s;
2049} ii_ipdr_u_t;
2050
2051/************************************************************************
2052 * *
2053 * A write to this register causes a CRB entry to be returned to the *
2054 * queue of free CRBs. The entry should have previously been cleared *
2055 * (mark bit) via backdoor access to the pertinent CRB entry. This *
2056 * register is used in the last step of handling the errors that are *
2057 * captured and marked in CRB entries. Briefly: 1) first error for *
2058 * DMA write from a particular device, and first error for a *
2059 * particular BTE stream, lead to a marked CRB entry, and processor *
2060 * interrupt, 2) software reads the error information captured in the *
2061 * CRB entry, and presumably takes some corrective action, 3) *
2062 * software clears the mark bit, and finally 4) software writes to *
2063 * the ICDR register to return the CRB entry to the list of free CRB *
2064 * entries. *
2065 * *
2066 ************************************************************************/
2067
2068typedef union ii_icdr_u {
2069 u64 ii_icdr_regval;
2070 struct {
2071 u64 i_crb_num:4;
2072 u64 i_pnd:1;
2073 u64 i_rsvd:59;
2074 } ii_icdr_fld_s;
2075} ii_icdr_u_t;
2076
2077/************************************************************************
2078 * *
2079 * This register provides debug access to two FIFOs inside of II. *
2080 * Both IOQ_MAX* fields of this register contain the instantaneous *
2081 * depth (in units of the number of available entries) of the *
2082 * associated IOQ FIFO. A read of this register will return the *
2083 * number of free entries on each FIFO at the time of the read. So *
2084 * when a FIFO is idle, the associated field contains the maximum *
2085 * depth of the FIFO. This register is writable for debug reasons *
2086 * and is intended to be written with the maximum desired FIFO depth *
2087 * while the FIFO is idle. Software must assure that II is idle when *
2088 * this register is written. If there are any active entries in any *
2089 * of these FIFOs when this register is written, the results are *
2090 * undefined. *
2091 * *
2092 ************************************************************************/
2093
2094typedef union ii_ifdr_u {
2095 u64 ii_ifdr_regval;
2096 struct {
2097 u64 i_ioq_max_rq:7;
2098 u64 i_set_ioq_rq:1;
2099 u64 i_ioq_max_rp:7;
2100 u64 i_set_ioq_rp:1;
2101 u64 i_rsvd:48;
2102 } ii_ifdr_fld_s;
2103} ii_ifdr_u_t;
2104
2105/************************************************************************
2106 * *
2107 * This register allows the II to become sluggish in removing *
2108 * messages from its inbound queue (IIQ). This will cause messages to *
2109 * back up in either virtual channel. Disabling the "molasses" mode *
2110 * subsequently allows the II to be tested under stress. In the *
2111 * sluggish ("Molasses") mode, the localized effects of congestion *
2112 * can be observed. *
2113 * *
2114 ************************************************************************/
2115
2116typedef union ii_iiap_u {
2117 u64 ii_iiap_regval;
2118 struct {
2119 u64 i_rq_mls:6;
2120 u64 i_rsvd_1:2;
2121 u64 i_rp_mls:6;
2122 u64 i_rsvd:50;
2123 } ii_iiap_fld_s;
2124} ii_iiap_u_t;
2125
2126/************************************************************************
2127 * *
2128 * This register allows several parameters of CRB operation to be *
2129 * set. Note that writing to this register can have catastrophic side *
2130 * effects, if the CRB is not quiescent, i.e. if the CRB is *
2131 * processing protocol messages when the write occurs. *
2132 * *
2133 ************************************************************************/
2134
2135typedef union ii_icmr_u {
2136 u64 ii_icmr_regval;
2137 struct {
2138 u64 i_sp_msg:1;
2139 u64 i_rd_hdr:1;
2140 u64 i_rsvd_4:2;
2141 u64 i_c_cnt:4;
2142 u64 i_rsvd_3:4;
2143 u64 i_clr_rqpd:1;
2144 u64 i_clr_rppd:1;
2145 u64 i_rsvd_2:2;
2146 u64 i_fc_cnt:4;
2147 u64 i_crb_vld:15;
2148 u64 i_crb_mark:15;
2149 u64 i_rsvd_1:2;
2150 u64 i_precise:1;
2151 u64 i_rsvd:11;
2152 } ii_icmr_fld_s;
2153} ii_icmr_u_t;
2154
2155/************************************************************************
2156 * *
2157 * This register allows control of the table portion of the CRB *
2158 * logic via software. Control operations from this register have *
2159 * priority over all incoming Crosstalk or BTE requests. *
2160 * *
2161 ************************************************************************/
2162
2163typedef union ii_iccr_u {
2164 u64 ii_iccr_regval;
2165 struct {
2166 u64 i_crb_num:4;
2167 u64 i_rsvd_1:4;
2168 u64 i_cmd:8;
2169 u64 i_pending:1;
2170 u64 i_rsvd:47;
2171 } ii_iccr_fld_s;
2172} ii_iccr_u_t;
2173
2174/************************************************************************
2175 * *
2176 * This register allows the maximum timeout value to be programmed. *
2177 * *
2178 ************************************************************************/
2179
2180typedef union ii_icto_u {
2181 u64 ii_icto_regval;
2182 struct {
2183 u64 i_timeout:8;
2184 u64 i_rsvd:56;
2185 } ii_icto_fld_s;
2186} ii_icto_u_t;
2187
2188/************************************************************************
2189 * *
2190 * This register allows the timeout prescalar to be programmed. An *
2191 * internal counter is associated with this register. When the *
2192 * internal counter reaches the value of the PRESCALE field, the *
2193 * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] *
2194 * field). The internal counter resets to zero, and then continues *
2195 * counting. *
2196 * *
2197 ************************************************************************/
2198
2199typedef union ii_ictp_u {
2200 u64 ii_ictp_regval;
2201 struct {
2202 u64 i_prescale:24;
2203 u64 i_rsvd:40;
2204 } ii_ictp_fld_s;
2205} ii_ictp_u_t;
2206
2207/************************************************************************
2208 * *
2209 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2210 * used for Crosstalk operations (both cacheline and partial *
2211 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2212 * registers (_A to _E) are required to read and write each entry. *
2213 * The CRB Entry registers can be conceptualized as rows and columns *
2214 * (illustrated in the table above). Each row contains the 4 *
2215 * registers required for a single CRB Entry. The first doubleword *
2216 * (column) for each entry is labeled A, and the second doubleword *
2217 * (higher address) is labeled B, the third doubleword is labeled C, *
2218 * the fourth doubleword is labeled D and the fifth doubleword is *
2219 * labeled E. All CRB entries have their addresses on a quarter *
2220 * cacheline aligned boundary. *
2221 * Upon reset, only the following fields are initialized: valid *
2222 * (VLD), priority count, timeout, timeout valid, and context valid. *
2223 * All other bits should be cleared by software before use (after *
2224 * recovering any potential error state from before the reset). *
2225 * The following four tables summarize the format for the four *
2226 * registers that are used for each ICRB# Entry. *
2227 * *
2228 ************************************************************************/
2229
2230typedef union ii_icrb0_a_u {
2231 u64 ii_icrb0_a_regval;
2232 struct {
2233 u64 ia_iow:1;
2234 u64 ia_vld:1;
2235 u64 ia_addr:47;
2236 u64 ia_tnum:5;
2237 u64 ia_sidn:4;
2238 u64 ia_rsvd:6;
2239 } ii_icrb0_a_fld_s;
2240} ii_icrb0_a_u_t;
2241
2242/************************************************************************
2243 * *
2244 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2245 * used for Crosstalk operations (both cacheline and partial *
2246 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2247 * registers (_A to _E) are required to read and write each entry. *
2248 * *
2249 ************************************************************************/
2250
2251typedef union ii_icrb0_b_u {
2252 u64 ii_icrb0_b_regval;
2253 struct {
2254 u64 ib_xt_err:1;
2255 u64 ib_mark:1;
2256 u64 ib_ln_uce:1;
2257 u64 ib_errcode:3;
2258 u64 ib_error:1;
2259 u64 ib_stall__bte_1:1;
2260 u64 ib_stall__bte_0:1;
2261 u64 ib_stall__intr:1;
2262 u64 ib_stall_ib:1;
2263 u64 ib_intvn:1;
2264 u64 ib_wb:1;
2265 u64 ib_hold:1;
2266 u64 ib_ack:1;
2267 u64 ib_resp:1;
2268 u64 ib_ack_cnt:11;
2269 u64 ib_rsvd:7;
2270 u64 ib_exc:5;
2271 u64 ib_init:3;
2272 u64 ib_imsg:8;
2273 u64 ib_imsgtype:2;
2274 u64 ib_use_old:1;
2275 u64 ib_rsvd_1:11;
2276 } ii_icrb0_b_fld_s;
2277} ii_icrb0_b_u_t;
2278
2279/************************************************************************
2280 * *
2281 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2282 * used for Crosstalk operations (both cacheline and partial *
2283 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2284 * registers (_A to _E) are required to read and write each entry. *
2285 * *
2286 ************************************************************************/
2287
2288typedef union ii_icrb0_c_u {
2289 u64 ii_icrb0_c_regval;
2290 struct {
2291 u64 ic_source:15;
2292 u64 ic_size:2;
2293 u64 ic_ct:1;
2294 u64 ic_bte_num:1;
2295 u64 ic_gbr:1;
2296 u64 ic_resprqd:1;
2297 u64 ic_bo:1;
2298 u64 ic_suppl:15;
2299 u64 ic_rsvd:27;
2300 } ii_icrb0_c_fld_s;
2301} ii_icrb0_c_u_t;
2302
2303/************************************************************************
2304 * *
2305 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2306 * used for Crosstalk operations (both cacheline and partial *
2307 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2308 * registers (_A to _E) are required to read and write each entry. *
2309 * *
2310 ************************************************************************/
2311
2312typedef union ii_icrb0_d_u {
2313 u64 ii_icrb0_d_regval;
2314 struct {
2315 u64 id_pa_be:43;
2316 u64 id_bte_op:1;
2317 u64 id_pr_psc:4;
2318 u64 id_pr_cnt:4;
2319 u64 id_sleep:1;
2320 u64 id_rsvd:11;
2321 } ii_icrb0_d_fld_s;
2322} ii_icrb0_d_u_t;
2323
2324/************************************************************************
2325 * *
2326 * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are *
2327 * used for Crosstalk operations (both cacheline and partial *
2328 * operations) or BTE/IO. Because the CRB entries are very wide, five *
2329 * registers (_A to _E) are required to read and write each entry. *
2330 * *
2331 ************************************************************************/
2332
2333typedef union ii_icrb0_e_u {
2334 u64 ii_icrb0_e_regval;
2335 struct {
2336 u64 ie_timeout:8;
2337 u64 ie_context:15;
2338 u64 ie_rsvd:1;
2339 u64 ie_tvld:1;
2340 u64 ie_cvld:1;
2341 u64 ie_rsvd_0:38;
2342 } ii_icrb0_e_fld_s;
2343} ii_icrb0_e_u_t;
2344
2345/************************************************************************
2346 * *
2347 * This register contains the lower 64 bits of the header of the *
2348 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2349 * register is set. *
2350 * *
2351 ************************************************************************/
2352
2353typedef union ii_icsml_u {
2354 u64 ii_icsml_regval;
2355 struct {
2356 u64 i_tt_addr:47;
2357 u64 i_newsuppl_ex:14;
2358 u64 i_reserved:2;
2359 u64 i_overflow:1;
2360 } ii_icsml_fld_s;
2361} ii_icsml_u_t;
2362
2363/************************************************************************
2364 * *
2365 * This register contains the middle 64 bits of the header of the *
2366 * spurious message captured by II. Valid when the SP_MSG bit in ICMR *
2367 * register is set. *
2368 * *
2369 ************************************************************************/
2370
2371typedef union ii_icsmm_u {
2372 u64 ii_icsmm_regval;
2373 struct {
2374 u64 i_tt_ack_cnt:11;
2375 u64 i_reserved:53;
2376 } ii_icsmm_fld_s;
2377} ii_icsmm_u_t;
2378
2379/************************************************************************
2380 * *
2381 * This register contains the microscopic state, all the inputs to *
2382 * the protocol table, captured with the spurious message. Valid when *
2383 * the SP_MSG bit in the ICMR register is set. *
2384 * *
2385 ************************************************************************/
2386
2387typedef union ii_icsmh_u {
2388 u64 ii_icsmh_regval;
2389 struct {
2390 u64 i_tt_vld:1;
2391 u64 i_xerr:1;
2392 u64 i_ft_cwact_o:1;
2393 u64 i_ft_wact_o:1;
2394 u64 i_ft_active_o:1;
2395 u64 i_sync:1;
2396 u64 i_mnusg:1;
2397 u64 i_mnusz:1;
2398 u64 i_plusz:1;
2399 u64 i_plusg:1;
2400 u64 i_tt_exc:5;
2401 u64 i_tt_wb:1;
2402 u64 i_tt_hold:1;
2403 u64 i_tt_ack:1;
2404 u64 i_tt_resp:1;
2405 u64 i_tt_intvn:1;
2406 u64 i_g_stall_bte1:1;
2407 u64 i_g_stall_bte0:1;
2408 u64 i_g_stall_il:1;
2409 u64 i_g_stall_ib:1;
2410 u64 i_tt_imsg:8;
2411 u64 i_tt_imsgtype:2;
2412 u64 i_tt_use_old:1;
2413 u64 i_tt_respreqd:1;
2414 u64 i_tt_bte_num:1;
2415 u64 i_cbn:1;
2416 u64 i_match:1;
2417 u64 i_rpcnt_lt_34:1;
2418 u64 i_rpcnt_ge_34:1;
2419 u64 i_rpcnt_lt_18:1;
2420 u64 i_rpcnt_ge_18:1;
2421 u64 i_rpcnt_lt_2:1;
2422 u64 i_rpcnt_ge_2:1;
2423 u64 i_rqcnt_lt_18:1;
2424 u64 i_rqcnt_ge_18:1;
2425 u64 i_rqcnt_lt_2:1;
2426 u64 i_rqcnt_ge_2:1;
2427 u64 i_tt_device:7;
2428 u64 i_tt_init:3;
2429 u64 i_reserved:5;
2430 } ii_icsmh_fld_s;
2431} ii_icsmh_u_t;
2432
2433/************************************************************************
2434 * *
2435 * The Shub DEBUG unit provides a 3-bit selection signal to the *
2436 * II core and a 3-bit selection signal to the fsbclk domain in the II *
2437 * wrapper. *
2438 * *
2439 ************************************************************************/
2440
2441typedef union ii_idbss_u {
2442 u64 ii_idbss_regval;
2443 struct {
2444 u64 i_iioclk_core_submenu:3;
2445 u64 i_rsvd:5;
2446 u64 i_fsbclk_wrapper_submenu:3;
2447 u64 i_rsvd_1:5;
2448 u64 i_iioclk_menu:5;
2449 u64 i_rsvd_2:43;
2450 } ii_idbss_fld_s;
2451} ii_idbss_u_t;
2452
2453/************************************************************************
2454 * *
2455 * Description: This register is used to set up the length for a *
2456 * transfer and then to monitor the progress of that transfer. This *
2457 * register needs to be initialized before a transfer is started. A *
2458 * legitimate write to this register will set the Busy bit, clear the *
2459 * Error bit, and initialize the length to the value desired. *
2460 * While the transfer is in progress, hardware will decrement the *
2461 * length field with each successful block that is copied. Once the *
2462 * transfer completes, hardware will clear the Busy bit. The length *
2463 * field will also contain the number of cache lines left to be *
2464 * transferred. *
2465 * *
2466 ************************************************************************/
2467
2468typedef union ii_ibls0_u {
2469 u64 ii_ibls0_regval;
2470 struct {
2471 u64 i_length:16;
2472 u64 i_error:1;
2473 u64 i_rsvd_1:3;
2474 u64 i_busy:1;
2475 u64 i_rsvd:43;
2476 } ii_ibls0_fld_s;
2477} ii_ibls0_u_t;
2478
2479/************************************************************************
2480 * *
2481 * This register should be loaded before a transfer is started. The *
2482 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2483 * address as described in Section 1.3, Figure2 and Figure3. Since *
2484 * the bottom 7 bits of the address are always taken to be zero, BTE *
2485 * transfers are always cacheline-aligned. *
2486 * *
2487 ************************************************************************/
2488
2489typedef union ii_ibsa0_u {
2490 u64 ii_ibsa0_regval;
2491 struct {
2492 u64 i_rsvd_1:7;
2493 u64 i_addr:42;
2494 u64 i_rsvd:15;
2495 } ii_ibsa0_fld_s;
2496} ii_ibsa0_u_t;
2497
2498/************************************************************************
2499 * *
2500 * This register should be loaded before a transfer is started. The *
2501 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2502 * address as described in Section 1.3, Figure2 and Figure3. Since *
2503 * the bottom 7 bits of the address are always taken to be zero, BTE *
2504 * transfers are always cacheline-aligned. *
2505 * *
2506 ************************************************************************/
2507
2508typedef union ii_ibda0_u {
2509 u64 ii_ibda0_regval;
2510 struct {
2511 u64 i_rsvd_1:7;
2512 u64 i_addr:42;
2513 u64 i_rsvd:15;
2514 } ii_ibda0_fld_s;
2515} ii_ibda0_u_t;
2516
2517/************************************************************************
2518 * *
2519 * Writing to this register sets up the attributes of the transfer *
2520 * and initiates the transfer operation. Reading this register has *
2521 * the side effect of terminating any transfer in progress. Note: *
2522 * stopping a transfer midstream could have an adverse impact on the *
2523 * other BTE. If a BTE stream has to be stopped (due to error *
2524 * handling for example), both BTE streams should be stopped and *
2525 * their transfers discarded. *
2526 * *
2527 ************************************************************************/
2528
2529typedef union ii_ibct0_u {
2530 u64 ii_ibct0_regval;
2531 struct {
2532 u64 i_zerofill:1;
2533 u64 i_rsvd_2:3;
2534 u64 i_notify:1;
2535 u64 i_rsvd_1:3;
2536 u64 i_poison:1;
2537 u64 i_rsvd:55;
2538 } ii_ibct0_fld_s;
2539} ii_ibct0_u_t;
2540
2541/************************************************************************
2542 * *
2543 * This register contains the address to which the WINV is sent. *
2544 * This address has to be cache line aligned. *
2545 * *
2546 ************************************************************************/
2547
2548typedef union ii_ibna0_u {
2549 u64 ii_ibna0_regval;
2550 struct {
2551 u64 i_rsvd_1:7;
2552 u64 i_addr:42;
2553 u64 i_rsvd:15;
2554 } ii_ibna0_fld_s;
2555} ii_ibna0_u_t;
2556
2557/************************************************************************
2558 * *
2559 * This register contains the programmable level as well as the node *
2560 * ID and PI unit of the processor to which the interrupt will be *
2561 * sent. *
2562 * *
2563 ************************************************************************/
2564
2565typedef union ii_ibia0_u {
2566 u64 ii_ibia0_regval;
2567 struct {
2568 u64 i_rsvd_2:1;
2569 u64 i_node_id:11;
2570 u64 i_rsvd_1:4;
2571 u64 i_level:7;
2572 u64 i_rsvd:41;
2573 } ii_ibia0_fld_s;
2574} ii_ibia0_u_t;
2575
2576/************************************************************************
2577 * *
2578 * Description: This register is used to set up the length for a *
2579 * transfer and then to monitor the progress of that transfer. This *
2580 * register needs to be initialized before a transfer is started. A *
2581 * legitimate write to this register will set the Busy bit, clear the *
2582 * Error bit, and initialize the length to the value desired. *
2583 * While the transfer is in progress, hardware will decrement the *
2584 * length field with each successful block that is copied. Once the *
2585 * transfer completes, hardware will clear the Busy bit. The length *
2586 * field will also contain the number of cache lines left to be *
2587 * transferred. *
2588 * *
2589 ************************************************************************/
2590
2591typedef union ii_ibls1_u {
2592 u64 ii_ibls1_regval;
2593 struct {
2594 u64 i_length:16;
2595 u64 i_error:1;
2596 u64 i_rsvd_1:3;
2597 u64 i_busy:1;
2598 u64 i_rsvd:43;
2599 } ii_ibls1_fld_s;
2600} ii_ibls1_u_t;
2601
2602/************************************************************************
2603 * *
2604 * This register should be loaded before a transfer is started. The *
2605 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2606 * address as described in Section 1.3, Figure2 and Figure3. Since *
2607 * the bottom 7 bits of the address are always taken to be zero, BTE *
2608 * transfers are always cacheline-aligned. *
2609 * *
2610 ************************************************************************/
2611
2612typedef union ii_ibsa1_u {
2613 u64 ii_ibsa1_regval;
2614 struct {
2615 u64 i_rsvd_1:7;
2616 u64 i_addr:33;
2617 u64 i_rsvd:24;
2618 } ii_ibsa1_fld_s;
2619} ii_ibsa1_u_t;
2620
2621/************************************************************************
2622 * *
2623 * This register should be loaded before a transfer is started. The *
2624 * address to be loaded in bits 39:0 is the 40-bit TRex+ physical *
2625 * address as described in Section 1.3, Figure2 and Figure3. Since *
2626 * the bottom 7 bits of the address are always taken to be zero, BTE *
2627 * transfers are always cacheline-aligned. *
2628 * *
2629 ************************************************************************/
2630
2631typedef union ii_ibda1_u {
2632 u64 ii_ibda1_regval;
2633 struct {
2634 u64 i_rsvd_1:7;
2635 u64 i_addr:33;
2636 u64 i_rsvd:24;
2637 } ii_ibda1_fld_s;
2638} ii_ibda1_u_t;
2639
2640/************************************************************************
2641 * *
2642 * Writing to this register sets up the attributes of the transfer *
2643 * and initiates the transfer operation. Reading this register has *
2644 * the side effect of terminating any transfer in progress. Note: *
2645 * stopping a transfer midstream could have an adverse impact on the *
2646 * other BTE. If a BTE stream has to be stopped (due to error *
2647 * handling for example), both BTE streams should be stopped and *
2648 * their transfers discarded. *
2649 * *
2650 ************************************************************************/
2651
2652typedef union ii_ibct1_u {
2653 u64 ii_ibct1_regval;
2654 struct {
2655 u64 i_zerofill:1;
2656 u64 i_rsvd_2:3;
2657 u64 i_notify:1;
2658 u64 i_rsvd_1:3;
2659 u64 i_poison:1;
2660 u64 i_rsvd:55;
2661 } ii_ibct1_fld_s;
2662} ii_ibct1_u_t;
2663
2664/************************************************************************
2665 * *
2666 * This register contains the address to which the WINV is sent. *
2667 * This address has to be cache line aligned. *
2668 * *
2669 ************************************************************************/
2670
2671typedef union ii_ibna1_u {
2672 u64 ii_ibna1_regval;
2673 struct {
2674 u64 i_rsvd_1:7;
2675 u64 i_addr:33;
2676 u64 i_rsvd:24;
2677 } ii_ibna1_fld_s;
2678} ii_ibna1_u_t;
2679
2680/************************************************************************
2681 * *
2682 * This register contains the programmable level as well as the node *
2683 * ID and PI unit of the processor to which the interrupt will be *
2684 * sent. *
2685 * *
2686 ************************************************************************/
2687
2688typedef union ii_ibia1_u {
2689 u64 ii_ibia1_regval;
2690 struct {
2691 u64 i_pi_id:1;
2692 u64 i_node_id:8;
2693 u64 i_rsvd_1:7;
2694 u64 i_level:7;
2695 u64 i_rsvd:41;
2696 } ii_ibia1_fld_s;
2697} ii_ibia1_u_t;
2698
2699/************************************************************************
2700 * *
2701 * This register defines the resources that feed information into *
2702 * the two performance counters located in the IO Performance *
2703 * Profiling Register. There are 17 different quantities that can be *
2704 * measured. Given these 17 different options, the two performance *
2705 * counters have 15 of them in common; menu selections 0 through 0xE *
2706 * are identical for each performance counter. As for the other two *
2707 * options, one is available from one performance counter and the *
2708 * other is available from the other performance counter. Hence, the *
2709 * II supports all 17*16=272 possible combinations of quantities to *
2710 * measure. *
2711 * *
2712 ************************************************************************/
2713
2714typedef union ii_ipcr_u {
2715 u64 ii_ipcr_regval;
2716 struct {
2717 u64 i_ippr0_c:4;
2718 u64 i_ippr1_c:4;
2719 u64 i_icct:8;
2720 u64 i_rsvd:48;
2721 } ii_ipcr_fld_s;
2722} ii_ipcr_u_t;
2723
2724/************************************************************************
2725 * *
2726 * *
2727 * *
2728 ************************************************************************/
2729
2730typedef union ii_ippr_u {
2731 u64 ii_ippr_regval;
2732 struct {
2733 u64 i_ippr0:32;
2734 u64 i_ippr1:32;
2735 } ii_ippr_fld_s;
2736} ii_ippr_u_t;
2737
2738/************************************************************************
2739 * *
2740 * The following defines which were not formed into structures are *
2741 * probably indentical to another register, and the name of the *
2742 * register is provided against each of these registers. This *
2743 * information needs to be checked carefully *
2744 * *
2745 * IIO_ICRB1_A IIO_ICRB0_A *
2746 * IIO_ICRB1_B IIO_ICRB0_B *
2747 * IIO_ICRB1_C IIO_ICRB0_C *
2748 * IIO_ICRB1_D IIO_ICRB0_D *
2749 * IIO_ICRB1_E IIO_ICRB0_E *
2750 * IIO_ICRB2_A IIO_ICRB0_A *
2751 * IIO_ICRB2_B IIO_ICRB0_B *
2752 * IIO_ICRB2_C IIO_ICRB0_C *
2753 * IIO_ICRB2_D IIO_ICRB0_D *
2754 * IIO_ICRB2_E IIO_ICRB0_E *
2755 * IIO_ICRB3_A IIO_ICRB0_A *
2756 * IIO_ICRB3_B IIO_ICRB0_B *
2757 * IIO_ICRB3_C IIO_ICRB0_C *
2758 * IIO_ICRB3_D IIO_ICRB0_D *
2759 * IIO_ICRB3_E IIO_ICRB0_E *
2760 * IIO_ICRB4_A IIO_ICRB0_A *
2761 * IIO_ICRB4_B IIO_ICRB0_B *
2762 * IIO_ICRB4_C IIO_ICRB0_C *
2763 * IIO_ICRB4_D IIO_ICRB0_D *
2764 * IIO_ICRB4_E IIO_ICRB0_E *
2765 * IIO_ICRB5_A IIO_ICRB0_A *
2766 * IIO_ICRB5_B IIO_ICRB0_B *
2767 * IIO_ICRB5_C IIO_ICRB0_C *
2768 * IIO_ICRB5_D IIO_ICRB0_D *
2769 * IIO_ICRB5_E IIO_ICRB0_E *
2770 * IIO_ICRB6_A IIO_ICRB0_A *
2771 * IIO_ICRB6_B IIO_ICRB0_B *
2772 * IIO_ICRB6_C IIO_ICRB0_C *
2773 * IIO_ICRB6_D IIO_ICRB0_D *
2774 * IIO_ICRB6_E IIO_ICRB0_E *
2775 * IIO_ICRB7_A IIO_ICRB0_A *
2776 * IIO_ICRB7_B IIO_ICRB0_B *
2777 * IIO_ICRB7_C IIO_ICRB0_C *
2778 * IIO_ICRB7_D IIO_ICRB0_D *
2779 * IIO_ICRB7_E IIO_ICRB0_E *
2780 * IIO_ICRB8_A IIO_ICRB0_A *
2781 * IIO_ICRB8_B IIO_ICRB0_B *
2782 * IIO_ICRB8_C IIO_ICRB0_C *
2783 * IIO_ICRB8_D IIO_ICRB0_D *
2784 * IIO_ICRB8_E IIO_ICRB0_E *
2785 * IIO_ICRB9_A IIO_ICRB0_A *
2786 * IIO_ICRB9_B IIO_ICRB0_B *
2787 * IIO_ICRB9_C IIO_ICRB0_C *
2788 * IIO_ICRB9_D IIO_ICRB0_D *
2789 * IIO_ICRB9_E IIO_ICRB0_E *
2790 * IIO_ICRBA_A IIO_ICRB0_A *
2791 * IIO_ICRBA_B IIO_ICRB0_B *
2792 * IIO_ICRBA_C IIO_ICRB0_C *
2793 * IIO_ICRBA_D IIO_ICRB0_D *
2794 * IIO_ICRBA_E IIO_ICRB0_E *
2795 * IIO_ICRBB_A IIO_ICRB0_A *
2796 * IIO_ICRBB_B IIO_ICRB0_B *
2797 * IIO_ICRBB_C IIO_ICRB0_C *
2798 * IIO_ICRBB_D IIO_ICRB0_D *
2799 * IIO_ICRBB_E IIO_ICRB0_E *
2800 * IIO_ICRBC_A IIO_ICRB0_A *
2801 * IIO_ICRBC_B IIO_ICRB0_B *
2802 * IIO_ICRBC_C IIO_ICRB0_C *
2803 * IIO_ICRBC_D IIO_ICRB0_D *
2804 * IIO_ICRBC_E IIO_ICRB0_E *
2805 * IIO_ICRBD_A IIO_ICRB0_A *
2806 * IIO_ICRBD_B IIO_ICRB0_B *
2807 * IIO_ICRBD_C IIO_ICRB0_C *
2808 * IIO_ICRBD_D IIO_ICRB0_D *
2809 * IIO_ICRBD_E IIO_ICRB0_E *
2810 * IIO_ICRBE_A IIO_ICRB0_A *
2811 * IIO_ICRBE_B IIO_ICRB0_B *
2812 * IIO_ICRBE_C IIO_ICRB0_C *
2813 * IIO_ICRBE_D IIO_ICRB0_D *
2814 * IIO_ICRBE_E IIO_ICRB0_E *
2815 * *
2816 ************************************************************************/
2817
2818/*
2819 * Slightly friendlier names for some common registers.
2820 */
2821#define IIO_WIDGET IIO_WID /* Widget identification */
2822#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
2823#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
2824#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
2825#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
2826#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
2827#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
2828#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
2829#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
2830#define IIO_LLP_LOG IIO_ILLR /* LLP log */
2831#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout */
2832#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
2833#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
2834#define IIO_IGFX_0 IIO_IGFX0
2835#define IIO_IGFX_1 IIO_IGFX1
2836#define IIO_IBCT_0 IIO_IBCT0
2837#define IIO_IBCT_1 IIO_IBCT1
2838#define IIO_IBLS_0 IIO_IBLS0
2839#define IIO_IBLS_1 IIO_IBLS1
2840#define IIO_IBSA_0 IIO_IBSA0
2841#define IIO_IBSA_1 IIO_IBSA1
2842#define IIO_IBDA_0 IIO_IBDA0
2843#define IIO_IBDA_1 IIO_IBDA1
2844#define IIO_IBNA_0 IIO_IBNA0
2845#define IIO_IBNA_1 IIO_IBNA1
2846#define IIO_IBIA_0 IIO_IBIA0
2847#define IIO_IBIA_1 IIO_IBIA1
2848#define IIO_IOPRB_0 IIO_IPRB0
2849
2850#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x)))
2851#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x)))
2852#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */
2853#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
2854#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
2855
2856#define IIO_NUM_IPRBS 9
2857
2858#define IIO_LLP_CSR_IS_UP 0x00002000
2859#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
2860#define IIO_LLP_CSR_LLP_STAT_SHFT 12
2861
2862#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */
2863#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */
2864
2865/* key to IIO_PROTECT_OVRRD */
2866#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
2867
2868/* BTE register names */
2869#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
2870#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
2871#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
2872#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
2873#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
2874#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
2875#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
2876#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
2877
2878/* BTE register offsets from base */
2879#define BTEOFF_STAT 0
2880#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
2881#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
2882#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
2883#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
2884#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
2885
2886/* names used in shub diags */
2887#define IIO_BASE_BTE0 IIO_IBLS_0
2888#define IIO_BASE_BTE1 IIO_IBLS_1
2889
2890/*
2891 * Macro which takes the widget number, and returns the
2892 * IO PRB address of that widget.
2893 * value _x is expected to be a widget number in the range
2894 * 0, 8 - 0xF
2895 */
2896#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
2897 (_x) : \
2898 (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
2899
2900/* GFX Flow Control Node/Widget Register */
2901#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
2902#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
2903#define IIO_IGFX_W_NUM_SHIFT 0
2904#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */
2905#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1)
2906#define IIO_IGFX_PI_NUM_SHIFT 4
2907#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */
2908#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
2909#define IIO_IGFX_N_NUM_SHIFT 5
2910#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
2911#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
2912#define IIO_IGFX_P_NUM_SHIFT 16
2913#define IIO_IGFX_INIT(widget, pi, node, cpu) (\
2914 (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
2915 (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \
2916 (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
2917 (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
2918
2919/* Scratch registers (all bits available) */
2920#define IIO_SCRATCH_REG0 IIO_ISCR0
2921#define IIO_SCRATCH_REG1 IIO_ISCR1
2922#define IIO_SCRATCH_MASK 0xffffffffffffffffUL
2923
2924#define IIO_SCRATCH_BIT0_0 0x0000000000000001UL
2925#define IIO_SCRATCH_BIT0_1 0x0000000000000002UL
2926#define IIO_SCRATCH_BIT0_2 0x0000000000000004UL
2927#define IIO_SCRATCH_BIT0_3 0x0000000000000008UL
2928#define IIO_SCRATCH_BIT0_4 0x0000000000000010UL
2929#define IIO_SCRATCH_BIT0_5 0x0000000000000020UL
2930#define IIO_SCRATCH_BIT0_6 0x0000000000000040UL
2931#define IIO_SCRATCH_BIT0_7 0x0000000000000080UL
2932#define IIO_SCRATCH_BIT0_8 0x0000000000000100UL
2933#define IIO_SCRATCH_BIT0_9 0x0000000000000200UL
2934#define IIO_SCRATCH_BIT0_A 0x0000000000000400UL
2935
2936#define IIO_SCRATCH_BIT1_0 0x0000000000000001UL
2937#define IIO_SCRATCH_BIT1_1 0x0000000000000002UL
2938/* IO Translation Table Entries */
2939#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
2940 /* Hw manuals number them 1..7! */
2941/*
2942 * IIO_IMEM Register fields.
2943 */
2944#define IIO_IMEM_W0ESD 0x1UL /* Widget 0 shut down due to error */
2945#define IIO_IMEM_B0ESD (1UL << 4) /* BTE 0 shut down due to error */
2946#define IIO_IMEM_B1ESD (1UL << 8) /* BTE 1 Shut down due to error */
2947
2948/*
2949 * As a permanent workaround for a bug in the PI side of the shub, we've
2950 * redefined big window 7 as small window 0.
2951 XXX does this still apply for SN1??
2952 */
2953#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
2954
2955/*
2956 * Use the top big window as a surrogate for the first small window
2957 */
2958#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
2959
2960#define ILCSR_WARM_RESET 0x100
2961
2962/*
2963 * CRB manipulation macros
2964 * The CRB macros are slightly complicated, since there are up to
2965 * four registers associated with each CRB entry.
2966 */
2967#define IIO_NUM_CRBS 15 /* Number of CRBs */
2968#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */
2969#define IIO_ICRB_OFFSET 8
2970#define IIO_ICRB_0 IIO_ICRB0_A
2971#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
2972/* XXX - This is now tuneable:
2973 #define IIO_FIRST_PC_ENTRY 12
2974 */
2975
2976#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))))
2977#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET))
2978#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET))
2979#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET))
2980#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET))
2981
2982#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7)
2983
2984/*
2985 * values for "ecode" field
2986 */
2987#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */
2988#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */
2989#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access
2990 * e.g. WINV to a Read only line. */
2991#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */
2992#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */
2993#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */
2994#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */
2995#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */
2996
2997/*
2998 * Values for field imsgtype
2999 */
3000#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
3001#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
3002#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */
3003#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
3004
3005/*
3006 * values for field initiator.
3007 */
3008#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */
3009#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */
3010#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */
3011#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */
3012#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */
3013
3014/*
3015 * Number of credits Hub widget has while sending req/response to
3016 * xbow.
3017 * Value of 3 is required by Xbow 1.1
3018 * We may be able to increase this to 4 with Xbow 1.2.
3019 */
3020#define HUBII_XBOW_CREDIT 3
3021#define HUBII_XBOW_REV2_CREDIT 4
3022
3023/*
3024 * Number of credits that xtalk devices should use when communicating
3025 * with a SHub (depth of SHub's queue).
3026 */
3027#define HUB_CREDIT 4
3028
3029/*
3030 * Some IIO_PRB fields
3031 */
3032#define IIO_PRB_MULTI_ERR (1LL << 63)
3033#define IIO_PRB_SPUR_RD (1LL << 51)
3034#define IIO_PRB_SPUR_WR (1LL << 50)
3035#define IIO_PRB_RD_TO (1LL << 49)
3036#define IIO_PRB_ERROR (1LL << 48)
3037
3038/*************************************************************************
3039
3040 Some of the IIO field masks and shifts are defined here.
3041 This is in order to maintain compatibility in SN0 and SN1 code
3042
3043**************************************************************************/
3044
3045/*
3046 * ICMR register fields
3047 * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
3048 * present in SHub)
3049 */
3050
3051#define IIO_ICMR_CRB_VLD_SHFT 20
3052#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
3053
3054#define IIO_ICMR_FC_CNT_SHFT 16
3055#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT)
3056
3057#define IIO_ICMR_C_CNT_SHFT 4
3058#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT)
3059
3060#define IIO_ICMR_PRECISE (1UL << 52)
3061#define IIO_ICMR_CLR_RPPD (1UL << 13)
3062#define IIO_ICMR_CLR_RQPD (1UL << 12)
3063
3064/*
3065 * IIO PIO Deallocation register field masks : (IIO_IPDR)
3066 XXX present but not needed in bedrock? See the manual.
3067 */
3068#define IIO_IPDR_PND (1 << 4)
3069
3070/*
3071 * IIO CRB deallocation register field masks: (IIO_ICDR)
3072 */
3073#define IIO_ICDR_PND (1 << 4)
3074
3075/*
3076 * IO BTE Length/Status (IIO_IBLS) register bit field definitions
3077 */
3078#define IBLS_BUSY (0x1UL << 20)
3079#define IBLS_ERROR_SHFT 16
3080#define IBLS_ERROR (0x1UL << IBLS_ERROR_SHFT)
3081#define IBLS_LENGTH_MASK 0xffff
3082
3083/*
3084 * IO BTE Control/Terminate register (IBCT) register bit field definitions
3085 */
3086#define IBCT_POISON (0x1UL << 8)
3087#define IBCT_NOTIFY (0x1UL << 4)
3088#define IBCT_ZFIL_MODE (0x1UL << 0)
3089
3090/*
3091 * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
3092 */
3093#define IIEPH1_VALID (1UL << 44)
3094#define IIEPH1_OVERRUN (1UL << 40)
3095#define IIEPH1_ERR_TYPE_SHFT 32
3096#define IIEPH1_ERR_TYPE_MASK 0xf
3097#define IIEPH1_SOURCE_SHFT 20
3098#define IIEPH1_SOURCE_MASK 11
3099#define IIEPH1_SUPPL_SHFT 8
3100#define IIEPH1_SUPPL_MASK 11
3101#define IIEPH1_CMD_SHFT 0
3102#define IIEPH1_CMD_MASK 7
3103
3104#define IIEPH2_TAIL (1UL << 40)
3105#define IIEPH2_ADDRESS_SHFT 0
3106#define IIEPH2_ADDRESS_MASK 38
3107
3108#define IIEPH1_ERR_SHORT_REQ 2
3109#define IIEPH1_ERR_SHORT_REPLY 3
3110#define IIEPH1_ERR_LONG_REQ 4
3111#define IIEPH1_ERR_LONG_REPLY 5
3112
3113/*
3114 * IO Error Clear register bit field definitions
3115 */
3116#define IECLR_PI1_FWD_INT (1UL << 31) /* clear PI1_FORWARD_INT in iidsr */
3117#define IECLR_PI0_FWD_INT (1UL << 30) /* clear PI0_FORWARD_INT in iidsr */
3118#define IECLR_SPUR_RD_HDR (1UL << 29) /* clear valid bit in ixss reg */
3119#define IECLR_BTE1 (1UL << 18) /* clear bte error 1 */
3120#define IECLR_BTE0 (1UL << 17) /* clear bte error 0 */
3121#define IECLR_CRAZY (1UL << 16) /* clear crazy bit in wstat reg */
3122#define IECLR_PRB_F (1UL << 15) /* clear err bit in PRB_F reg */
3123#define IECLR_PRB_E (1UL << 14) /* clear err bit in PRB_E reg */
3124#define IECLR_PRB_D (1UL << 13) /* clear err bit in PRB_D reg */
3125#define IECLR_PRB_C (1UL << 12) /* clear err bit in PRB_C reg */
3126#define IECLR_PRB_B (1UL << 11) /* clear err bit in PRB_B reg */
3127#define IECLR_PRB_A (1UL << 10) /* clear err bit in PRB_A reg */
3128#define IECLR_PRB_9 (1UL << 9) /* clear err bit in PRB_9 reg */
3129#define IECLR_PRB_8 (1UL << 8) /* clear err bit in PRB_8 reg */
3130#define IECLR_PRB_0 (1UL << 0) /* clear err bit in PRB_0 reg */
3131
3132/*
3133 * IIO CRB control register Fields: IIO_ICCR
3134 */
3135#define IIO_ICCR_PENDING 0x10000
3136#define IIO_ICCR_CMD_MASK 0xFF
3137#define IIO_ICCR_CMD_SHFT 7
3138#define IIO_ICCR_CMD_NOP 0x0 /* No Op */
3139#define IIO_ICCR_CMD_WAKE 0x100 /* Reactivate CRB entry and process */
3140#define IIO_ICCR_CMD_TIMEOUT 0x200 /* Make CRB timeout & mark invalid */
3141#define IIO_ICCR_CMD_EJECT 0x400 /* Contents of entry written to memory
3142 * via a WB
3143 */
3144#define IIO_ICCR_CMD_FLUSH 0x800
3145
3146/*
3147 *
3148 * CRB Register description.
3149 *
3150 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3151 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3152 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3153 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3154 * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
3155 *
3156 * Many of the fields in CRB are status bits used by hardware
3157 * for implementation of the protocol. It's very dangerous to
3158 * mess around with the CRB registers.
3159 *
3160 * It's OK to read the CRB registers and try to make sense out of the
3161 * fields in CRB.
3162 *
3163 * Updating CRB requires all activities in Hub IIO to be quiesced.
3164 * otherwise, a write to CRB could corrupt other CRB entries.
3165 * CRBs are here only as a back door peek to shub IIO's status.
3166 * Quiescing implies no dmas no PIOs
3167 * either directly from the cpu or from sn0net.
3168 * this is not something that can be done easily. So, AVOID updating
3169 * CRBs.
3170 */
3171
3172/*
3173 * Easy access macros for CRBs, all 5 registers (A-E)
3174 */
3175typedef ii_icrb0_a_u_t icrba_t;
3176#define a_sidn ii_icrb0_a_fld_s.ia_sidn
3177#define a_tnum ii_icrb0_a_fld_s.ia_tnum
3178#define a_addr ii_icrb0_a_fld_s.ia_addr
3179#define a_valid ii_icrb0_a_fld_s.ia_vld
3180#define a_iow ii_icrb0_a_fld_s.ia_iow
3181#define a_regvalue ii_icrb0_a_regval
3182
3183typedef ii_icrb0_b_u_t icrbb_t;
3184#define b_use_old ii_icrb0_b_fld_s.ib_use_old
3185#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype
3186#define b_imsg ii_icrb0_b_fld_s.ib_imsg
3187#define b_initiator ii_icrb0_b_fld_s.ib_init
3188#define b_exc ii_icrb0_b_fld_s.ib_exc
3189#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt
3190#define b_resp ii_icrb0_b_fld_s.ib_resp
3191#define b_ack ii_icrb0_b_fld_s.ib_ack
3192#define b_hold ii_icrb0_b_fld_s.ib_hold
3193#define b_wb ii_icrb0_b_fld_s.ib_wb
3194#define b_intvn ii_icrb0_b_fld_s.ib_intvn
3195#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib
3196#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr
3197#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0
3198#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1
3199#define b_error ii_icrb0_b_fld_s.ib_error
3200#define b_ecode ii_icrb0_b_fld_s.ib_errcode
3201#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce
3202#define b_mark ii_icrb0_b_fld_s.ib_mark
3203#define b_xerr ii_icrb0_b_fld_s.ib_xt_err
3204#define b_regvalue ii_icrb0_b_regval
3205
3206typedef ii_icrb0_c_u_t icrbc_t;
3207#define c_suppl ii_icrb0_c_fld_s.ic_suppl
3208#define c_barrop ii_icrb0_c_fld_s.ic_bo
3209#define c_doresp ii_icrb0_c_fld_s.ic_resprqd
3210#define c_gbr ii_icrb0_c_fld_s.ic_gbr
3211#define c_btenum ii_icrb0_c_fld_s.ic_bte_num
3212#define c_cohtrans ii_icrb0_c_fld_s.ic_ct
3213#define c_xtsize ii_icrb0_c_fld_s.ic_size
3214#define c_source ii_icrb0_c_fld_s.ic_source
3215#define c_regvalue ii_icrb0_c_regval
3216
3217typedef ii_icrb0_d_u_t icrbd_t;
3218#define d_sleep ii_icrb0_d_fld_s.id_sleep
3219#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt
3220#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc
3221#define d_bteop ii_icrb0_d_fld_s.id_bte_op
3222#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3223#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names */
3224#define d_regvalue ii_icrb0_d_regval
3225
3226typedef ii_icrb0_e_u_t icrbe_t;
3227#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld
3228#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld
3229#define icrbe_context ii_icrb0_e_fld_s.ie_context
3230#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout
3231#define e_regvalue ii_icrb0_e_regval
3232
3233/* Number of widgets supported by shub */
3234#define HUB_NUM_WIDGET 9
3235#define HUB_WIDGET_ID_MIN 0x8
3236#define HUB_WIDGET_ID_MAX 0xf
3237
3238#define HUB_WIDGET_PART_NUM 0xc120
3239#define MAX_HUBS_PER_XBOW 2
3240
3241/* A few more #defines for backwards compatibility */
3242#define iprb_t ii_iprb0_u_t
3243#define iprb_regval ii_iprb0_regval
3244#define iprb_mult_err ii_iprb0_fld_s.i_mult_err
3245#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd
3246#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr
3247#define iprb_rd_to ii_iprb0_fld_s.i_rd_to
3248#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt
3249#define iprb_error ii_iprb0_fld_s.i_error
3250#define iprb_ff ii_iprb0_fld_s.i_f
3251#define iprb_mode ii_iprb0_fld_s.i_m
3252#define iprb_bnakctr ii_iprb0_fld_s.i_nb
3253#define iprb_anakctr ii_iprb0_fld_s.i_na
3254#define iprb_xtalkctr ii_iprb0_fld_s.i_c
3255
3256#define LNK_STAT_WORKING 0x2 /* LLP is working */
3257
3258#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
3259#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
3260#define IIO_WSTAT_TXRETRY_MASK 0x7F /* should be 0xFF?? */
3261#define IIO_WSTAT_TXRETRY_SHFT 16
3262#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
3263 IIO_WSTAT_TXRETRY_MASK)
3264
3265/* Number of II perf. counters we can multiplex at once */
3266
3267#define IO_PERF_SETS 32
3268
3269/* Bit for the widget in inbound access register */
3270#define IIO_IIWA_WIDGET(_w) ((u64)(1ULL << _w))
3271/* Bit for the widget in outbound access register */
3272#define IIO_IOWA_WIDGET(_w) ((u64)(1ULL << _w))
3273
3274/* NOTE: The following define assumes that we are going to get
3275 * widget numbers from 8 thru F and the device numbers within
3276 * widget from 0 thru 7.
3277 */
3278#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((u64)(1ULL << (8 * ((w) - 8) + (d))))
3279
3280/* IO Interrupt Destination Register */
3281#define IIO_IIDSR_SENT_SHIFT 28
3282#define IIO_IIDSR_SENT_MASK 0x30000000
3283#define IIO_IIDSR_ENB_SHIFT 24
3284#define IIO_IIDSR_ENB_MASK 0x01000000
3285#define IIO_IIDSR_NODE_SHIFT 9
3286#define IIO_IIDSR_NODE_MASK 0x000ff700
3287#define IIO_IIDSR_PI_ID_SHIFT 8
3288#define IIO_IIDSR_PI_ID_MASK 0x00000100
3289#define IIO_IIDSR_LVL_SHIFT 0
3290#define IIO_IIDSR_LVL_MASK 0x000000ff
3291
3292/* Xtalk timeout threshhold register (IIO_IXTT) */
3293#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */
3294#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT)
3295#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */
3296#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
3297#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */
3298#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
3299
3300/*
3301 * The IO LLP control status register and widget control register
3302 */
3303
3304typedef union hubii_wcr_u {
3305 u64 wcr_reg_value;
3306 struct {
3307 u64 wcr_widget_id:4, /* LLP crossbar credit */
3308 wcr_tag_mode:1, /* Tag mode */
3309 wcr_rsvd1:8, /* Reserved */
3310 wcr_xbar_crd:3, /* LLP crossbar credit */
3311 wcr_f_bad_pkt:1, /* Force bad llp pkt enable */
3312 wcr_dir_con:1, /* widget direct connect */
3313 wcr_e_thresh:5, /* elasticity threshold */
3314 wcr_rsvd:41; /* unused */
3315 } wcr_fields_s;
3316} hubii_wcr_t;
3317
3318#define iwcr_dir_con wcr_fields_s.wcr_dir_con
3319
3320/* The structures below are defined to extract and modify the ii
3321performance registers */
3322
3323/* io_perf_sel allows the caller to specify what tests will be
3324 performed */
3325
3326typedef union io_perf_sel {
3327 u64 perf_sel_reg;
3328 struct {
3329 u64 perf_ippr0:4, perf_ippr1:4, perf_icct:8, perf_rsvd:48;
3330 } perf_sel_bits;
3331} io_perf_sel_t;
3332
3333/* io_perf_cnt is to extract the count from the shub registers. Due to
3334 hardware problems there is only one counter, not two. */
3335
3336typedef union io_perf_cnt {
3337 u64 perf_cnt;
3338 struct {
3339 u64 perf_cnt:20, perf_rsvd2:12, perf_rsvd1:32;
3340 } perf_cnt_bits;
3341
3342} io_perf_cnt_t;
3343
3344typedef union iprte_a {
3345 u64 entry;
3346 struct {
3347 u64 i_rsvd_1:3;
3348 u64 i_addr:38;
3349 u64 i_init:3;
3350 u64 i_source:8;
3351 u64 i_rsvd:2;
3352 u64 i_widget:4;
3353 u64 i_to_cnt:5;
3354 u64 i_vld:1;
3355 } iprte_fields;
3356} iprte_a_t;
3357
3358#endif /* _ASM_IA64_SN_SHUBIO_H */
diff --git a/arch/ia64/include/asm/sn/simulator.h b/arch/ia64/include/asm/sn/simulator.h
new file mode 100644
index 000000000000..c2611f6cfe33
--- /dev/null
+++ b/arch/ia64/include/asm/sn/simulator.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 * Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
6 */
7
8#ifndef _ASM_IA64_SN_SIMULATOR_H
9#define _ASM_IA64_SN_SIMULATOR_H
10
11#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_SGI_UV)
12#define SNMAGIC 0xaeeeeeee8badbeefL
13#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
14
15#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
16#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
17#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
18extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
19#else
20#define IS_MEDUSA() 0
21#define SIMULATOR_SLEEP()
22#define IS_RUNNING_ON_SIMULATOR() 0
23#endif
24
25#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff --git a/arch/ia64/include/asm/sn/sn2/sn_hwperf.h b/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
new file mode 100644
index 000000000000..e61ebac38cdd
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn2/sn_hwperf.h
@@ -0,0 +1,242 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
7 *
8 * Data types used by the SN_SAL_HWPERF_OP SAL call for monitoring
9 * SGI Altix node and router hardware
10 *
11 * Mark Goodwin <markgw@sgi.com> Mon Aug 30 12:23:46 EST 2004
12 */
13
14#ifndef SN_HWPERF_H
15#define SN_HWPERF_H
16
17/*
18 * object structure. SN_HWPERF_ENUM_OBJECTS and SN_HWPERF_GET_CPU_INFO
19 * return an array of these. Do not change this without also
20 * changing the corresponding SAL code.
21 */
22#define SN_HWPERF_MAXSTRING 128
23struct sn_hwperf_object_info {
24 u32 id;
25 union {
26 struct {
27 u64 this_part:1;
28 u64 is_shared:1;
29 } fields;
30 struct {
31 u64 flags;
32 u64 reserved;
33 } b;
34 } f;
35 char name[SN_HWPERF_MAXSTRING];
36 char location[SN_HWPERF_MAXSTRING];
37 u32 ports;
38};
39
40#define sn_hwp_this_part f.fields.this_part
41#define sn_hwp_is_shared f.fields.is_shared
42#define sn_hwp_flags f.b.flags
43
44/* macros for object classification */
45#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
46#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
47#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
48#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
49#define SN_HWPERF_IS_NL4ROUTER(x) ((x) && strstr((x)->name, "NL4Router"))
50#define SN_HWPERF_IS_OLDROUTER(x) ((x) && strstr((x)->name, "Router"))
51#define SN_HWPERF_IS_ROUTER(x) (SN_HWPERF_IS_NL3ROUTER(x) || \
52 SN_HWPERF_IS_NL4ROUTER(x) || \
53 SN_HWPERF_IS_OLDROUTER(x))
54#define SN_HWPERF_FOREIGN(x) ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
55#define SN_HWPERF_SAME_OBJTYPE(x,y) ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
56 (SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
57 (SN_HWPERF_IS_ROUTER(x) && SN_HWPERF_IS_ROUTER(y)))
58
59/* numa port structure, SN_HWPERF_ENUM_PORTS returns an array of these */
60struct sn_hwperf_port_info {
61 u32 port;
62 u32 conn_id;
63 u32 conn_port;
64};
65
66/* for HWPERF_{GET,SET}_MMRS */
67struct sn_hwperf_data {
68 u64 addr;
69 u64 data;
70};
71
72/* user ioctl() argument, see below */
73struct sn_hwperf_ioctl_args {
74 u64 arg; /* argument, usually an object id */
75 u64 sz; /* size of transfer */
76 void *ptr; /* pointer to source/target */
77 u32 v0; /* second return value */
78};
79
80/*
81 * For SN_HWPERF_{GET,SET}_MMRS and SN_HWPERF_OBJECT_DISTANCE,
82 * sn_hwperf_ioctl_args.arg can be used to specify a CPU on which
83 * to call SAL, and whether to use an interprocessor interrupt
84 * or task migration in order to do so. If the CPU specified is
85 * SN_HWPERF_ARG_ANY_CPU, then the current CPU will be used.
86 */
87#define SN_HWPERF_ARG_ANY_CPU 0x7fffffffUL
88#define SN_HWPERF_ARG_CPU_MASK 0x7fffffff00000000ULL
89#define SN_HWPERF_ARG_USE_IPI_MASK 0x8000000000000000ULL
90#define SN_HWPERF_ARG_OBJID_MASK 0x00000000ffffffffULL
91
92/*
93 * ioctl requests on the "sn_hwperf" misc device that call SAL.
94 */
95#define SN_HWPERF_OP_MEM_COPYIN 0x1000
96#define SN_HWPERF_OP_MEM_COPYOUT 0x2000
97#define SN_HWPERF_OP_MASK 0x0fff
98
99/*
100 * Determine mem requirement.
101 * arg don't care
102 * sz 8
103 * p pointer to u64 integer
104 */
105#define SN_HWPERF_GET_HEAPSIZE 1
106
107/*
108 * Install mem for SAL drvr
109 * arg don't care
110 * sz sizeof buffer pointed to by p
111 * p pointer to buffer for scratch area
112 */
113#define SN_HWPERF_INSTALL_HEAP 2
114
115/*
116 * Determine number of objects
117 * arg don't care
118 * sz 8
119 * p pointer to u64 integer
120 */
121#define SN_HWPERF_OBJECT_COUNT (10|SN_HWPERF_OP_MEM_COPYOUT)
122
123/*
124 * Determine object "distance", relative to a cpu. This operation can
125 * execute on a designated logical cpu number, using either an IPI or
126 * via task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
127 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
128 *
129 * arg bitmap of IPI flag, cpu number and object id
130 * sz 8
131 * p pointer to u64 integer
132 */
133#define SN_HWPERF_OBJECT_DISTANCE (11|SN_HWPERF_OP_MEM_COPYOUT)
134
135/*
136 * Enumerate objects. Special case if sz == 8, returns the required
137 * buffer size.
138 * arg don't care
139 * sz sizeof buffer pointed to by p
140 * p pointer to array of struct sn_hwperf_object_info
141 */
142#define SN_HWPERF_ENUM_OBJECTS (12|SN_HWPERF_OP_MEM_COPYOUT)
143
144/*
145 * Enumerate NumaLink ports for an object. Special case if sz == 8,
146 * returns the required buffer size.
147 * arg object id
148 * sz sizeof buffer pointed to by p
149 * p pointer to array of struct sn_hwperf_port_info
150 */
151#define SN_HWPERF_ENUM_PORTS (13|SN_HWPERF_OP_MEM_COPYOUT)
152
153/*
154 * SET/GET memory mapped registers. These operations can execute
155 * on a designated logical cpu number, using either an IPI or via
156 * task migration. If the cpu number is SN_HWPERF_ANY_CPU, then
157 * the current CPU is used. See the SN_HWPERF_ARG_* macros above.
158 *
159 * arg bitmap of ipi flag, cpu number and object id
160 * sz sizeof buffer pointed to by p
161 * p pointer to array of struct sn_hwperf_data
162 */
163#define SN_HWPERF_SET_MMRS (14|SN_HWPERF_OP_MEM_COPYIN)
164#define SN_HWPERF_GET_MMRS (15|SN_HWPERF_OP_MEM_COPYOUT| \
165 SN_HWPERF_OP_MEM_COPYIN)
166/*
167 * Lock a shared object
168 * arg object id
169 * sz don't care
170 * p don't care
171 */
172#define SN_HWPERF_ACQUIRE 16
173
174/*
175 * Unlock a shared object
176 * arg object id
177 * sz don't care
178 * p don't care
179 */
180#define SN_HWPERF_RELEASE 17
181
182/*
183 * Break a lock on a shared object
184 * arg object id
185 * sz don't care
186 * p don't care
187 */
188#define SN_HWPERF_FORCE_RELEASE 18
189
190/*
191 * ioctl requests on "sn_hwperf" that do not call SAL
192 */
193
194/*
195 * get cpu info as an array of hwperf_object_info_t.
196 * id is logical CPU number, name is description, location
197 * is geoid (e.g. 001c04#1c). Special case if sz == 8,
198 * returns the required buffer size.
199 *
200 * arg don't care
201 * sz sizeof buffer pointed to by p
202 * p pointer to array of struct sn_hwperf_object_info
203 */
204#define SN_HWPERF_GET_CPU_INFO (100|SN_HWPERF_OP_MEM_COPYOUT)
205
206/*
207 * Given an object id, return it's node number (aka cnode).
208 * arg object id
209 * sz 8
210 * p pointer to u64 integer
211 */
212#define SN_HWPERF_GET_OBJ_NODE (101|SN_HWPERF_OP_MEM_COPYOUT)
213
214/*
215 * Given a node number (cnode), return it's nasid.
216 * arg ordinal node number (aka cnodeid)
217 * sz 8
218 * p pointer to u64 integer
219 */
220#define SN_HWPERF_GET_NODE_NASID (102|SN_HWPERF_OP_MEM_COPYOUT)
221
222/*
223 * Given a node id, determine the id of the nearest node with CPUs
224 * and the id of the nearest node that has memory. The argument
225 * node would normally be a "headless" node, e.g. an "IO node".
226 * Return 0 on success.
227 */
228extern int sn_hwperf_get_nearest_node(cnodeid_t node,
229 cnodeid_t *near_mem, cnodeid_t *near_cpu);
230
231/* return codes */
232#define SN_HWPERF_OP_OK 0
233#define SN_HWPERF_OP_NOMEM 1
234#define SN_HWPERF_OP_NO_PERM 2
235#define SN_HWPERF_OP_IO_ERROR 3
236#define SN_HWPERF_OP_BUSY 4
237#define SN_HWPERF_OP_RECONFIGURE 253
238#define SN_HWPERF_OP_INVAL 254
239
240int sn_topology_open(struct inode *inode, struct file *file);
241int sn_topology_release(struct inode *inode, struct file *file);
242#endif /* SN_HWPERF_H */
diff --git a/arch/ia64/include/asm/sn/sn_cpuid.h b/arch/ia64/include/asm/sn/sn_cpuid.h
new file mode 100644
index 000000000000..a676dd9ace3e
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_cpuid.h
@@ -0,0 +1,132 @@
1/*
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
8 */
9
10
11#ifndef _ASM_IA64_SN_SN_CPUID_H
12#define _ASM_IA64_SN_SN_CPUID_H
13
14#include <linux/smp.h>
15#include <asm/sn/addrs.h>
16#include <asm/sn/pda.h>
17#include <asm/intrinsics.h>
18
19
20/*
21 * Functions for converting between cpuids, nodeids and NASIDs.
22 *
23 * These are for SGI platforms only.
24 *
25 */
26
27
28
29
30/*
31 * Definitions of terms (these definitions are for IA64 ONLY. Other architectures
32 * use cpuid/cpunum quite defferently):
33 *
34 * CPUID - a number in range of 0..NR_CPUS-1 that uniquely identifies
35 * the cpu. The value cpuid has no significance on IA64 other than
36 * the boot cpu is 0.
37 * smp_processor_id() returns the cpuid of the current cpu.
38 *
39 * CPU_PHYSICAL_ID (also known as HARD_PROCESSOR_ID)
40 * This is the same as 31:24 of the processor LID register
41 * hard_smp_processor_id()- cpu_physical_id of current processor
42 * cpu_physical_id(cpuid) - convert a <cpuid> to a <physical_cpuid>
43 * cpu_logical_id(phy_id) - convert a <physical_cpuid> to a <cpuid>
44 * * not real efficient - don't use in perf critical code
45 *
46 * SLICE - a number in the range of 0 - 3 (typically) that represents the
47 * cpu number on a brick.
48 *
49 * SUBNODE - (almost obsolete) the number of the FSB that a cpu is
50 * connected to. This is also the same as the PI number. Usually 0 or 1.
51 *
52 * NOTE!!!: the value of the bits in the cpu physical id (SAPICid or LID) of a cpu has no
53 * significance. The SAPIC id (LID) is a 16-bit cookie that has meaning only to the PROM.
54 *
55 *
56 * The macros convert between cpu physical ids & slice/nasid/cnodeid.
57 * These terms are described below:
58 *
59 *
60 * Brick
61 * ----- ----- ----- ----- CPU
62 * | 0 | | 1 | | 0 | | 1 | SLICE
63 * ----- ----- ----- -----
64 * | | | |
65 * | | | |
66 * 0 | | 2 0 | | 2 FSB SLOT
67 * ------- -------
68 * | |
69 * | |
70 * | |
71 * ------------ -------------
72 * | | | |
73 * | SHUB | | SHUB | NASID (0..MAX_NASIDS)
74 * | |----- | | CNODEID (0..num_compact_nodes-1)
75 * | | | |
76 * | | | |
77 * ------------ -------------
78 * | |
79 *
80 *
81 */
82
83#define get_node_number(addr) NASID_GET(addr)
84
85/*
86 * NOTE: on non-MP systems, only cpuid 0 exists
87 */
88
89extern short physical_node_map[]; /* indexed by nasid to get cnode */
90
91/*
92 * Macros for retrieving info about current cpu
93 */
94#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
95#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
96#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
97#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
98#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
99
100/*
101 * Macros for retrieving info about an arbitrary cpu
102 * cpuid - logical cpu id
103 */
104#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid)
105#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode)
106#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
107
108
109/*
110 * Dont use the following in performance critical code. They require scans
111 * of potentially large tables.
112 */
113extern int nasid_slice_to_cpuid(int, int);
114
115/*
116 * cnodeid_to_nasid - convert a cnodeid to a NASID
117 */
118#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid])
119
120/*
121 * nasid_to_cnodeid - convert a NASID to a cnodeid
122 */
123#define nasid_to_cnodeid(nasid) (physical_node_map[nasid])
124
125/*
126 * partition_coherence_id - get the coherence ID of the current partition
127 */
128extern u8 sn_coherency_id;
129#define partition_coherence_id() (sn_coherency_id)
130
131#endif /* _ASM_IA64_SN_SN_CPUID_H */
132
diff --git a/arch/ia64/include/asm/sn/sn_feature_sets.h b/arch/ia64/include/asm/sn/sn_feature_sets.h
new file mode 100644
index 000000000000..8e83ac117ace
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_feature_sets.h
@@ -0,0 +1,58 @@
1#ifndef _ASM_IA64_SN_FEATURE_SETS_H
2#define _ASM_IA64_SN_FEATURE_SETS_H
3
4/*
5 * SN PROM Features
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2005-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15/* --------------------- PROM Features -----------------------------*/
16extern int sn_prom_feature_available(int id);
17
18#define MAX_PROM_FEATURE_SETS 2
19
20/*
21 * The following defines features that may or may not be supported by the
22 * current PROM. The OS uses sn_prom_feature_available(feature) to test for
23 * the presence of a PROM feature. Down rev (old) PROMs will always test
24 * "false" for new features.
25 *
26 * Use:
27 * if (sn_prom_feature_available(PRF_XXX))
28 * ...
29 */
30
31#define PRF_PAL_CACHE_FLUSH_SAFE 0
32#define PRF_DEVICE_FLUSH_LIST 1
33#define PRF_HOTPLUG_SUPPORT 2
34#define PRF_CPU_DISABLE_SUPPORT 3
35
36/* --------------------- OS Features -------------------------------*/
37
38/*
39 * The following defines OS features that are optionally present in
40 * the operating system.
41 * During boot, PROM is notified of these features via a series of calls:
42 *
43 * ia64_sn_set_os_feature(feature1);
44 *
45 * Once enabled, a feature cannot be disabled.
46 *
47 * By default, features are disabled unless explicitly enabled.
48 *
49 * These defines must be kept in sync with the corresponding
50 * PROM definitions in feature_sets.h.
51 */
52#define OSF_MCA_SLV_TO_OS_INIT_SLV 0
53#define OSF_FEAT_LOG_SBES 1
54#define OSF_ACPI_ENABLE 2
55#define OSF_PCISEGMENT_ENABLE 3
56
57
58#endif /* _ASM_IA64_SN_FEATURE_SETS_H */
diff --git a/arch/ia64/include/asm/sn/sn_sal.h b/arch/ia64/include/asm/sn/sn_sal.h
new file mode 100644
index 000000000000..57e649d388b8
--- /dev/null
+++ b/arch/ia64/include/asm/sn/sn_sal.h
@@ -0,0 +1,1188 @@
1#ifndef _ASM_IA64_SN_SN_SAL_H
2#define _ASM_IA64_SN_SN_SAL_H
3
4/*
5 * System Abstraction Layer definitions for IA64
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved.
12 */
13
14
15#include <asm/sal.h>
16#include <asm/sn/sn_cpuid.h>
17#include <asm/sn/arch.h>
18#include <asm/sn/geo.h>
19#include <asm/sn/nodepda.h>
20#include <asm/sn/shub_mmr.h>
21
22// SGI Specific Calls
23#define SN_SAL_POD_MODE 0x02000001
24#define SN_SAL_SYSTEM_RESET 0x02000002
25#define SN_SAL_PROBE 0x02000003
26#define SN_SAL_GET_MASTER_NASID 0x02000004
27#define SN_SAL_GET_KLCONFIG_ADDR 0x02000005
28#define SN_SAL_LOG_CE 0x02000006
29#define SN_SAL_REGISTER_CE 0x02000007
30#define SN_SAL_GET_PARTITION_ADDR 0x02000009
31#define SN_SAL_XP_ADDR_REGION 0x0200000f
32#define SN_SAL_NO_FAULT_ZONE_VIRTUAL 0x02000010
33#define SN_SAL_NO_FAULT_ZONE_PHYSICAL 0x02000011
34#define SN_SAL_PRINT_ERROR 0x02000012
35#define SN_SAL_REGISTER_PMI_HANDLER 0x02000014
36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
38#define SN_SAL_GET_SAPIC_INFO 0x0200001d
39#define SN_SAL_GET_SN_INFO 0x0200001e
40#define SN_SAL_CONSOLE_PUTC 0x02000021
41#define SN_SAL_CONSOLE_GETC 0x02000022
42#define SN_SAL_CONSOLE_PUTS 0x02000023
43#define SN_SAL_CONSOLE_GETS 0x02000024
44#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025
45#define SN_SAL_CONSOLE_POLL 0x02000026
46#define SN_SAL_CONSOLE_INTR 0x02000027
47#define SN_SAL_CONSOLE_PUTB 0x02000028
48#define SN_SAL_CONSOLE_XMIT_CHARS 0x0200002a
49#define SN_SAL_CONSOLE_READC 0x0200002b
50#define SN_SAL_SYSCTL_OP 0x02000030
51#define SN_SAL_SYSCTL_MODID_GET 0x02000031
52#define SN_SAL_SYSCTL_GET 0x02000032
53#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033
54#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035
55#define SN_SAL_SYSCTL_SLAB_GET 0x02000036
56#define SN_SAL_BUS_CONFIG 0x02000037
57#define SN_SAL_SYS_SERIAL_GET 0x02000038
58#define SN_SAL_PARTITION_SERIAL_GET 0x02000039
59#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a
60#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b
61#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c
62#define SN_SAL_COHERENCE 0x0200003d
63#define SN_SAL_MEMPROTECT 0x0200003e
64#define SN_SAL_SYSCTL_FRU_CAPTURE 0x0200003f
65
66#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
67#define SN_SAL_IROUTER_OP 0x02000043
68#define SN_SAL_SYSCTL_EVENT 0x02000044
69#define SN_SAL_IOIF_INTERRUPT 0x0200004a
70#define SN_SAL_HWPERF_OP 0x02000050 // lock
71#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
72#define SN_SAL_IOIF_PCI_SAFE 0x02000052
73#define SN_SAL_IOIF_SLOT_ENABLE 0x02000053
74#define SN_SAL_IOIF_SLOT_DISABLE 0x02000054
75#define SN_SAL_IOIF_GET_HUBDEV_INFO 0x02000055
76#define SN_SAL_IOIF_GET_PCIBUS_INFO 0x02000056
77#define SN_SAL_IOIF_GET_PCIDEV_INFO 0x02000057
78#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 // deprecated
79#define SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST 0x0200005a
80
81#define SN_SAL_IOIF_INIT 0x0200005f
82#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
83#define SN_SAL_BTE_RECOVER 0x02000061
84#define SN_SAL_RESERVED_DO_NOT_USE 0x02000062
85#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000064
86
87#define SN_SAL_GET_PROM_FEATURE_SET 0x02000065
88#define SN_SAL_SET_OS_FEATURE_SET 0x02000066
89#define SN_SAL_INJECT_ERROR 0x02000067
90#define SN_SAL_SET_CPU_NUMBER 0x02000068
91
92#define SN_SAL_KERNEL_LAUNCH_EVENT 0x02000069
93
94/*
95 * Service-specific constants
96 */
97
98/* Console interrupt manipulation */
99 /* action codes */
100#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */
101#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */
102#define SAL_CONSOLE_INTR_STATUS 2 /* retrieve the interrupt status */
103 /* interrupt specification & status return codes */
104#define SAL_CONSOLE_INTR_XMIT 1 /* output interrupt */
105#define SAL_CONSOLE_INTR_RECV 2 /* input interrupt */
106
107/* interrupt handling */
108#define SAL_INTR_ALLOC 1
109#define SAL_INTR_FREE 2
110#define SAL_INTR_REDIRECT 3
111
112/*
113 * operations available on the generic SN_SAL_SYSCTL_OP
114 * runtime service
115 */
116#define SAL_SYSCTL_OP_IOBOARD 0x0001 /* retrieve board type */
117#define SAL_SYSCTL_OP_TIO_JLCK_RST 0x0002 /* issue TIO clock reset */
118
119/*
120 * IRouter (i.e. generalized system controller) operations
121 */
122#define SAL_IROUTER_OPEN 0 /* open a subchannel */
123#define SAL_IROUTER_CLOSE 1 /* close a subchannel */
124#define SAL_IROUTER_SEND 2 /* send part of an IRouter packet */
125#define SAL_IROUTER_RECV 3 /* receive part of an IRouter packet */
126#define SAL_IROUTER_INTR_STATUS 4 /* check the interrupt status for
127 * an open subchannel
128 */
129#define SAL_IROUTER_INTR_ON 5 /* enable an interrupt */
130#define SAL_IROUTER_INTR_OFF 6 /* disable an interrupt */
131#define SAL_IROUTER_INIT 7 /* initialize IRouter driver */
132
133/* IRouter interrupt mask bits */
134#define SAL_IROUTER_INTR_XMIT SAL_CONSOLE_INTR_XMIT
135#define SAL_IROUTER_INTR_RECV SAL_CONSOLE_INTR_RECV
136
137/*
138 * Error Handling Features
139 */
140#define SAL_ERR_FEAT_MCA_SLV_TO_OS_INIT_SLV 0x1 // obsolete
141#define SAL_ERR_FEAT_LOG_SBES 0x2 // obsolete
142#define SAL_ERR_FEAT_MFR_OVERRIDE 0x4
143#define SAL_ERR_FEAT_SBE_THRESHOLD 0xffff0000
144
145/*
146 * SAL Error Codes
147 */
148#define SALRET_MORE_PASSES 1
149#define SALRET_OK 0
150#define SALRET_NOT_IMPLEMENTED (-1)
151#define SALRET_INVALID_ARG (-2)
152#define SALRET_ERROR (-3)
153
154#define SN_SAL_FAKE_PROM 0x02009999
155
156/**
157 * sn_sal_revision - get the SGI SAL revision number
158 *
159 * The SGI PROM stores its version in the sal_[ab]_rev_(major|minor).
160 * This routine simply extracts the major and minor values and
161 * presents them in a u32 format.
162 *
163 * For example, version 4.05 would be represented at 0x0405.
164 */
165static inline u32
166sn_sal_rev(void)
167{
168 struct ia64_sal_systab *systab = __va(efi.sal_systab);
169
170 return (u32)(systab->sal_b_rev_major << 8 | systab->sal_b_rev_minor);
171}
172
173/*
174 * Returns the master console nasid, if the call fails, return an illegal
175 * value.
176 */
177static inline u64
178ia64_sn_get_console_nasid(void)
179{
180 struct ia64_sal_retval ret_stuff;
181
182 ret_stuff.status = 0;
183 ret_stuff.v0 = 0;
184 ret_stuff.v1 = 0;
185 ret_stuff.v2 = 0;
186 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0);
187
188 if (ret_stuff.status < 0)
189 return ret_stuff.status;
190
191 /* Master console nasid is in 'v0' */
192 return ret_stuff.v0;
193}
194
195/*
196 * Returns the master baseio nasid, if the call fails, return an illegal
197 * value.
198 */
199static inline u64
200ia64_sn_get_master_baseio_nasid(void)
201{
202 struct ia64_sal_retval ret_stuff;
203
204 ret_stuff.status = 0;
205 ret_stuff.v0 = 0;
206 ret_stuff.v1 = 0;
207 ret_stuff.v2 = 0;
208 SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0);
209
210 if (ret_stuff.status < 0)
211 return ret_stuff.status;
212
213 /* Master baseio nasid is in 'v0' */
214 return ret_stuff.v0;
215}
216
217static inline void *
218ia64_sn_get_klconfig_addr(nasid_t nasid)
219{
220 struct ia64_sal_retval ret_stuff;
221
222 ret_stuff.status = 0;
223 ret_stuff.v0 = 0;
224 ret_stuff.v1 = 0;
225 ret_stuff.v2 = 0;
226 SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
227 return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL;
228}
229
230/*
231 * Returns the next console character.
232 */
233static inline u64
234ia64_sn_console_getc(int *ch)
235{
236 struct ia64_sal_retval ret_stuff;
237
238 ret_stuff.status = 0;
239 ret_stuff.v0 = 0;
240 ret_stuff.v1 = 0;
241 ret_stuff.v2 = 0;
242 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0);
243
244 /* character is in 'v0' */
245 *ch = (int)ret_stuff.v0;
246
247 return ret_stuff.status;
248}
249
250/*
251 * Read a character from the SAL console device, after a previous interrupt
252 * or poll operation has given us to know that a character is available
253 * to be read.
254 */
255static inline u64
256ia64_sn_console_readc(void)
257{
258 struct ia64_sal_retval ret_stuff;
259
260 ret_stuff.status = 0;
261 ret_stuff.v0 = 0;
262 ret_stuff.v1 = 0;
263 ret_stuff.v2 = 0;
264 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_READC, 0, 0, 0, 0, 0, 0, 0);
265
266 /* character is in 'v0' */
267 return ret_stuff.v0;
268}
269
270/*
271 * Sends the given character to the console.
272 */
273static inline u64
274ia64_sn_console_putc(char ch)
275{
276 struct ia64_sal_retval ret_stuff;
277
278 ret_stuff.status = 0;
279 ret_stuff.v0 = 0;
280 ret_stuff.v1 = 0;
281 ret_stuff.v2 = 0;
282 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTC, (u64)ch, 0, 0, 0, 0, 0, 0);
283
284 return ret_stuff.status;
285}
286
287/*
288 * Sends the given buffer to the console.
289 */
290static inline u64
291ia64_sn_console_putb(const char *buf, int len)
292{
293 struct ia64_sal_retval ret_stuff;
294
295 ret_stuff.status = 0;
296 ret_stuff.v0 = 0;
297 ret_stuff.v1 = 0;
298 ret_stuff.v2 = 0;
299 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_PUTB, (u64)buf, (u64)len, 0, 0, 0, 0, 0);
300
301 if ( ret_stuff.status == 0 ) {
302 return ret_stuff.v0;
303 }
304 return (u64)0;
305}
306
307/*
308 * Print a platform error record
309 */
310static inline u64
311ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec)
312{
313 struct ia64_sal_retval ret_stuff;
314
315 ret_stuff.status = 0;
316 ret_stuff.v0 = 0;
317 ret_stuff.v1 = 0;
318 ret_stuff.v2 = 0;
319 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_PRINT_ERROR, (u64)hook, (u64)rec, 0, 0, 0, 0, 0);
320
321 return ret_stuff.status;
322}
323
324/*
325 * Check for Platform errors
326 */
327static inline u64
328ia64_sn_plat_cpei_handler(void)
329{
330 struct ia64_sal_retval ret_stuff;
331
332 ret_stuff.status = 0;
333 ret_stuff.v0 = 0;
334 ret_stuff.v1 = 0;
335 ret_stuff.v2 = 0;
336 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0);
337
338 return ret_stuff.status;
339}
340
341/*
342 * Set Error Handling Features (Obsolete)
343 */
344static inline u64
345ia64_sn_plat_set_error_handling_features(void)
346{
347 struct ia64_sal_retval ret_stuff;
348
349 ret_stuff.status = 0;
350 ret_stuff.v0 = 0;
351 ret_stuff.v1 = 0;
352 ret_stuff.v2 = 0;
353 SAL_CALL_REENTRANT(ret_stuff, SN_SAL_SET_ERROR_HANDLING_FEATURES,
354 SAL_ERR_FEAT_LOG_SBES,
355 0, 0, 0, 0, 0, 0);
356
357 return ret_stuff.status;
358}
359
360/*
361 * Checks for console input.
362 */
363static inline u64
364ia64_sn_console_check(int *result)
365{
366 struct ia64_sal_retval ret_stuff;
367
368 ret_stuff.status = 0;
369 ret_stuff.v0 = 0;
370 ret_stuff.v1 = 0;
371 ret_stuff.v2 = 0;
372 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0);
373
374 /* result is in 'v0' */
375 *result = (int)ret_stuff.v0;
376
377 return ret_stuff.status;
378}
379
380/*
381 * Checks console interrupt status
382 */
383static inline u64
384ia64_sn_console_intr_status(void)
385{
386 struct ia64_sal_retval ret_stuff;
387
388 ret_stuff.status = 0;
389 ret_stuff.v0 = 0;
390 ret_stuff.v1 = 0;
391 ret_stuff.v2 = 0;
392 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
393 0, SAL_CONSOLE_INTR_STATUS,
394 0, 0, 0, 0, 0);
395
396 if (ret_stuff.status == 0) {
397 return ret_stuff.v0;
398 }
399
400 return 0;
401}
402
403/*
404 * Enable an interrupt on the SAL console device.
405 */
406static inline void
407ia64_sn_console_intr_enable(u64 intr)
408{
409 struct ia64_sal_retval ret_stuff;
410
411 ret_stuff.status = 0;
412 ret_stuff.v0 = 0;
413 ret_stuff.v1 = 0;
414 ret_stuff.v2 = 0;
415 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
416 intr, SAL_CONSOLE_INTR_ON,
417 0, 0, 0, 0, 0);
418}
419
420/*
421 * Disable an interrupt on the SAL console device.
422 */
423static inline void
424ia64_sn_console_intr_disable(u64 intr)
425{
426 struct ia64_sal_retval ret_stuff;
427
428 ret_stuff.status = 0;
429 ret_stuff.v0 = 0;
430 ret_stuff.v1 = 0;
431 ret_stuff.v2 = 0;
432 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_INTR,
433 intr, SAL_CONSOLE_INTR_OFF,
434 0, 0, 0, 0, 0);
435}
436
437/*
438 * Sends a character buffer to the console asynchronously.
439 */
440static inline u64
441ia64_sn_console_xmit_chars(char *buf, int len)
442{
443 struct ia64_sal_retval ret_stuff;
444
445 ret_stuff.status = 0;
446 ret_stuff.v0 = 0;
447 ret_stuff.v1 = 0;
448 ret_stuff.v2 = 0;
449 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_CONSOLE_XMIT_CHARS,
450 (u64)buf, (u64)len,
451 0, 0, 0, 0, 0);
452
453 if (ret_stuff.status == 0) {
454 return ret_stuff.v0;
455 }
456
457 return 0;
458}
459
460/*
461 * Returns the iobrick module Id
462 */
463static inline u64
464ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result)
465{
466 struct ia64_sal_retval ret_stuff;
467
468 ret_stuff.status = 0;
469 ret_stuff.v0 = 0;
470 ret_stuff.v1 = 0;
471 ret_stuff.v2 = 0;
472 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0);
473
474 /* result is in 'v0' */
475 *result = (int)ret_stuff.v0;
476
477 return ret_stuff.status;
478}
479
480/**
481 * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function
482 *
483 * SN_SAL_POD_MODE actually takes an argument, but it's always
484 * 0 when we call it from the kernel, so we don't have to expose
485 * it to the caller.
486 */
487static inline u64
488ia64_sn_pod_mode(void)
489{
490 struct ia64_sal_retval isrv;
491 SAL_CALL_REENTRANT(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0);
492 if (isrv.status)
493 return 0;
494 return isrv.v0;
495}
496
497/**
498 * ia64_sn_probe_mem - read from memory safely
499 * @addr: address to probe
500 * @size: number bytes to read (1,2,4,8)
501 * @data_ptr: address to store value read by probe (-1 returned if probe fails)
502 *
503 * Call into the SAL to do a memory read. If the read generates a machine
504 * check, this routine will recover gracefully and return -1 to the caller.
505 * @addr is usually a kernel virtual address in uncached space (i.e. the
506 * address starts with 0xc), but if called in physical mode, @addr should
507 * be a physical address.
508 *
509 * Return values:
510 * 0 - probe successful
511 * 1 - probe failed (generated MCA)
512 * 2 - Bad arg
513 * <0 - PAL error
514 */
515static inline u64
516ia64_sn_probe_mem(long addr, long size, void *data_ptr)
517{
518 struct ia64_sal_retval isrv;
519
520 SAL_CALL(isrv, SN_SAL_PROBE, addr, size, 0, 0, 0, 0, 0);
521
522 if (data_ptr) {
523 switch (size) {
524 case 1:
525 *((u8*)data_ptr) = (u8)isrv.v0;
526 break;
527 case 2:
528 *((u16*)data_ptr) = (u16)isrv.v0;
529 break;
530 case 4:
531 *((u32*)data_ptr) = (u32)isrv.v0;
532 break;
533 case 8:
534 *((u64*)data_ptr) = (u64)isrv.v0;
535 break;
536 default:
537 isrv.status = 2;
538 }
539 }
540 return isrv.status;
541}
542
543/*
544 * Retrieve the system serial number as an ASCII string.
545 */
546static inline u64
547ia64_sn_sys_serial_get(char *buf)
548{
549 struct ia64_sal_retval ret_stuff;
550 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0);
551 return ret_stuff.status;
552}
553
554extern char sn_system_serial_number_string[];
555extern u64 sn_partition_serial_number;
556
557static inline char *
558sn_system_serial_number(void) {
559 if (sn_system_serial_number_string[0]) {
560 return(sn_system_serial_number_string);
561 } else {
562 ia64_sn_sys_serial_get(sn_system_serial_number_string);
563 return(sn_system_serial_number_string);
564 }
565}
566
567
568/*
569 * Returns a unique id number for this system and partition (suitable for
570 * use with license managers), based in part on the system serial number.
571 */
572static inline u64
573ia64_sn_partition_serial_get(void)
574{
575 struct ia64_sal_retval ret_stuff;
576 ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
577 0, 0, 0, 0, 0, 0);
578 if (ret_stuff.status != 0)
579 return 0;
580 return ret_stuff.v0;
581}
582
583static inline u64
584sn_partition_serial_number_val(void) {
585 if (unlikely(sn_partition_serial_number == 0)) {
586 sn_partition_serial_number = ia64_sn_partition_serial_get();
587 }
588 return sn_partition_serial_number;
589}
590
591/*
592 * Returns the partition id of the nasid passed in as an argument,
593 * or INVALID_PARTID if the partition id cannot be retrieved.
594 */
595static inline partid_t
596ia64_sn_sysctl_partition_get(nasid_t nasid)
597{
598 struct ia64_sal_retval ret_stuff;
599 SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
600 0, 0, 0, 0, 0, 0);
601 if (ret_stuff.status != 0)
602 return -1;
603 return ((partid_t)ret_stuff.v0);
604}
605
606/*
607 * Returns the physical address of the partition's reserved page through
608 * an iterative number of calls.
609 *
610 * On first call, 'cookie' and 'len' should be set to 0, and 'addr'
611 * set to the nasid of the partition whose reserved page's address is
612 * being sought.
613 * On subsequent calls, pass the values, that were passed back on the
614 * previous call.
615 *
616 * While the return status equals SALRET_MORE_PASSES, keep calling
617 * this function after first copying 'len' bytes starting at 'addr'
618 * into 'buf'. Once the return status equals SALRET_OK, 'addr' will
619 * be the physical address of the partition's reserved page. If the
620 * return status equals neither of these, an error as occurred.
621 */
622static inline s64
623sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
624{
625 struct ia64_sal_retval rv;
626 ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
627 *addr, buf, *len, 0, 0, 0);
628 *cookie = rv.v0;
629 *addr = rv.v1;
630 *len = rv.v2;
631 return rv.status;
632}
633
634/*
635 * Register or unregister a physical address range being referenced across
636 * a partition boundary for which certain SAL errors should be scanned for,
637 * cleaned up and ignored. This is of value for kernel partitioning code only.
638 * Values for the operation argument:
639 * 1 = register this address range with SAL
640 * 0 = unregister this address range with SAL
641 *
642 * SAL maintains a reference count on an address range in case it is registered
643 * multiple times.
644 *
645 * On success, returns the reference count of the address range after the SAL
646 * call has performed the current registration/unregistration. Returns a
647 * negative value if an error occurred.
648 */
649static inline int
650sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
651{
652 struct ia64_sal_retval ret_stuff;
653 ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
654 (u64)operation, 0, 0, 0, 0);
655 return ret_stuff.status;
656}
657
658/*
659 * Register or unregister an instruction range for which SAL errors should
660 * be ignored. If an error occurs while in the registered range, SAL jumps
661 * to return_addr after ignoring the error. Values for the operation argument:
662 * 1 = register this instruction range with SAL
663 * 0 = unregister this instruction range with SAL
664 *
665 * Returns 0 on success, or a negative value if an error occurred.
666 */
667static inline int
668sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
669 int virtual, int operation)
670{
671 struct ia64_sal_retval ret_stuff;
672 u64 call;
673 if (virtual) {
674 call = SN_SAL_NO_FAULT_ZONE_VIRTUAL;
675 } else {
676 call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
677 }
678 ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
679 (u64)1, 0, 0, 0);
680 return ret_stuff.status;
681}
682
683/*
684 * Register or unregister a function to handle a PMI received by a CPU.
685 * Before calling the registered handler, SAL sets r1 to the value that
686 * was passed in as the global_pointer.
687 *
688 * If the handler pointer is NULL, then the currently registered handler
689 * will be unregistered.
690 *
691 * Returns 0 on success, or a negative value if an error occurred.
692 */
693static inline int
694sn_register_pmi_handler(u64 handler, u64 global_pointer)
695{
696 struct ia64_sal_retval ret_stuff;
697 ia64_sal_oemcall(&ret_stuff, SN_SAL_REGISTER_PMI_HANDLER, handler,
698 global_pointer, 0, 0, 0, 0, 0);
699 return ret_stuff.status;
700}
701
702/*
703 * Change or query the coherence domain for this partition. Each cpu-based
704 * nasid is represented by a bit in an array of 64-bit words:
705 * 0 = not in this partition's coherency domain
706 * 1 = in this partition's coherency domain
707 *
708 * It is not possible for the local system's nasids to be removed from
709 * the coherency domain. Purpose of the domain arguments:
710 * new_domain = set the coherence domain to the given nasids
711 * old_domain = return the current coherence domain
712 *
713 * Returns 0 on success, or a negative value if an error occurred.
714 */
715static inline int
716sn_change_coherence(u64 *new_domain, u64 *old_domain)
717{
718 struct ia64_sal_retval ret_stuff;
719 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
720 (u64)old_domain, 0, 0, 0, 0, 0);
721 return ret_stuff.status;
722}
723
724/*
725 * Change memory access protections for a physical address range.
726 * nasid_array is not used on Altix, but may be in future architectures.
727 * Available memory protection access classes are defined after the function.
728 */
729static inline int
730sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
731{
732 struct ia64_sal_retval ret_stuff;
733
734 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
735 (u64)nasid_array, perms, 0, 0, 0);
736 return ret_stuff.status;
737}
738#define SN_MEMPROT_ACCESS_CLASS_0 0x14a080
739#define SN_MEMPROT_ACCESS_CLASS_1 0x2520c2
740#define SN_MEMPROT_ACCESS_CLASS_2 0x14a1ca
741#define SN_MEMPROT_ACCESS_CLASS_3 0x14a290
742#define SN_MEMPROT_ACCESS_CLASS_6 0x084080
743#define SN_MEMPROT_ACCESS_CLASS_7 0x021080
744
745/*
746 * Turns off system power.
747 */
748static inline void
749ia64_sn_power_down(void)
750{
751 struct ia64_sal_retval ret_stuff;
752 SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0);
753 while(1)
754 cpu_relax();
755 /* never returns */
756}
757
758/**
759 * ia64_sn_fru_capture - tell the system controller to capture hw state
760 *
761 * This routine will call the SAL which will tell the system controller(s)
762 * to capture hw mmr information from each SHub in the system.
763 */
764static inline u64
765ia64_sn_fru_capture(void)
766{
767 struct ia64_sal_retval isrv;
768 SAL_CALL(isrv, SN_SAL_SYSCTL_FRU_CAPTURE, 0, 0, 0, 0, 0, 0, 0);
769 if (isrv.status)
770 return 0;
771 return isrv.v0;
772}
773
774/*
775 * Performs an operation on a PCI bus or slot -- power up, power down
776 * or reset.
777 */
778static inline u64
779ia64_sn_sysctl_iobrick_pci_op(nasid_t n, u64 connection_type,
780 u64 bus, char slot,
781 u64 action)
782{
783 struct ia64_sal_retval rv = {0, 0, 0, 0};
784
785 SAL_CALL_NOLOCK(rv, SN_SAL_SYSCTL_IOBRICK_PCI_OP, connection_type, n, action,
786 bus, (u64) slot, 0, 0);
787 if (rv.status)
788 return rv.v0;
789 return 0;
790}
791
792
793/*
794 * Open a subchannel for sending arbitrary data to the system
795 * controller network via the system controller device associated with
796 * 'nasid'. Return the subchannel number or a negative error code.
797 */
798static inline int
799ia64_sn_irtr_open(nasid_t nasid)
800{
801 struct ia64_sal_retval rv;
802 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_OPEN, nasid,
803 0, 0, 0, 0, 0);
804 return (int) rv.v0;
805}
806
807/*
808 * Close system controller subchannel 'subch' previously opened on 'nasid'.
809 */
810static inline int
811ia64_sn_irtr_close(nasid_t nasid, int subch)
812{
813 struct ia64_sal_retval rv;
814 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_CLOSE,
815 (u64) nasid, (u64) subch, 0, 0, 0, 0);
816 return (int) rv.status;
817}
818
819/*
820 * Read data from system controller associated with 'nasid' on
821 * subchannel 'subch'. The buffer to be filled is pointed to by
822 * 'buf', and its capacity is in the integer pointed to by 'len'. The
823 * referent of 'len' is set to the number of bytes read by the SAL
824 * call. The return value is either SALRET_OK (for bytes read) or
825 * SALRET_ERROR (for error or "no data available").
826 */
827static inline int
828ia64_sn_irtr_recv(nasid_t nasid, int subch, char *buf, int *len)
829{
830 struct ia64_sal_retval rv;
831 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_RECV,
832 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
833 0, 0);
834 return (int) rv.status;
835}
836
837/*
838 * Write data to the system controller network via the system
839 * controller associated with 'nasid' on suchannel 'subch'. The
840 * buffer to be written out is pointed to by 'buf', and 'len' is the
841 * number of bytes to be written. The return value is either the
842 * number of bytes written (which could be zero) or a negative error
843 * code.
844 */
845static inline int
846ia64_sn_irtr_send(nasid_t nasid, int subch, char *buf, int len)
847{
848 struct ia64_sal_retval rv;
849 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_SEND,
850 (u64) nasid, (u64) subch, (u64) buf, (u64) len,
851 0, 0);
852 return (int) rv.v0;
853}
854
855/*
856 * Check whether any interrupts are pending for the system controller
857 * associated with 'nasid' and its subchannel 'subch'. The return
858 * value is a mask of pending interrupts (SAL_IROUTER_INTR_XMIT and/or
859 * SAL_IROUTER_INTR_RECV).
860 */
861static inline int
862ia64_sn_irtr_intr(nasid_t nasid, int subch)
863{
864 struct ia64_sal_retval rv;
865 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_STATUS,
866 (u64) nasid, (u64) subch, 0, 0, 0, 0);
867 return (int) rv.v0;
868}
869
870/*
871 * Enable the interrupt indicated by the intr parameter (either
872 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
873 */
874static inline int
875ia64_sn_irtr_intr_enable(nasid_t nasid, int subch, u64 intr)
876{
877 struct ia64_sal_retval rv;
878 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_ON,
879 (u64) nasid, (u64) subch, intr, 0, 0, 0);
880 return (int) rv.v0;
881}
882
883/*
884 * Disable the interrupt indicated by the intr parameter (either
885 * SAL_IROUTER_INTR_XMIT or SAL_IROUTER_INTR_RECV).
886 */
887static inline int
888ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
889{
890 struct ia64_sal_retval rv;
891 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INTR_OFF,
892 (u64) nasid, (u64) subch, intr, 0, 0, 0);
893 return (int) rv.v0;
894}
895
896/*
897 * Set up a node as the point of contact for system controller
898 * environmental event delivery.
899 */
900static inline int
901ia64_sn_sysctl_event_init(nasid_t nasid)
902{
903 struct ia64_sal_retval rv;
904 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
905 0, 0, 0, 0, 0, 0);
906 return (int) rv.v0;
907}
908
909/*
910 * Ask the system controller on the specified nasid to reset
911 * the CX corelet clock. Only valid on TIO nodes.
912 */
913static inline int
914ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
915{
916 struct ia64_sal_retval rv;
917 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_TIO_JLCK_RST,
918 nasid, 0, 0, 0, 0, 0);
919 if (rv.status != 0)
920 return (int)rv.status;
921 if (rv.v0 != 0)
922 return (int)rv.v0;
923
924 return 0;
925}
926
927/*
928 * Get the associated ioboard type for a given nasid.
929 */
930static inline s64
931ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
932{
933 struct ia64_sal_retval isrv;
934 SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
935 nasid, 0, 0, 0, 0, 0);
936 if (isrv.v0 != 0) {
937 *ioboard = isrv.v0;
938 return isrv.status;
939 }
940 if (isrv.v1 != 0) {
941 *ioboard = isrv.v1;
942 return isrv.status;
943 }
944
945 return isrv.status;
946}
947
948/**
949 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
950 * @nasid: NASID of node to read
951 * @index: FIT entry index to be retrieved (0..n)
952 * @fitentry: 16 byte buffer where FIT entry will be stored.
953 * @banbuf: optional buffer for retrieving banner
954 * @banlen: length of banner buffer
955 *
956 * Access to the physical PROM chips needs to be serialized since reads and
957 * writes can't occur at the same time, so we need to call into the SAL when
958 * we want to look at the FIT entries on the chips.
959 *
960 * Returns:
961 * %SALRET_OK if ok
962 * %SALRET_INVALID_ARG if index too big
963 * %SALRET_NOT_IMPLEMENTED if running on older PROM
964 * ??? if nasid invalid OR banner buffer not large enough
965 */
966static inline int
967ia64_sn_get_fit_compt(u64 nasid, u64 index, void *fitentry, void *banbuf,
968 u64 banlen)
969{
970 struct ia64_sal_retval rv;
971 SAL_CALL_NOLOCK(rv, SN_SAL_GET_FIT_COMPT, nasid, index, fitentry,
972 banbuf, banlen, 0, 0);
973 return (int) rv.status;
974}
975
976/*
977 * Initialize the SAL components of the system controller
978 * communication driver; specifically pass in a sizable buffer that
979 * can be used for allocation of subchannel queues as new subchannels
980 * are opened. "buf" points to the buffer, and "len" specifies its
981 * length.
982 */
983static inline int
984ia64_sn_irtr_init(nasid_t nasid, void *buf, int len)
985{
986 struct ia64_sal_retval rv;
987 SAL_CALL_REENTRANT(rv, SN_SAL_IROUTER_OP, SAL_IROUTER_INIT,
988 (u64) nasid, (u64) buf, (u64) len, 0, 0, 0);
989 return (int) rv.status;
990}
991
992/*
993 * Returns the nasid, subnode & slice corresponding to a SAPIC ID
994 *
995 * In:
996 * arg0 - SN_SAL_GET_SAPIC_INFO
997 * arg1 - sapicid (lid >> 16)
998 * Out:
999 * v0 - nasid
1000 * v1 - subnode
1001 * v2 - slice
1002 */
1003static inline u64
1004ia64_sn_get_sapic_info(int sapicid, int *nasid, int *subnode, int *slice)
1005{
1006 struct ia64_sal_retval ret_stuff;
1007
1008 ret_stuff.status = 0;
1009 ret_stuff.v0 = 0;
1010 ret_stuff.v1 = 0;
1011 ret_stuff.v2 = 0;
1012 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SAPIC_INFO, sapicid, 0, 0, 0, 0, 0, 0);
1013
1014/***** BEGIN HACK - temp til old proms no longer supported ********/
1015 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1016 if (nasid) *nasid = sapicid & 0xfff;
1017 if (subnode) *subnode = (sapicid >> 13) & 1;
1018 if (slice) *slice = (sapicid >> 12) & 3;
1019 return 0;
1020 }
1021/***** END HACK *******/
1022
1023 if (ret_stuff.status < 0)
1024 return ret_stuff.status;
1025
1026 if (nasid) *nasid = (int) ret_stuff.v0;
1027 if (subnode) *subnode = (int) ret_stuff.v1;
1028 if (slice) *slice = (int) ret_stuff.v2;
1029 return 0;
1030}
1031
1032/*
1033 * Returns information about the HUB/SHUB.
1034 * In:
1035 * arg0 - SN_SAL_GET_SN_INFO
1036 * arg1 - 0 (other values reserved for future use)
1037 * Out:
1038 * v0
1039 * [7:0] - shub type (0=shub1, 1=shub2)
1040 * [15:8] - Log2 max number of nodes in entire system (includes
1041 * C-bricks, I-bricks, etc)
1042 * [23:16] - Log2 of nodes per sharing domain
1043 * [31:24] - partition ID
1044 * [39:32] - coherency_id
1045 * [47:40] - regionsize
1046 * v1
1047 * [15:0] - nasid mask (ex., 0x7ff for 11 bit nasid)
1048 * [23:15] - bit position of low nasid bit
1049 */
1050static inline u64
1051ia64_sn_get_sn_info(int fc, u8 *shubtype, u16 *nasid_bitmask, u8 *nasid_shift,
1052 u8 *systemsize, u8 *sharing_domain_size, u8 *partid, u8 *coher, u8 *reg)
1053{
1054 struct ia64_sal_retval ret_stuff;
1055
1056 ret_stuff.status = 0;
1057 ret_stuff.v0 = 0;
1058 ret_stuff.v1 = 0;
1059 ret_stuff.v2 = 0;
1060 SAL_CALL_NOLOCK(ret_stuff, SN_SAL_GET_SN_INFO, fc, 0, 0, 0, 0, 0, 0);
1061
1062/***** BEGIN HACK - temp til old proms no longer supported ********/
1063 if (ret_stuff.status == SALRET_NOT_IMPLEMENTED) {
1064 int nasid = get_sapicid() & 0xfff;
1065#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000UL
1066#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48
1067 if (shubtype) *shubtype = 0;
1068 if (nasid_bitmask) *nasid_bitmask = 0x7ff;
1069 if (nasid_shift) *nasid_shift = 38;
1070 if (systemsize) *systemsize = 10;
1071 if (sharing_domain_size) *sharing_domain_size = 8;
1072 if (partid) *partid = ia64_sn_sysctl_partition_get(nasid);
1073 if (coher) *coher = nasid >> 9;
1074 if (reg) *reg = (HUB_L((u64 *) LOCAL_MMR_ADDR(SH1_SHUB_ID)) & SH_SHUB_ID_NODES_PER_BIT_MASK) >>
1075 SH_SHUB_ID_NODES_PER_BIT_SHFT;
1076 return 0;
1077 }
1078/***** END HACK *******/
1079
1080 if (ret_stuff.status < 0)
1081 return ret_stuff.status;
1082
1083 if (shubtype) *shubtype = ret_stuff.v0 & 0xff;
1084 if (systemsize) *systemsize = (ret_stuff.v0 >> 8) & 0xff;
1085 if (sharing_domain_size) *sharing_domain_size = (ret_stuff.v0 >> 16) & 0xff;
1086 if (partid) *partid = (ret_stuff.v0 >> 24) & 0xff;
1087 if (coher) *coher = (ret_stuff.v0 >> 32) & 0xff;
1088 if (reg) *reg = (ret_stuff.v0 >> 40) & 0xff;
1089 if (nasid_bitmask) *nasid_bitmask = (ret_stuff.v1 & 0xffff);
1090 if (nasid_shift) *nasid_shift = (ret_stuff.v1 >> 16) & 0xff;
1091 return 0;
1092}
1093
1094/*
1095 * This is the access point to the Altix PROM hardware performance
1096 * and status monitoring interface. For info on using this, see
1097 * arch/ia64/include/asm/sn/sn2/sn_hwperf.h
1098 */
1099static inline int
1100ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
1101 u64 a3, u64 a4, int *v0)
1102{
1103 struct ia64_sal_retval rv;
1104 SAL_CALL_NOLOCK(rv, SN_SAL_HWPERF_OP, (u64)nasid,
1105 opcode, a0, a1, a2, a3, a4);
1106 if (v0)
1107 *v0 = (int) rv.v0;
1108 return (int) rv.status;
1109}
1110
1111static inline int
1112ia64_sn_ioif_get_pci_topology(u64 buf, u64 len)
1113{
1114 struct ia64_sal_retval rv;
1115 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY, buf, len, 0, 0, 0, 0, 0);
1116 return (int) rv.status;
1117}
1118
1119/*
1120 * BTE error recovery is implemented in SAL
1121 */
1122static inline int
1123ia64_sn_bte_recovery(nasid_t nasid)
1124{
1125 struct ia64_sal_retval rv;
1126
1127 rv.status = 0;
1128 SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, (u64)nasid, 0, 0, 0, 0, 0, 0);
1129 if (rv.status == SALRET_NOT_IMPLEMENTED)
1130 return 0;
1131 return (int) rv.status;
1132}
1133
1134static inline int
1135ia64_sn_is_fake_prom(void)
1136{
1137 struct ia64_sal_retval rv;
1138 SAL_CALL_NOLOCK(rv, SN_SAL_FAKE_PROM, 0, 0, 0, 0, 0, 0, 0);
1139 return (rv.status == 0);
1140}
1141
1142static inline int
1143ia64_sn_get_prom_feature_set(int set, unsigned long *feature_set)
1144{
1145 struct ia64_sal_retval rv;
1146
1147 SAL_CALL_NOLOCK(rv, SN_SAL_GET_PROM_FEATURE_SET, set, 0, 0, 0, 0, 0, 0);
1148 if (rv.status != 0)
1149 return rv.status;
1150 *feature_set = rv.v0;
1151 return 0;
1152}
1153
1154static inline int
1155ia64_sn_set_os_feature(int feature)
1156{
1157 struct ia64_sal_retval rv;
1158
1159 SAL_CALL_NOLOCK(rv, SN_SAL_SET_OS_FEATURE_SET, feature, 0, 0, 0, 0, 0, 0);
1160 return rv.status;
1161}
1162
1163static inline int
1164sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
1165{
1166 struct ia64_sal_retval ret_stuff;
1167
1168 ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
1169 (u64)ecc, 0, 0, 0, 0);
1170 return ret_stuff.status;
1171}
1172
1173static inline int
1174ia64_sn_set_cpu_number(int cpu)
1175{
1176 struct ia64_sal_retval rv;
1177
1178 SAL_CALL_NOLOCK(rv, SN_SAL_SET_CPU_NUMBER, cpu, 0, 0, 0, 0, 0, 0);
1179 return rv.status;
1180}
1181static inline int
1182ia64_sn_kernel_launch_event(void)
1183{
1184 struct ia64_sal_retval rv;
1185 SAL_CALL_NOLOCK(rv, SN_SAL_KERNEL_LAUNCH_EVENT, 0, 0, 0, 0, 0, 0, 0);
1186 return rv.status;
1187}
1188#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/arch/ia64/include/asm/sn/tioca.h b/arch/ia64/include/asm/sn/tioca.h
new file mode 100644
index 000000000000..666222d7f0f6
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioca.h
@@ -0,0 +1,596 @@
1#ifndef _ASM_IA64_SN_TIO_TIOCA_H
2#define _ASM_IA64_SN_TIO_TIOCA_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
10 */
11
12
13#define TIOCA_PART_NUM 0xE020
14#define TIOCA_MFGR_NUM 0x24
15#define TIOCA_REV_A 0x1
16
17/*
18 * Register layout for TIO:CA. See below for bitmasks for each register.
19 */
20
21struct tioca {
22 u64 ca_id; /* 0x000000 */
23 u64 ca_control1; /* 0x000008 */
24 u64 ca_control2; /* 0x000010 */
25 u64 ca_status1; /* 0x000018 */
26 u64 ca_status2; /* 0x000020 */
27 u64 ca_gart_aperature; /* 0x000028 */
28 u64 ca_gfx_detach; /* 0x000030 */
29 u64 ca_inta_dest_addr; /* 0x000038 */
30 u64 ca_intb_dest_addr; /* 0x000040 */
31 u64 ca_err_int_dest_addr; /* 0x000048 */
32 u64 ca_int_status; /* 0x000050 */
33 u64 ca_int_status_alias; /* 0x000058 */
34 u64 ca_mult_error; /* 0x000060 */
35 u64 ca_mult_error_alias; /* 0x000068 */
36 u64 ca_first_error; /* 0x000070 */
37 u64 ca_int_mask; /* 0x000078 */
38 u64 ca_crm_pkterr_type; /* 0x000080 */
39 u64 ca_crm_pkterr_type_alias; /* 0x000088 */
40 u64 ca_crm_ct_error_detail_1; /* 0x000090 */
41 u64 ca_crm_ct_error_detail_2; /* 0x000098 */
42 u64 ca_crm_tnumto; /* 0x0000A0 */
43 u64 ca_gart_err; /* 0x0000A8 */
44 u64 ca_pcierr_type; /* 0x0000B0 */
45 u64 ca_pcierr_addr; /* 0x0000B8 */
46
47 u64 ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48
49 u64 ca_pci_rd_buf_flush; /* 0x0000D8 */
50 u64 ca_pci_dma_addr_extn; /* 0x0000E0 */
51 u64 ca_agp_dma_addr_extn; /* 0x0000E8 */
52 u64 ca_force_inta; /* 0x0000F0 */
53 u64 ca_force_intb; /* 0x0000F8 */
54 u64 ca_debug_vector_sel; /* 0x000100 */
55 u64 ca_debug_mux_core_sel; /* 0x000108 */
56 u64 ca_debug_mux_pci_sel; /* 0x000110 */
57 u64 ca_debug_domain_sel; /* 0x000118 */
58
59 u64 ca_pad_000120[28]; /* 0x0001{20..F8} */
60
61 u64 ca_gart_ptr_table; /* 0x200 */
62 u64 ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63};
64
65/*
66 * Mask/shift definitions for TIO:CA registers. The convention here is
67 * to mainly use the names as they appear in the "TIO AEGIS Programmers'
68 * Reference" with a CA_ prefix added. Some exceptions were made to fix
69 * duplicate field names or to generalize fields that are common to
70 * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
71 * example).
72 *
73 * Fields consisting of a single bit have a single #define have a single
74 * macro declaration to mask the bit. Fields consisting of multiple bits
75 * have two declarations: one to mask the proper bits in a register, and
76 * a second with the suffix "_SHFT" to identify how far the mask needs to
77 * be shifted right to get its base value.
78 */
79
80/* ==== ca_control1 */
81#define CA_SYS_BIG_END (1ull << 0)
82#define CA_DMA_AGP_SWAP (1ull << 1)
83#define CA_DMA_PCI_SWAP (1ull << 2)
84#define CA_PIO_IO_SWAP (1ull << 3)
85#define CA_PIO_MEM_SWAP (1ull << 4)
86#define CA_GFX_WR_SWAP (1ull << 5)
87#define CA_AGP_FW_ENABLE (1ull << 6)
88#define CA_AGP_CAL_CYCLE (0x7ull << 7)
89#define CA_AGP_CAL_CYCLE_SHFT 7
90#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
91#define CA_AGP_INIT_CAL_ENB (1ull << 11)
92#define CA_INJ_ADDR_PERR (1ull << 12)
93#define CA_INJ_DATA_PERR (1ull << 13)
94 /* bits 15:14 unused */
95#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
96#define CA_PCIM_IO_NBE_AD_SHFT 16
97#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
98 /* bits 23:20 unused */
99#define CA_PIO_ADDR_OFFSET (0xffull << 24)
100#define CA_PIO_ADDR_OFFSET_SHFT 24
101 /* bits 35:32 unused */
102#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
103#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
104 /* bit 41 unused */
105#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
106#define CA_PCI_INT_LPCNT (0xffull << 44)
107#define CA_PCI_INT_LPCNT_SHFT 44
108 /* bits 63:52 unused */
109
110/* ==== ca_control2 */
111#define CA_AGP_LATENCY_TO (0xffull << 0)
112#define CA_AGP_LATENCY_TO_SHFT 0
113#define CA_PCI_LATENCY_TO (0xffull << 8)
114#define CA_PCI_LATENCY_TO_SHFT 8
115#define CA_PCI_MAX_RETRY (0x3ffull << 16)
116#define CA_PCI_MAX_RETRY_SHFT 16
117 /* bits 27:26 unused */
118#define CA_RT_INT_EN (0x3ull << 28)
119#define CA_RT_INT_EN_SHFT 28
120#define CA_MSI_INT_ENB (1ull << 30)
121#define CA_PCI_ARB_ERR_ENB (1ull << 31)
122#define CA_GART_MEM_PARAM (0x3ull << 32)
123#define CA_GART_MEM_PARAM_SHFT 32
124#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
125#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
126#define CA_GART_FLUSH_TLB (1ull << 36)
127 /* bits 39:37 unused */
128#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
129#define CA_CRM_TNUMTO_PERIOD_SHFT 40
130 /* bits 55:53 unused */
131#define CA_CRM_TNUMTO_ENB (1ull << 56)
132#define CA_CRM_PRESCALER_BYP (1ull << 57)
133 /* bits 59:58 unused */
134#define CA_CRM_MAX_CREDIT (0x7ull << 60)
135#define CA_CRM_MAX_CREDIT_SHFT 60
136 /* bit 63 unused */
137
138/* ==== ca_status1 */
139#define CA_CORELET_ID (0x3ull << 0)
140#define CA_CORELET_ID_SHFT 0
141#define CA_INTA_N (1ull << 2)
142#define CA_INTB_N (1ull << 3)
143#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
144#define CA_CRM_CREDIT_AVAIL_SHFT 4
145 /* bit 7 unused */
146#define CA_CRM_SPACE_AVAIL (0x7full << 8)
147#define CA_CRM_SPACE_AVAIL_SHFT 8
148 /* bit 15 unused */
149#define CA_GART_TLB_VAL (0xffull << 16)
150#define CA_GART_TLB_VAL_SHFT 16
151 /* bits 63:24 unused */
152
153/* ==== ca_status2 */
154#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
155#define CA_GFX_CREDIT_AVAIL_SHFT 0
156#define CA_GFX_OPQ_AVAIL (0xffull << 8)
157#define CA_GFX_OPQ_AVAIL_SHFT 8
158#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
159#define CA_GFX_WRBUFF_AVAIL_SHFT 16
160#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
161#define CA_ADMA_OPQ_AVAIL_SHFT 24
162#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
163#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
164#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
165#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
166#define CA_PCI_PIO_OP_STAT (1ull << 47)
167#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
168#define CA_PDMA_OPQ_AVAIL_SHFT 48
169#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
170#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
171#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
172#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
173 /* bits 63:58 unused */
174
175/* ==== ca_gart_aperature */
176#define CA_GART_AP_ENB_AGP (1ull << 0)
177#define CA_GART_PAGE_SIZE (1ull << 1)
178#define CA_GART_AP_ENB_PCI (1ull << 2)
179 /* bits 11:3 unused */
180#define CA_GART_AP_SIZE (0x3ffull << 12)
181#define CA_GART_AP_SIZE_SHFT 12
182#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
183#define CA_GART_AP_BASE_SHFT 22
184
185/* ==== ca_inta_dest_addr
186 ==== ca_intb_dest_addr
187 ==== ca_err_int_dest_addr */
188 /* bits 2:0 unused */
189#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
190#define CA_INT_DEST_ADDR_SHFT 3
191 /* bits 55:54 unused */
192#define CA_INT_DEST_VECT (0xffull << 56)
193#define CA_INT_DEST_VECT_SHFT 56
194
195/* ==== ca_int_status */
196/* ==== ca_int_status_alias */
197/* ==== ca_mult_error */
198/* ==== ca_mult_error_alias */
199/* ==== ca_first_error */
200/* ==== ca_int_mask */
201#define CA_PCI_ERR (1ull << 0)
202 /* bits 3:1 unused */
203#define CA_GART_FETCH_ERR (1ull << 4)
204#define CA_GFX_WR_OVFLW (1ull << 5)
205#define CA_PIO_REQ_OVFLW (1ull << 6)
206#define CA_CRM_PKTERR (1ull << 7)
207#define CA_CRM_DVERR (1ull << 8)
208#define CA_TNUMTO (1ull << 9)
209#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
210#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
211#define CA_PIO_INVALID_ADDR (1ull << 12)
212#define CA_PCI_ARB_TO (1ull << 13)
213#define CA_AGP_REQ_OFLOW (1ull << 14)
214#define CA_SBA_TYPE1_ERR (1ull << 15)
215 /* bit 16 unused */
216#define CA_INTA (1ull << 17)
217#define CA_INTB (1ull << 18)
218#define CA_MULT_INTA (1ull << 19)
219#define CA_MULT_INTB (1ull << 20)
220#define CA_GFX_CREDIT_OVFLW (1ull << 21)
221 /* bits 63:22 unused */
222
223/* ==== ca_crm_pkterr_type */
224/* ==== ca_crm_pkterr_type_alias */
225#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
226#define CA_CRM_PKTERR_DIDN (1ull << 1)
227#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
228#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
229#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
230#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
231#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
232#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
233#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
234#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
235#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
236#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
237#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
238 /* bits 15:13 unused */
239#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
240#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
241#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
242#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
243#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
244#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
245#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
246#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
247#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
248#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
249#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
250#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
251#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
252 /* bits 63:29 unused */
253
254/* ==== ca_crm_ct_error_detail_1 */
255#define CA_PKT_TYPE (0xfull << 0)
256#define CA_PKT_TYPE_SHFT 0
257#define CA_SRC_ID (0x3ull << 4)
258#define CA_SRC_ID_SHFT 4
259#define CA_DATA_SZ (0x3ull << 6)
260#define CA_DATA_SZ_SHFT 6
261#define CA_TNUM (0xffull << 8)
262#define CA_TNUM_SHFT 8
263#define CA_DW_DATA_EN (0xffull << 16)
264#define CA_DW_DATA_EN_SHFT 16
265#define CA_GFX_CRED (0xffull << 24)
266#define CA_GFX_CRED_SHFT 24
267#define CA_MEM_RD_PARAM (0x3ull << 32)
268#define CA_MEM_RD_PARAM_SHFT 32
269#define CA_PIO_OP (1ull << 34)
270#define CA_CW_ERR (1ull << 35)
271 /* bits 62:36 unused */
272#define CA_VALID (1ull << 63)
273
274/* ==== ca_crm_ct_error_detail_2 */
275 /* bits 2:0 unused */
276#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
277#define CA_PKT_ADDR_SHFT 3
278 /* bits 63:56 unused */
279
280/* ==== ca_crm_tnumto */
281#define CA_CRM_TNUMTO_VAL (0xffull << 0)
282#define CA_CRM_TNUMTO_VAL_SHFT 0
283#define CA_CRM_TNUMTO_WR (1ull << 8)
284 /* bits 63:9 unused */
285
286/* ==== ca_gart_err */
287#define CA_GART_ERR_SOURCE (0x3ull << 0)
288#define CA_GART_ERR_SOURCE_SHFT 0
289 /* bits 3:2 unused */
290#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
291#define CA_GART_ERR_ADDR_SHFT 4
292 /* bits 63:40 unused */
293
294/* ==== ca_pcierr_type */
295#define CA_PCIERR_DATA (0xffffffffull << 0)
296#define CA_PCIERR_DATA_SHFT 0
297#define CA_PCIERR_ENB (0xfull << 32)
298#define CA_PCIERR_ENB_SHFT 32
299#define CA_PCIERR_CMD (0xfull << 36)
300#define CA_PCIERR_CMD_SHFT 36
301#define CA_PCIERR_A64 (1ull << 40)
302#define CA_PCIERR_SLV_SERR (1ull << 41)
303#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
304#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
305#define CA_PCIERR_MST_SERR (1ull << 44)
306#define CA_PCIERR_MST_WR_PERR (1ull << 45)
307#define CA_PCIERR_MST_RD_PERR (1ull << 46)
308#define CA_PCIERR_MST_MABT (1ull << 47)
309#define CA_PCIERR_MST_TABT (1ull << 48)
310#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
311
312#define CA_PCIERR_TYPES \
313 (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
314 CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
315 CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
316 CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
317
318 /* bits 63:50 unused */
319
320/* ==== ca_pci_dma_addr_extn */
321#define CA_UPPER_NODE_OFFSET (0x3full << 0)
322#define CA_UPPER_NODE_OFFSET_SHFT 0
323 /* bits 7:6 unused */
324#define CA_CHIPLET_ID (0x3ull << 8)
325#define CA_CHIPLET_ID_SHFT 8
326 /* bits 11:10 unused */
327#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
328#define CA_PCI_DMA_NODE_ID_SHFT 12
329 /* bits 27:26 unused */
330#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
331 /* bits 63:29 unused */
332
333
334/* ==== ca_agp_dma_addr_extn */
335 /* bits 19:0 unused */
336#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
337#define CA_AGP_DMA_NODE_ID_SHFT 20
338 /* bits 27:26 unused */
339#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
340 /* bits 63:29 unused */
341
342/* ==== ca_debug_vector_sel */
343#define CA_DEBUG_MN_VSEL (0xfull << 0)
344#define CA_DEBUG_MN_VSEL_SHFT 0
345#define CA_DEBUG_PP_VSEL (0xfull << 4)
346#define CA_DEBUG_PP_VSEL_SHFT 4
347#define CA_DEBUG_GW_VSEL (0xfull << 8)
348#define CA_DEBUG_GW_VSEL_SHFT 8
349#define CA_DEBUG_GT_VSEL (0xfull << 12)
350#define CA_DEBUG_GT_VSEL_SHFT 12
351#define CA_DEBUG_PD_VSEL (0xfull << 16)
352#define CA_DEBUG_PD_VSEL_SHFT 16
353#define CA_DEBUG_AD_VSEL (0xfull << 20)
354#define CA_DEBUG_AD_VSEL_SHFT 20
355#define CA_DEBUG_CX_VSEL (0xfull << 24)
356#define CA_DEBUG_CX_VSEL_SHFT 24
357#define CA_DEBUG_CR_VSEL (0xfull << 28)
358#define CA_DEBUG_CR_VSEL_SHFT 28
359#define CA_DEBUG_BA_VSEL (0xfull << 32)
360#define CA_DEBUG_BA_VSEL_SHFT 32
361#define CA_DEBUG_PE_VSEL (0xfull << 36)
362#define CA_DEBUG_PE_VSEL_SHFT 36
363#define CA_DEBUG_BO_VSEL (0xfull << 40)
364#define CA_DEBUG_BO_VSEL_SHFT 40
365#define CA_DEBUG_BI_VSEL (0xfull << 44)
366#define CA_DEBUG_BI_VSEL_SHFT 44
367#define CA_DEBUG_AS_VSEL (0xfull << 48)
368#define CA_DEBUG_AS_VSEL_SHFT 48
369#define CA_DEBUG_PS_VSEL (0xfull << 52)
370#define CA_DEBUG_PS_VSEL_SHFT 52
371#define CA_DEBUG_PM_VSEL (0xfull << 56)
372#define CA_DEBUG_PM_VSEL_SHFT 56
373 /* bits 63:60 unused */
374
375/* ==== ca_debug_mux_core_sel */
376/* ==== ca_debug_mux_pci_sel */
377#define CA_DEBUG_MSEL0 (0x7ull << 0)
378#define CA_DEBUG_MSEL0_SHFT 0
379 /* bit 3 unused */
380#define CA_DEBUG_NSEL0 (0x7ull << 4)
381#define CA_DEBUG_NSEL0_SHFT 4
382 /* bit 7 unused */
383#define CA_DEBUG_MSEL1 (0x7ull << 8)
384#define CA_DEBUG_MSEL1_SHFT 8
385 /* bit 11 unused */
386#define CA_DEBUG_NSEL1 (0x7ull << 12)
387#define CA_DEBUG_NSEL1_SHFT 12
388 /* bit 15 unused */
389#define CA_DEBUG_MSEL2 (0x7ull << 16)
390#define CA_DEBUG_MSEL2_SHFT 16
391 /* bit 19 unused */
392#define CA_DEBUG_NSEL2 (0x7ull << 20)
393#define CA_DEBUG_NSEL2_SHFT 20
394 /* bit 23 unused */
395#define CA_DEBUG_MSEL3 (0x7ull << 24)
396#define CA_DEBUG_MSEL3_SHFT 24
397 /* bit 27 unused */
398#define CA_DEBUG_NSEL3 (0x7ull << 28)
399#define CA_DEBUG_NSEL3_SHFT 28
400 /* bit 31 unused */
401#define CA_DEBUG_MSEL4 (0x7ull << 32)
402#define CA_DEBUG_MSEL4_SHFT 32
403 /* bit 35 unused */
404#define CA_DEBUG_NSEL4 (0x7ull << 36)
405#define CA_DEBUG_NSEL4_SHFT 36
406 /* bit 39 unused */
407#define CA_DEBUG_MSEL5 (0x7ull << 40)
408#define CA_DEBUG_MSEL5_SHFT 40
409 /* bit 43 unused */
410#define CA_DEBUG_NSEL5 (0x7ull << 44)
411#define CA_DEBUG_NSEL5_SHFT 44
412 /* bit 47 unused */
413#define CA_DEBUG_MSEL6 (0x7ull << 48)
414#define CA_DEBUG_MSEL6_SHFT 48
415 /* bit 51 unused */
416#define CA_DEBUG_NSEL6 (0x7ull << 52)
417#define CA_DEBUG_NSEL6_SHFT 52
418 /* bit 55 unused */
419#define CA_DEBUG_MSEL7 (0x7ull << 56)
420#define CA_DEBUG_MSEL7_SHFT 56
421 /* bit 59 unused */
422#define CA_DEBUG_NSEL7 (0x7ull << 60)
423#define CA_DEBUG_NSEL7_SHFT 60
424 /* bit 63 unused */
425
426
427/* ==== ca_debug_domain_sel */
428#define CA_DEBUG_DOMAIN_L (1ull << 0)
429#define CA_DEBUG_DOMAIN_H (1ull << 1)
430 /* bits 63:2 unused */
431
432/* ==== ca_gart_ptr_table */
433#define CA_GART_PTR_VAL (1ull << 0)
434 /* bits 11:1 unused */
435#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
436#define CA_GART_PTR_ADDR_SHFT 12
437 /* bits 63:56 unused */
438
439/* ==== ca_gart_tlb_addr[0-7] */
440#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
441#define CA_GART_TLB_ADDR_SHFT 0
442 /* bits 62:56 unused */
443#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
444
445/*
446 * PIO address space ranges for TIO:CA
447 */
448
449/* CA internal registers */
450#define CA_PIO_ADMIN 0x00000000
451#define CA_PIO_ADMIN_LEN 0x00010000
452
453/* GFX Write Buffer - Diagnostics */
454#define CA_PIO_GFX 0x00010000
455#define CA_PIO_GFX_LEN 0x00010000
456
457/* AGP DMA Write Buffer - Diagnostics */
458#define CA_PIO_AGP_DMAWRITE 0x00020000
459#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
460
461/* AGP DMA READ Buffer - Diagnostics */
462#define CA_PIO_AGP_DMAREAD 0x00030000
463#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
464
465/* PCI Config Type 0 */
466#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
467#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
468
469/* PCI Config Type 1 */
470#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
471#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
472
473/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
474#define CA_PIO_PCI_IO 0x03000000
475#define CA_PIO_PCI_IO_LEN 0x05000000
476
477/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
478/* use Fast Write if enabled and coretalk packet type is a GFX request */
479#define CA_PIO_PCI_MEM_OFFSET 0x08000000
480#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
481
482/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
483/* use Fast Write if enabled and coretalk packet type is a GFX request */
484#define CA_PIO_PCI_MEM 0x40000000
485#define CA_PIO_PCI_MEM_LEN 0xc0000000
486
487/*
488 * DMA space
489 *
490 * The CA aperature (ie. bus address range) mapped by the GART is segmented into
491 * two parts. The lower portion of the aperature is used for mapping 32 bit
492 * PCI addresses which are managed by the dma interfaces in this file. The
493 * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
494 * The AGP portion of the aperature is managed by the agpgart_be.c driver
495 * in drivers/linux/agp. There are ca-specific hooks in that driver to
496 * manipulate the gart, but management of the AGP portion of the aperature
497 * is the responsibility of that driver.
498 *
499 * CA allows three main types of DMA mapping:
500 *
501 * PCI 64-bit Managed by this driver
502 * PCI 32-bit Managed by this driver
503 * AGP 48-bit Managed by hooks in the /dev/agpgart driver
504 *
505 * All of the above can optionally be remapped through the GART. The following
506 * table lists the combinations of addressing types and GART remapping that
507 * is currently supported by the driver (h/w supports all, s/w limits this):
508 *
509 * PCI64 PCI32 AGP48
510 * GART no yes yes
511 * Direct yes yes no
512 *
513 * GART remapping of PCI64 is not done because there is no need to. The
514 * 64 bit PCI address holds all of the information necessary to target any
515 * memory in the system.
516 *
517 * AGP48 is always mapped through the GART. Management of the AGP48 portion
518 * of the aperature is the responsibility of code in the agpgart_be driver.
519 *
520 * The non-64 bit bus address space will currently be partitioned like this:
521 *
522 * 0xffff_ffff_ffff +--------
523 * | AGP48 direct
524 * | Space managed by this driver
525 * CA_AGP_DIRECT_BASE +--------
526 * | AGP GART mapped (gfx aperature)
527 * | Space managed by /dev/agpgart driver
528 * | This range is exposed to the agpgart
529 * | driver as the "graphics aperature"
530 * CA_AGP_MAPPED_BASE +-----
531 * | PCI GART mapped
532 * | Space managed by this driver
533 * CA_PCI32_MAPPED_BASE +----
534 * | PCI32 direct
535 * | Space managed by this driver
536 * 0xC000_0000 +--------
537 * (CA_PCI32_DIRECT_BASE)
538 *
539 * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
540 * is what we call the CA aperature. Addresses falling in this range will
541 * be remapped using the GART.
542 *
543 * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
544 * is what we call the graphics aperature. This is a subset of the CA
545 * aperature and is under the control of the agpgart_be driver.
546 *
547 * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
548 * somewhat arbitrary values. The known constraints on choosing these is:
549 *
550 * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
551 * must be one of the values supported by the ca_gart_aperature register.
552 * Currently valid values are: 4MB through 4096MB in powers of 2 increments
553 *
554 * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
555 * must be in MB units since that's what the agpgart driver assumes.
556 */
557
558/*
559 * Define Bus DMA ranges. These are configurable (see constraints above)
560 * and will probably need tuning based on experience.
561 */
562
563
564/*
565 * 11/24/03
566 * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
567 * generally unusable. The problem is that for PCI direct 32
568 * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
569 * of the coretalk address, and coretalk bits 38:32 come from a register.
570 * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
571 * for DMA (the rest is allocated to PIO), host node addresses need to be
572 * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
573 * as well. So there can be no PCI32 direct DMA below 3GB!! For this
574 * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
575 * tioca_dma_direct32() a noop but preserves the code flow should this issue
576 * be fixed in a respin.
577 *
578 * For now, all PCI32 DMA's must be mapped through the GART.
579 */
580
581#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
582#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
583
584#define CA_PCI32_MAPPED_BASE 0xC0000000UL
585#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
586
587#define CA_AGP_MAPPED_BASE 0x80000000UL
588#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
589
590#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
591#define CA_AGP_DIRECT_SIZE 0x40000000UL
592
593#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
594#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
595
596#endif /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/arch/ia64/include/asm/sn/tioca_provider.h b/arch/ia64/include/asm/sn/tioca_provider.h
new file mode 100644
index 000000000000..9a820ac61be3
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioca_provider.h
@@ -0,0 +1,207 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
10#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
11
12#include <asm/sn/tioca.h>
13
14/*
15 * WAR enables
16 * Defines for individual WARs. Each is a bitmask of applicable
17 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
18 * (3 << 1) == (rev A or rev B), etc
19 */
20
21#define TIOCA_WAR_ENABLED(pv, tioca_common) \
22 ((1 << tioca_common->ca_rev) & pv)
23
24 /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
25#define PV907908 (1 << 1)
26 /* ATI config space problems after BIOS execution starts */
27#define PV908234 (1 << 1)
28 /* CA:AGPDMA write request data mismatch with ABC1CL merge */
29#define PV895469 (1 << 1)
30 /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/
31#define PV910244 (1 << 1)
32
33struct tioca_dmamap{
34 struct list_head cad_list; /* headed by ca_list */
35
36 dma_addr_t cad_dma_addr; /* Linux dma handle */
37 uint cad_gart_entry; /* start entry in ca_gart_pagemap */
38 uint cad_gart_size; /* #entries for this map */
39};
40
41/*
42 * Kernel only fields. Prom may look at this stuff for debugging only.
43 * Access this structure through the ca_kernel_private ptr.
44 */
45
46struct tioca_common ;
47
48struct tioca_kernel {
49 struct tioca_common *ca_common; /* tioca this belongs to */
50 struct list_head ca_list; /* list of all ca's */
51 struct list_head ca_dmamaps;
52 spinlock_t ca_lock; /* Kernel lock */
53 cnodeid_t ca_closest_node;
54 struct list_head *ca_devices; /* bus->devices */
55
56 /*
57 * General GART stuff
58 */
59 u64 ca_ap_size; /* size of aperature in bytes */
60 u32 ca_gart_entries; /* # u64 entries in gart */
61 u32 ca_ap_pagesize; /* aperature page size in bytes */
62 u64 ca_ap_bus_base; /* bus address of CA aperature */
63 u64 ca_gart_size; /* gart size in bytes */
64 u64 *ca_gart; /* gart table vaddr */
65 u64 ca_gart_coretalk_addr; /* gart coretalk addr */
66 u8 ca_gart_iscoherent; /* used in tioca_tlbflush */
67
68 /* PCI GART convenience values */
69 u64 ca_pciap_base; /* pci aperature bus base address */
70 u64 ca_pciap_size; /* pci aperature size (bytes) */
71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 u64 *ca_pcigart; /* gfx GART vm address */
73 u32 ca_pcigart_entries;
74 u32 ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap;
76
77 /* AGP GART convenience values */
78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 u64 *ca_gfxgart; /* gfx GART vm address */
82 u32 ca_gfxgart_entries;
83 u32 ca_gfxgart_start; /* agpgart start index in ca_gart */
84};
85
86/*
87 * Common tioca info shared between kernel and prom
88 *
89 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
90 * TO THE PROM VERSION.
91 */
92
93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */
95
96 u32 ca_rev;
97 u32 ca_closest_nasid;
98
99 u64 ca_prom_private;
100 u64 ca_kernel_private;
101};
102
103/**
104 * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
105 * @paddr: page address to convert
106 *
107 * Convert a system [coretalk] address to a GART entry. GART entries are
108 * formed using the following:
109 *
110 * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
111 * (REMAP_SYS_ADDR) ) >> 12 )
112 *
113 * DATA written to 1 GART TABLE Entry in system memory is remapped system
114 * addr for 1 page
115 *
116 * The data is for coretalk address format right shifted 12 bits with a
117 * valid bit.
118 *
119 * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
120 * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
121 * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
122 * GART_TABLE_ENTRY [ 63 ] -- Valid Bit
123 */
124static inline u64
125tioca_paddr_to_gart(unsigned long paddr)
126{
127 /*
128 * We are assuming right now that paddr already has the correct
129 * format since the address from xtalk_dmaXXX should already have
130 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
131 */
132
133 return ((paddr) >> 12) | (1UL << 63);
134}
135
136/**
137 * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
138 * @page_addr: system page address to map
139 */
140
141static inline unsigned long
142tioca_physpage_to_gart(u64 page_addr)
143{
144 u64 coretalk_addr;
145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) {
148 return 0;
149 }
150
151 return tioca_paddr_to_gart(coretalk_addr);
152}
153
154/**
155 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
156 * @tioca_kernel: CA context
157 *
158 * Invalidate tlb entries for a given CA GART. Main complexity is to account
159 * for revA bug.
160 */
161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{
164 volatile u64 tmp;
165 volatile struct tioca __iomem *ca_base;
166 struct tioca_common *tioca_common;
167
168 tioca_common = tioca_kernel->ca_common;
169 ca_base = (struct tioca __iomem *)tioca_common->ca_common.bs_base;
170
171 /*
172 * Explicit flushes not needed if GART is in cached mode
173 */
174 if (tioca_kernel->ca_gart_iscoherent) {
175 if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
176 /*
177 * PV910244: RevA CA needs explicit flushes.
178 * Need to put GART into uncached mode before
179 * flushing otherwise the explicit flush is ignored.
180 *
181 * Alternate WAR would be to leave GART cached and
182 * touch every CL aligned GART entry.
183 */
184
185 __sn_clrq_relaxed(&ca_base->ca_control2, CA_GART_MEM_PARAM);
186 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
187 __sn_setq_relaxed(&ca_base->ca_control2,
188 (0x2ull << CA_GART_MEM_PARAM_SHFT));
189 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
190 }
191
192 return;
193 }
194
195 /*
196 * Gart in uncached mode ... need an explicit flush.
197 */
198
199 __sn_setq_relaxed(&ca_base->ca_control2, CA_GART_FLUSH_TLB);
200 tmp = __sn_readq_relaxed(&ca_base->ca_control2);
201}
202
203extern u32 tioca_gart_found;
204extern struct list_head tioca_list;
205extern int tioca_init_provider(void);
206extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
207#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tioce.h b/arch/ia64/include/asm/sn/tioce.h
new file mode 100644
index 000000000000..893468e1b41b
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioce.h
@@ -0,0 +1,760 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef __ASM_IA64_SN_TIOCE_H__
10#define __ASM_IA64_SN_TIOCE_H__
11
12/* CE ASIC part & mfgr information */
13#define TIOCE_PART_NUM 0xCE00
14#define TIOCE_SRC_ID 0x01
15#define TIOCE_REV_A 0x1
16
17/* CE Virtual PPB Vendor/Device IDs */
18#define CE_VIRT_PPB_VENDOR_ID 0x10a9
19#define CE_VIRT_PPB_DEVICE_ID 0x4002
20
21/* CE Host Bridge Vendor/Device IDs */
22#define CE_HOST_BRIDGE_VENDOR_ID 0x10a9
23#define CE_HOST_BRIDGE_DEVICE_ID 0x4001
24
25
26#define TIOCE_NUM_M40_ATES 4096
27#define TIOCE_NUM_M3240_ATES 2048
28#define TIOCE_NUM_PORTS 2
29
30/*
31 * Register layout for TIOCE. MMR offsets are shown at the far right of the
32 * structure definition.
33 */
34typedef volatile struct tioce {
35 /*
36 * ADMIN : Administration Registers
37 */
38 u64 ce_adm_id; /* 0x000000 */
39 u64 ce_pad_000008; /* 0x000008 */
40 u64 ce_adm_dyn_credit_status; /* 0x000010 */
41 u64 ce_adm_last_credit_status; /* 0x000018 */
42 u64 ce_adm_credit_limit; /* 0x000020 */
43 u64 ce_adm_force_credit; /* 0x000028 */
44 u64 ce_adm_control; /* 0x000030 */
45 u64 ce_adm_mmr_chn_timeout; /* 0x000038 */
46 u64 ce_adm_ssp_ure_timeout; /* 0x000040 */
47 u64 ce_adm_ssp_dre_timeout; /* 0x000048 */
48 u64 ce_adm_ssp_debug_sel; /* 0x000050 */
49 u64 ce_adm_int_status; /* 0x000058 */
50 u64 ce_adm_int_status_alias; /* 0x000060 */
51 u64 ce_adm_int_mask; /* 0x000068 */
52 u64 ce_adm_int_pending; /* 0x000070 */
53 u64 ce_adm_force_int; /* 0x000078 */
54 u64 ce_adm_ure_ups_buf_barrier_flush; /* 0x000080 */
55 u64 ce_adm_int_dest[15]; /* 0x000088 -- 0x0000F8 */
56 u64 ce_adm_error_summary; /* 0x000100 */
57 u64 ce_adm_error_summary_alias; /* 0x000108 */
58 u64 ce_adm_error_mask; /* 0x000110 */
59 u64 ce_adm_first_error; /* 0x000118 */
60 u64 ce_adm_error_overflow; /* 0x000120 */
61 u64 ce_adm_error_overflow_alias; /* 0x000128 */
62 u64 ce_pad_000130[2]; /* 0x000130 -- 0x000138 */
63 u64 ce_adm_tnum_error; /* 0x000140 */
64 u64 ce_adm_mmr_err_detail; /* 0x000148 */
65 u64 ce_adm_msg_sram_perr_detail; /* 0x000150 */
66 u64 ce_adm_bap_sram_perr_detail; /* 0x000158 */
67 u64 ce_adm_ce_sram_perr_detail; /* 0x000160 */
68 u64 ce_adm_ce_credit_oflow_detail; /* 0x000168 */
69 u64 ce_adm_tx_link_idle_max_timer; /* 0x000170 */
70 u64 ce_adm_pcie_debug_sel; /* 0x000178 */
71 u64 ce_pad_000180[16]; /* 0x000180 -- 0x0001F8 */
72
73 u64 ce_adm_pcie_debug_sel_top; /* 0x000200 */
74 u64 ce_adm_pcie_debug_lat_sel_lo_top; /* 0x000208 */
75 u64 ce_adm_pcie_debug_lat_sel_hi_top; /* 0x000210 */
76 u64 ce_adm_pcie_debug_trig_sel_top; /* 0x000218 */
77 u64 ce_adm_pcie_debug_trig_lat_sel_lo_top; /* 0x000220 */
78 u64 ce_adm_pcie_debug_trig_lat_sel_hi_top; /* 0x000228 */
79 u64 ce_adm_pcie_trig_compare_top; /* 0x000230 */
80 u64 ce_adm_pcie_trig_compare_en_top; /* 0x000238 */
81 u64 ce_adm_ssp_debug_sel_top; /* 0x000240 */
82 u64 ce_adm_ssp_debug_lat_sel_lo_top; /* 0x000248 */
83 u64 ce_adm_ssp_debug_lat_sel_hi_top; /* 0x000250 */
84 u64 ce_adm_ssp_debug_trig_sel_top; /* 0x000258 */
85 u64 ce_adm_ssp_debug_trig_lat_sel_lo_top; /* 0x000260 */
86 u64 ce_adm_ssp_debug_trig_lat_sel_hi_top; /* 0x000268 */
87 u64 ce_adm_ssp_trig_compare_top; /* 0x000270 */
88 u64 ce_adm_ssp_trig_compare_en_top; /* 0x000278 */
89 u64 ce_pad_000280[48]; /* 0x000280 -- 0x0003F8 */
90
91 u64 ce_adm_bap_ctrl; /* 0x000400 */
92 u64 ce_pad_000408[127]; /* 0x000408 -- 0x0007F8 */
93
94 u64 ce_msg_buf_data63_0[35]; /* 0x000800 -- 0x000918 */
95 u64 ce_pad_000920[29]; /* 0x000920 -- 0x0009F8 */
96
97 u64 ce_msg_buf_data127_64[35]; /* 0x000A00 -- 0x000B18 */
98 u64 ce_pad_000B20[29]; /* 0x000B20 -- 0x000BF8 */
99
100 u64 ce_msg_buf_parity[35]; /* 0x000C00 -- 0x000D18 */
101 u64 ce_pad_000D20[29]; /* 0x000D20 -- 0x000DF8 */
102
103 u64 ce_pad_000E00[576]; /* 0x000E00 -- 0x001FF8 */
104
105 /*
106 * LSI : LSI's PCI Express Link Registers (Link#1 and Link#2)
107 * Link#1 MMRs at start at 0x002000, Link#2 MMRs at 0x003000
108 * NOTE: the comment offsets at far right: let 'z' = {2 or 3}
109 */
110 #define ce_lsi(link_num) ce_lsi[link_num-1]
111 struct ce_lsi_reg {
112 u64 ce_lsi_lpu_id; /* 0x00z000 */
113 u64 ce_lsi_rst; /* 0x00z008 */
114 u64 ce_lsi_dbg_stat; /* 0x00z010 */
115 u64 ce_lsi_dbg_cfg; /* 0x00z018 */
116 u64 ce_lsi_ltssm_ctrl; /* 0x00z020 */
117 u64 ce_lsi_lk_stat; /* 0x00z028 */
118 u64 ce_pad_00z030[2]; /* 0x00z030 -- 0x00z038 */
119 u64 ce_lsi_int_and_stat; /* 0x00z040 */
120 u64 ce_lsi_int_mask; /* 0x00z048 */
121 u64 ce_pad_00z050[22]; /* 0x00z050 -- 0x00z0F8 */
122 u64 ce_lsi_lk_perf_cnt_sel; /* 0x00z100 */
123 u64 ce_pad_00z108; /* 0x00z108 */
124 u64 ce_lsi_lk_perf_cnt_ctrl; /* 0x00z110 */
125 u64 ce_pad_00z118; /* 0x00z118 */
126 u64 ce_lsi_lk_perf_cnt1; /* 0x00z120 */
127 u64 ce_lsi_lk_perf_cnt1_test; /* 0x00z128 */
128 u64 ce_lsi_lk_perf_cnt2; /* 0x00z130 */
129 u64 ce_lsi_lk_perf_cnt2_test; /* 0x00z138 */
130 u64 ce_pad_00z140[24]; /* 0x00z140 -- 0x00z1F8 */
131 u64 ce_lsi_lk_lyr_cfg; /* 0x00z200 */
132 u64 ce_lsi_lk_lyr_status; /* 0x00z208 */
133 u64 ce_lsi_lk_lyr_int_stat; /* 0x00z210 */
134 u64 ce_lsi_lk_ly_int_stat_test; /* 0x00z218 */
135 u64 ce_lsi_lk_ly_int_stat_mask; /* 0x00z220 */
136 u64 ce_pad_00z228[3]; /* 0x00z228 -- 0x00z238 */
137 u64 ce_lsi_fc_upd_ctl; /* 0x00z240 */
138 u64 ce_pad_00z248[3]; /* 0x00z248 -- 0x00z258 */
139 u64 ce_lsi_flw_ctl_upd_to_timer; /* 0x00z260 */
140 u64 ce_lsi_flw_ctl_upd_timer0; /* 0x00z268 */
141 u64 ce_lsi_flw_ctl_upd_timer1; /* 0x00z270 */
142 u64 ce_pad_00z278[49]; /* 0x00z278 -- 0x00z3F8 */
143 u64 ce_lsi_freq_nak_lat_thrsh; /* 0x00z400 */
144 u64 ce_lsi_ack_nak_lat_tmr; /* 0x00z408 */
145 u64 ce_lsi_rply_tmr_thr; /* 0x00z410 */
146 u64 ce_lsi_rply_tmr; /* 0x00z418 */
147 u64 ce_lsi_rply_num_stat; /* 0x00z420 */
148 u64 ce_lsi_rty_buf_max_addr; /* 0x00z428 */
149 u64 ce_lsi_rty_fifo_ptr; /* 0x00z430 */
150 u64 ce_lsi_rty_fifo_rd_wr_ptr; /* 0x00z438 */
151 u64 ce_lsi_rty_fifo_cred; /* 0x00z440 */
152 u64 ce_lsi_seq_cnt; /* 0x00z448 */
153 u64 ce_lsi_ack_sent_seq_num; /* 0x00z450 */
154 u64 ce_lsi_seq_cnt_fifo_max_addr; /* 0x00z458 */
155 u64 ce_lsi_seq_cnt_fifo_ptr; /* 0x00z460 */
156 u64 ce_lsi_seq_cnt_rd_wr_ptr; /* 0x00z468 */
157 u64 ce_lsi_tx_lk_ts_ctl; /* 0x00z470 */
158 u64 ce_pad_00z478; /* 0x00z478 */
159 u64 ce_lsi_mem_addr_ctl; /* 0x00z480 */
160 u64 ce_lsi_mem_d_ld0; /* 0x00z488 */
161 u64 ce_lsi_mem_d_ld1; /* 0x00z490 */
162 u64 ce_lsi_mem_d_ld2; /* 0x00z498 */
163 u64 ce_lsi_mem_d_ld3; /* 0x00z4A0 */
164 u64 ce_lsi_mem_d_ld4; /* 0x00z4A8 */
165 u64 ce_pad_00z4B0[2]; /* 0x00z4B0 -- 0x00z4B8 */
166 u64 ce_lsi_rty_d_cnt; /* 0x00z4C0 */
167 u64 ce_lsi_seq_buf_cnt; /* 0x00z4C8 */
168 u64 ce_lsi_seq_buf_bt_d; /* 0x00z4D0 */
169 u64 ce_pad_00z4D8; /* 0x00z4D8 */
170 u64 ce_lsi_ack_lat_thr; /* 0x00z4E0 */
171 u64 ce_pad_00z4E8[3]; /* 0x00z4E8 -- 0x00z4F8 */
172 u64 ce_lsi_nxt_rcv_seq_1_cntr; /* 0x00z500 */
173 u64 ce_lsi_unsp_dllp_rcvd; /* 0x00z508 */
174 u64 ce_lsi_rcv_lk_ts_ctl; /* 0x00z510 */
175 u64 ce_pad_00z518[29]; /* 0x00z518 -- 0x00z5F8 */
176 u64 ce_lsi_phy_lyr_cfg; /* 0x00z600 */
177 u64 ce_pad_00z608; /* 0x00z608 */
178 u64 ce_lsi_phy_lyr_int_stat; /* 0x00z610 */
179 u64 ce_lsi_phy_lyr_int_stat_test; /* 0x00z618 */
180 u64 ce_lsi_phy_lyr_int_mask; /* 0x00z620 */
181 u64 ce_pad_00z628[11]; /* 0x00z628 -- 0x00z678 */
182 u64 ce_lsi_rcv_phy_cfg; /* 0x00z680 */
183 u64 ce_lsi_rcv_phy_stat1; /* 0x00z688 */
184 u64 ce_lsi_rcv_phy_stat2; /* 0x00z690 */
185 u64 ce_lsi_rcv_phy_stat3; /* 0x00z698 */
186 u64 ce_lsi_rcv_phy_int_stat; /* 0x00z6A0 */
187 u64 ce_lsi_rcv_phy_int_stat_test; /* 0x00z6A8 */
188 u64 ce_lsi_rcv_phy_int_mask; /* 0x00z6B0 */
189 u64 ce_pad_00z6B8[9]; /* 0x00z6B8 -- 0x00z6F8 */
190 u64 ce_lsi_tx_phy_cfg; /* 0x00z700 */
191 u64 ce_lsi_tx_phy_stat; /* 0x00z708 */
192 u64 ce_lsi_tx_phy_int_stat; /* 0x00z710 */
193 u64 ce_lsi_tx_phy_int_stat_test; /* 0x00z718 */
194 u64 ce_lsi_tx_phy_int_mask; /* 0x00z720 */
195 u64 ce_lsi_tx_phy_stat2; /* 0x00z728 */
196 u64 ce_pad_00z730[10]; /* 0x00z730 -- 0x00z77F */
197 u64 ce_lsi_ltssm_cfg1; /* 0x00z780 */
198 u64 ce_lsi_ltssm_cfg2; /* 0x00z788 */
199 u64 ce_lsi_ltssm_cfg3; /* 0x00z790 */
200 u64 ce_lsi_ltssm_cfg4; /* 0x00z798 */
201 u64 ce_lsi_ltssm_cfg5; /* 0x00z7A0 */
202 u64 ce_lsi_ltssm_stat1; /* 0x00z7A8 */
203 u64 ce_lsi_ltssm_stat2; /* 0x00z7B0 */
204 u64 ce_lsi_ltssm_int_stat; /* 0x00z7B8 */
205 u64 ce_lsi_ltssm_int_stat_test; /* 0x00z7C0 */
206 u64 ce_lsi_ltssm_int_mask; /* 0x00z7C8 */
207 u64 ce_lsi_ltssm_stat_wr_en; /* 0x00z7D0 */
208 u64 ce_pad_00z7D8[5]; /* 0x00z7D8 -- 0x00z7F8 */
209 u64 ce_lsi_gb_cfg1; /* 0x00z800 */
210 u64 ce_lsi_gb_cfg2; /* 0x00z808 */
211 u64 ce_lsi_gb_cfg3; /* 0x00z810 */
212 u64 ce_lsi_gb_cfg4; /* 0x00z818 */
213 u64 ce_lsi_gb_stat; /* 0x00z820 */
214 u64 ce_lsi_gb_int_stat; /* 0x00z828 */
215 u64 ce_lsi_gb_int_stat_test; /* 0x00z830 */
216 u64 ce_lsi_gb_int_mask; /* 0x00z838 */
217 u64 ce_lsi_gb_pwr_dn1; /* 0x00z840 */
218 u64 ce_lsi_gb_pwr_dn2; /* 0x00z848 */
219 u64 ce_pad_00z850[246]; /* 0x00z850 -- 0x00zFF8 */
220 } ce_lsi[2];
221
222 u64 ce_pad_004000[10]; /* 0x004000 -- 0x004048 */
223
224 /*
225 * CRM: Coretalk Receive Module Registers
226 */
227 u64 ce_crm_debug_mux; /* 0x004050 */
228 u64 ce_pad_004058; /* 0x004058 */
229 u64 ce_crm_ssp_err_cmd_wrd; /* 0x004060 */
230 u64 ce_crm_ssp_err_addr; /* 0x004068 */
231 u64 ce_crm_ssp_err_syn; /* 0x004070 */
232
233 u64 ce_pad_004078[499]; /* 0x004078 -- 0x005008 */
234
235 /*
236 * CXM: Coretalk Xmit Module Registers
237 */
238 u64 ce_cxm_dyn_credit_status; /* 0x005010 */
239 u64 ce_cxm_last_credit_status; /* 0x005018 */
240 u64 ce_cxm_credit_limit; /* 0x005020 */
241 u64 ce_cxm_force_credit; /* 0x005028 */
242 u64 ce_cxm_disable_bypass; /* 0x005030 */
243 u64 ce_pad_005038[3]; /* 0x005038 -- 0x005048 */
244 u64 ce_cxm_debug_mux; /* 0x005050 */
245
246 u64 ce_pad_005058[501]; /* 0x005058 -- 0x005FF8 */
247
248 /*
249 * DTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
250 * DTL: Link#1 MMRs at start at 0x006000, Link#2 MMRs at 0x008000
251 * DTL: the comment offsets at far right: let 'y' = {6 or 8}
252 *
253 * UTL: Downstream Transaction Layer Regs (Link#1 and Link#2)
254 * UTL: Link#1 MMRs at start at 0x007000, Link#2 MMRs at 0x009000
255 * UTL: the comment offsets at far right: let 'z' = {7 or 9}
256 */
257 #define ce_dtl(link_num) ce_dtl_utl[link_num-1]
258 #define ce_utl(link_num) ce_dtl_utl[link_num-1]
259 struct ce_dtl_utl_reg {
260 /* DTL */
261 u64 ce_dtl_dtdr_credit_limit; /* 0x00y000 */
262 u64 ce_dtl_dtdr_credit_force; /* 0x00y008 */
263 u64 ce_dtl_dyn_credit_status; /* 0x00y010 */
264 u64 ce_dtl_dtl_last_credit_stat; /* 0x00y018 */
265 u64 ce_dtl_dtl_ctrl; /* 0x00y020 */
266 u64 ce_pad_00y028[5]; /* 0x00y028 -- 0x00y048 */
267 u64 ce_dtl_debug_sel; /* 0x00y050 */
268 u64 ce_pad_00y058[501]; /* 0x00y058 -- 0x00yFF8 */
269
270 /* UTL */
271 u64 ce_utl_utl_ctrl; /* 0x00z000 */
272 u64 ce_utl_debug_sel; /* 0x00z008 */
273 u64 ce_pad_00z010[510]; /* 0x00z010 -- 0x00zFF8 */
274 } ce_dtl_utl[2];
275
276 u64 ce_pad_00A000[514]; /* 0x00A000 -- 0x00B008 */
277
278 /*
279 * URE: Upstream Request Engine
280 */
281 u64 ce_ure_dyn_credit_status; /* 0x00B010 */
282 u64 ce_ure_last_credit_status; /* 0x00B018 */
283 u64 ce_ure_credit_limit; /* 0x00B020 */
284 u64 ce_pad_00B028; /* 0x00B028 */
285 u64 ce_ure_control; /* 0x00B030 */
286 u64 ce_ure_status; /* 0x00B038 */
287 u64 ce_pad_00B040[2]; /* 0x00B040 -- 0x00B048 */
288 u64 ce_ure_debug_sel; /* 0x00B050 */
289 u64 ce_ure_pcie_debug_sel; /* 0x00B058 */
290 u64 ce_ure_ssp_err_cmd_wrd; /* 0x00B060 */
291 u64 ce_ure_ssp_err_addr; /* 0x00B068 */
292 u64 ce_ure_page_map; /* 0x00B070 */
293 u64 ce_ure_dir_map[TIOCE_NUM_PORTS]; /* 0x00B078 */
294 u64 ce_ure_pipe_sel1; /* 0x00B088 */
295 u64 ce_ure_pipe_mask1; /* 0x00B090 */
296 u64 ce_ure_pipe_sel2; /* 0x00B098 */
297 u64 ce_ure_pipe_mask2; /* 0x00B0A0 */
298 u64 ce_ure_pcie1_credits_sent; /* 0x00B0A8 */
299 u64 ce_ure_pcie1_credits_used; /* 0x00B0B0 */
300 u64 ce_ure_pcie1_credit_limit; /* 0x00B0B8 */
301 u64 ce_ure_pcie2_credits_sent; /* 0x00B0C0 */
302 u64 ce_ure_pcie2_credits_used; /* 0x00B0C8 */
303 u64 ce_ure_pcie2_credit_limit; /* 0x00B0D0 */
304 u64 ce_ure_pcie_force_credit; /* 0x00B0D8 */
305 u64 ce_ure_rd_tnum_val; /* 0x00B0E0 */
306 u64 ce_ure_rd_tnum_rsp_rcvd; /* 0x00B0E8 */
307 u64 ce_ure_rd_tnum_esent_timer; /* 0x00B0F0 */
308 u64 ce_ure_rd_tnum_error; /* 0x00B0F8 */
309 u64 ce_ure_rd_tnum_first_cl; /* 0x00B100 */
310 u64 ce_ure_rd_tnum_link_buf; /* 0x00B108 */
311 u64 ce_ure_wr_tnum_val; /* 0x00B110 */
312 u64 ce_ure_sram_err_addr0; /* 0x00B118 */
313 u64 ce_ure_sram_err_addr1; /* 0x00B120 */
314 u64 ce_ure_sram_err_addr2; /* 0x00B128 */
315 u64 ce_ure_sram_rd_addr0; /* 0x00B130 */
316 u64 ce_ure_sram_rd_addr1; /* 0x00B138 */
317 u64 ce_ure_sram_rd_addr2; /* 0x00B140 */
318 u64 ce_ure_sram_wr_addr0; /* 0x00B148 */
319 u64 ce_ure_sram_wr_addr1; /* 0x00B150 */
320 u64 ce_ure_sram_wr_addr2; /* 0x00B158 */
321 u64 ce_ure_buf_flush10; /* 0x00B160 */
322 u64 ce_ure_buf_flush11; /* 0x00B168 */
323 u64 ce_ure_buf_flush12; /* 0x00B170 */
324 u64 ce_ure_buf_flush13; /* 0x00B178 */
325 u64 ce_ure_buf_flush20; /* 0x00B180 */
326 u64 ce_ure_buf_flush21; /* 0x00B188 */
327 u64 ce_ure_buf_flush22; /* 0x00B190 */
328 u64 ce_ure_buf_flush23; /* 0x00B198 */
329 u64 ce_ure_pcie_control1; /* 0x00B1A0 */
330 u64 ce_ure_pcie_control2; /* 0x00B1A8 */
331
332 u64 ce_pad_00B1B0[458]; /* 0x00B1B0 -- 0x00BFF8 */
333
334 /* Upstream Data Buffer, Port1 */
335 struct ce_ure_maint_ups_dat1_data {
336 u64 data63_0[512]; /* 0x00C000 -- 0x00CFF8 */
337 u64 data127_64[512]; /* 0x00D000 -- 0x00DFF8 */
338 u64 parity[512]; /* 0x00E000 -- 0x00EFF8 */
339 } ce_ure_maint_ups_dat1;
340
341 /* Upstream Header Buffer, Port1 */
342 struct ce_ure_maint_ups_hdr1_data {
343 u64 data63_0[512]; /* 0x00F000 -- 0x00FFF8 */
344 u64 data127_64[512]; /* 0x010000 -- 0x010FF8 */
345 u64 parity[512]; /* 0x011000 -- 0x011FF8 */
346 } ce_ure_maint_ups_hdr1;
347
348 /* Upstream Data Buffer, Port2 */
349 struct ce_ure_maint_ups_dat2_data {
350 u64 data63_0[512]; /* 0x012000 -- 0x012FF8 */
351 u64 data127_64[512]; /* 0x013000 -- 0x013FF8 */
352 u64 parity[512]; /* 0x014000 -- 0x014FF8 */
353 } ce_ure_maint_ups_dat2;
354
355 /* Upstream Header Buffer, Port2 */
356 struct ce_ure_maint_ups_hdr2_data {
357 u64 data63_0[512]; /* 0x015000 -- 0x015FF8 */
358 u64 data127_64[512]; /* 0x016000 -- 0x016FF8 */
359 u64 parity[512]; /* 0x017000 -- 0x017FF8 */
360 } ce_ure_maint_ups_hdr2;
361
362 /* Downstream Data Buffer */
363 struct ce_ure_maint_dns_dat_data {
364 u64 data63_0[512]; /* 0x018000 -- 0x018FF8 */
365 u64 data127_64[512]; /* 0x019000 -- 0x019FF8 */
366 u64 parity[512]; /* 0x01A000 -- 0x01AFF8 */
367 } ce_ure_maint_dns_dat;
368
369 /* Downstream Header Buffer */
370 struct ce_ure_maint_dns_hdr_data {
371 u64 data31_0[64]; /* 0x01B000 -- 0x01B1F8 */
372 u64 data95_32[64]; /* 0x01B200 -- 0x01B3F8 */
373 u64 parity[64]; /* 0x01B400 -- 0x01B5F8 */
374 } ce_ure_maint_dns_hdr;
375
376 /* RCI Buffer Data */
377 struct ce_ure_maint_rci_data {
378 u64 data41_0[64]; /* 0x01B600 -- 0x01B7F8 */
379 u64 data69_42[64]; /* 0x01B800 -- 0x01B9F8 */
380 } ce_ure_maint_rci;
381
382 /* Response Queue */
383 u64 ce_ure_maint_rspq[64]; /* 0x01BA00 -- 0x01BBF8 */
384
385 u64 ce_pad_01C000[4224]; /* 0x01BC00 -- 0x023FF8 */
386
387 /* Admin Build-a-Packet Buffer */
388 struct ce_adm_maint_bap_buf_data {
389 u64 data63_0[258]; /* 0x024000 -- 0x024808 */
390 u64 data127_64[258]; /* 0x024810 -- 0x025018 */
391 u64 parity[258]; /* 0x025020 -- 0x025828 */
392 } ce_adm_maint_bap_buf;
393
394 u64 ce_pad_025830[5370]; /* 0x025830 -- 0x02FFF8 */
395
396 /* URE: 40bit PMU ATE Buffer */ /* 0x030000 -- 0x037FF8 */
397 u64 ce_ure_ate40[TIOCE_NUM_M40_ATES];
398
399 /* URE: 32/40bit PMU ATE Buffer */ /* 0x038000 -- 0x03BFF8 */
400 u64 ce_ure_ate3240[TIOCE_NUM_M3240_ATES];
401
402 u64 ce_pad_03C000[2050]; /* 0x03C000 -- 0x040008 */
403
404 /*
405 * DRE: Down Stream Request Engine
406 */
407 u64 ce_dre_dyn_credit_status1; /* 0x040010 */
408 u64 ce_dre_dyn_credit_status2; /* 0x040018 */
409 u64 ce_dre_last_credit_status1; /* 0x040020 */
410 u64 ce_dre_last_credit_status2; /* 0x040028 */
411 u64 ce_dre_credit_limit1; /* 0x040030 */
412 u64 ce_dre_credit_limit2; /* 0x040038 */
413 u64 ce_dre_force_credit1; /* 0x040040 */
414 u64 ce_dre_force_credit2; /* 0x040048 */
415 u64 ce_dre_debug_mux1; /* 0x040050 */
416 u64 ce_dre_debug_mux2; /* 0x040058 */
417 u64 ce_dre_ssp_err_cmd_wrd; /* 0x040060 */
418 u64 ce_dre_ssp_err_addr; /* 0x040068 */
419 u64 ce_dre_comp_err_cmd_wrd; /* 0x040070 */
420 u64 ce_dre_comp_err_addr; /* 0x040078 */
421 u64 ce_dre_req_status; /* 0x040080 */
422 u64 ce_dre_config1; /* 0x040088 */
423 u64 ce_dre_config2; /* 0x040090 */
424 u64 ce_dre_config_req_status; /* 0x040098 */
425 u64 ce_pad_0400A0[12]; /* 0x0400A0 -- 0x0400F8 */
426 u64 ce_dre_dyn_fifo; /* 0x040100 */
427 u64 ce_pad_040108[3]; /* 0x040108 -- 0x040118 */
428 u64 ce_dre_last_fifo; /* 0x040120 */
429
430 u64 ce_pad_040128[27]; /* 0x040128 -- 0x0401F8 */
431
432 /* DRE Downstream Head Queue */
433 struct ce_dre_maint_ds_head_queue {
434 u64 data63_0[32]; /* 0x040200 -- 0x0402F8 */
435 u64 data127_64[32]; /* 0x040300 -- 0x0403F8 */
436 u64 parity[32]; /* 0x040400 -- 0x0404F8 */
437 } ce_dre_maint_ds_head_q;
438
439 u64 ce_pad_040500[352]; /* 0x040500 -- 0x040FF8 */
440
441 /* DRE Downstream Data Queue */
442 struct ce_dre_maint_ds_data_queue {
443 u64 data63_0[256]; /* 0x041000 -- 0x0417F8 */
444 u64 ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
445 u64 data127_64[256]; /* 0x042000 -- 0x0427F8 */
446 u64 ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
447 u64 parity[256]; /* 0x043000 -- 0x0437F8 */
448 u64 ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
449 } ce_dre_maint_ds_data_q;
450
451 /* DRE URE Upstream Response Queue */
452 struct ce_dre_maint_ure_us_rsp_queue {
453 u64 data63_0[8]; /* 0x044000 -- 0x044038 */
454 u64 ce_pad_044040[24]; /* 0x044040 -- 0x0440F8 */
455 u64 data127_64[8]; /* 0x044100 -- 0x044138 */
456 u64 ce_pad_044140[24]; /* 0x044140 -- 0x0441F8 */
457 u64 parity[8]; /* 0x044200 -- 0x044238 */
458 u64 ce_pad_044240[24]; /* 0x044240 -- 0x0442F8 */
459 } ce_dre_maint_ure_us_rsp_q;
460
461 u64 ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */
462
463 u64 ce_end_of_struct; /* 0x044400 */
464} tioce_t;
465
466/* ce_lsiX_gb_cfg1 register bit masks & shifts */
467#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
468#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
469#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
470#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8);
471#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
472#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
473#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
474#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
475#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
476#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
477#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
478#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
479#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
480#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
481#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
482#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
483#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
484#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)
485
486/* ce_adm_int_mask/ce_adm_int_status register bit defines */
487#define CE_ADM_INT_CE_ERROR_SHFT 0
488#define CE_ADM_INT_LSI1_IP_ERROR_SHFT 1
489#define CE_ADM_INT_LSI2_IP_ERROR_SHFT 2
490#define CE_ADM_INT_PCIE_ERROR_SHFT 3
491#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT 4
492#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT 5
493#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT 6
494#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT 7
495#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT 8
496#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT 9
497#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT 10
498#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT 11
499#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT 12
500#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT 13
501#define CE_ADM_INT_PCIE_MSG_SHFT 14 /*see int_dest_14*/
502#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT 14
503#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT 15
504#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT 16
505#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT 17
506#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT 22
507#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT 23
508
509/* ce_adm_force_int register bit defines */
510#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT 0
511#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT 1
512#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT 2
513#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT 3
514#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT 4
515#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT 5
516#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT 6
517#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT 7
518#define CE_ADM_FORCE_INT_ALWAYS_SHFT 8
519
520/* ce_adm_int_dest register bit masks & shifts */
521#define INTR_VECTOR_SHFT 56
522
523/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
524#define CE_ADM_ERR_CRM_SSP_REQ_INVALID (0x1ULL << 0)
525#define CE_ADM_ERR_SSP_REQ_HEADER (0x1ULL << 1)
526#define CE_ADM_ERR_SSP_RSP_HEADER (0x1ULL << 2)
527#define CE_ADM_ERR_SSP_PROTOCOL_ERROR (0x1ULL << 3)
528#define CE_ADM_ERR_SSP_SBE (0x1ULL << 4)
529#define CE_ADM_ERR_SSP_MBE (0x1ULL << 5)
530#define CE_ADM_ERR_CXM_CREDIT_OFLOW (0x1ULL << 6)
531#define CE_ADM_ERR_DRE_SSP_REQ_INVAL (0x1ULL << 7)
532#define CE_ADM_ERR_SSP_REQ_LONG (0x1ULL << 8)
533#define CE_ADM_ERR_SSP_REQ_OFLOW (0x1ULL << 9)
534#define CE_ADM_ERR_SSP_REQ_SHORT (0x1ULL << 10)
535#define CE_ADM_ERR_SSP_REQ_SIDEBAND (0x1ULL << 11)
536#define CE_ADM_ERR_SSP_REQ_ADDR_ERR (0x1ULL << 12)
537#define CE_ADM_ERR_SSP_REQ_BAD_BE (0x1ULL << 13)
538#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT (0x1ULL << 14)
539#define CE_ADM_ERR_PCIE_UNEXP_COMPL (0x1ULL << 15)
540#define CE_ADM_ERR_PCIE_ERR_COMPL (0x1ULL << 16)
541#define CE_ADM_ERR_DRE_CREDIT_OFLOW (0x1ULL << 17)
542#define CE_ADM_ERR_DRE_SRAM_PE (0x1ULL << 18)
543#define CE_ADM_ERR_SSP_RSP_INVALID (0x1ULL << 19)
544#define CE_ADM_ERR_SSP_RSP_LONG (0x1ULL << 20)
545#define CE_ADM_ERR_SSP_RSP_SHORT (0x1ULL << 21)
546#define CE_ADM_ERR_SSP_RSP_SIDEBAND (0x1ULL << 22)
547#define CE_ADM_ERR_URE_SSP_RSP_UNEXP (0x1ULL << 23)
548#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT (0x1ULL << 24)
549#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT (0x1ULL << 25)
550#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT (0x1ULL << 26)
551#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT (0x1ULL << 27)
552#define CE_ADM_ERR_URE_CREDIT_OFLOW (0x1ULL << 28)
553#define CE_ADM_ERR_URE_SRAM_PE (0x1ULL << 29)
554#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP (0x1ULL << 30)
555#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT (0x1ULL << 31)
556#define CE_ADM_ERR_MMR_ACCESS_ERROR (0x1ULL << 32)
557#define CE_ADM_ERR_MMR_ADDR_ERROR (0x1ULL << 33)
558#define CE_ADM_ERR_ADM_CREDIT_OFLOW (0x1ULL << 34)
559#define CE_ADM_ERR_ADM_SRAM_PE (0x1ULL << 35)
560#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR (0x1ULL << 36)
561#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 37)
562#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 38)
563#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 39)
564#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR (0x1ULL << 40)
565#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR (0x1ULL << 41)
566#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 42)
567#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 43)
568#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR (0x1ULL << 44)
569#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR (0x1ULL << 45)
570#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR (0x1ULL << 46)
571#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR (0x1ULL << 47)
572#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR (0x1ULL << 48)
573#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR (0x1ULL << 49)
574#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR (0x1ULL << 50)
575#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR (0x1ULL << 51)
576#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR (0x1ULL << 52)
577#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR (0x1ULL << 53)
578#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR (0x1ULL << 54)
579#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR (0x1ULL << 55)
580#define CE_ADM_ERR_PORT1_PCIE_COR_ERR (0x1ULL << 56)
581#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR (0x1ULL << 57)
582#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR (0x1ULL << 58)
583#define CE_ADM_ERR_PORT2_PCIE_COR_ERR (0x1ULL << 59)
584#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR (0x1ULL << 60)
585#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR (0x1ULL << 61)
586
587/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
588#define FLUSH_SEL_PORT1_PIPE0_SHFT 0
589#define FLUSH_SEL_PORT1_PIPE1_SHFT 4
590#define FLUSH_SEL_PORT1_PIPE2_SHFT 8
591#define FLUSH_SEL_PORT1_PIPE3_SHFT 12
592#define FLUSH_SEL_PORT2_PIPE0_SHFT 16
593#define FLUSH_SEL_PORT2_PIPE1_SHFT 20
594#define FLUSH_SEL_PORT2_PIPE2_SHFT 24
595#define FLUSH_SEL_PORT2_PIPE3_SHFT 28
596
597/* ce_dre_config1 register bit masks and shifts */
598#define CE_DRE_RO_ENABLE (0x1ULL << 0)
599#define CE_DRE_DYN_RO_ENABLE (0x1ULL << 1)
600#define CE_DRE_SUP_CONFIG_COMP_ERROR (0x1ULL << 2)
601#define CE_DRE_SUP_IO_COMP_ERROR (0x1ULL << 3)
602#define CE_DRE_ADDR_MODE_SHFT 4
603
604/* ce_dre_config_req_status register bit masks */
605#define CE_DRE_LAST_CONFIG_COMPLETION (0x7ULL << 0)
606#define CE_DRE_DOWNSTREAM_CONFIG_ERROR (0x1ULL << 3)
607#define CE_DRE_CONFIG_COMPLETION_VALID (0x1ULL << 4)
608#define CE_DRE_CONFIG_REQUEST_ACTIVE (0x1ULL << 5)
609
610/* ce_ure_control register bit masks & shifts */
611#define CE_URE_RD_MRG_ENABLE (0x1ULL << 0)
612#define CE_URE_WRT_MRG_ENABLE1 (0x1ULL << 4)
613#define CE_URE_WRT_MRG_ENABLE2 (0x1ULL << 5)
614#define CE_URE_WRT_MRG_TIMER_SHFT 12
615#define CE_URE_WRT_MRG_TIMER_MASK (0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
616#define CE_URE_WRT_MRG_TIMER(x) (((u64)(x) << \
617 CE_URE_WRT_MRG_TIMER_SHFT) & \
618 CE_URE_WRT_MRG_TIMER_MASK)
619#define CE_URE_RSPQ_BYPASS_DISABLE (0x1ULL << 24)
620#define CE_URE_UPS_DAT1_PAR_DISABLE (0x1ULL << 32)
621#define CE_URE_UPS_HDR1_PAR_DISABLE (0x1ULL << 33)
622#define CE_URE_UPS_DAT2_PAR_DISABLE (0x1ULL << 34)
623#define CE_URE_UPS_HDR2_PAR_DISABLE (0x1ULL << 35)
624#define CE_URE_ATE_PAR_DISABLE (0x1ULL << 36)
625#define CE_URE_RCI_PAR_DISABLE (0x1ULL << 37)
626#define CE_URE_RSPQ_PAR_DISABLE (0x1ULL << 38)
627#define CE_URE_DNS_DAT_PAR_DISABLE (0x1ULL << 39)
628#define CE_URE_DNS_HDR_PAR_DISABLE (0x1ULL << 40)
629#define CE_URE_MALFORM_DISABLE (0x1ULL << 44)
630#define CE_URE_UNSUP_DISABLE (0x1ULL << 45)
631
632/* ce_ure_page_map register bit masks & shifts */
633#define CE_URE_ATE3240_ENABLE (0x1ULL << 0)
634#define CE_URE_ATE40_ENABLE (0x1ULL << 1)
635#define CE_URE_PAGESIZE_SHFT 4
636#define CE_URE_PAGESIZE_MASK (0x7ULL << CE_URE_PAGESIZE_SHFT)
637#define CE_URE_4K_PAGESIZE (0x0ULL << CE_URE_PAGESIZE_SHFT)
638#define CE_URE_16K_PAGESIZE (0x1ULL << CE_URE_PAGESIZE_SHFT)
639#define CE_URE_64K_PAGESIZE (0x2ULL << CE_URE_PAGESIZE_SHFT)
640#define CE_URE_128K_PAGESIZE (0x3ULL << CE_URE_PAGESIZE_SHFT)
641#define CE_URE_256K_PAGESIZE (0x4ULL << CE_URE_PAGESIZE_SHFT)
642
643/* ce_ure_pipe_sel register bit masks & shifts */
644#define PKT_TRAFIC_SHRT 16
645#define BUS_SRC_ID_SHFT 8
646#define DEV_SRC_ID_SHFT 3
647#define FNC_SRC_ID_SHFT 0
648#define CE_URE_TC_MASK (0x07ULL << PKT_TRAFIC_SHRT)
649#define CE_URE_BUS_MASK (0xFFULL << BUS_SRC_ID_SHFT)
650#define CE_URE_DEV_MASK (0x1FULL << DEV_SRC_ID_SHFT)
651#define CE_URE_FNC_MASK (0x07ULL << FNC_SRC_ID_SHFT)
652#define CE_URE_PIPE_BUS(b) (((u64)(b) << BUS_SRC_ID_SHFT) & \
653 CE_URE_BUS_MASK)
654#define CE_URE_PIPE_DEV(d) (((u64)(d) << DEV_SRC_ID_SHFT) & \
655 CE_URE_DEV_MASK)
656#define CE_URE_PIPE_FNC(f) (((u64)(f) << FNC_SRC_ID_SHFT) & \
657 CE_URE_FNC_MASK)
658
659#define CE_URE_SEL1_SHFT 0
660#define CE_URE_SEL2_SHFT 20
661#define CE_URE_SEL3_SHFT 40
662#define CE_URE_SEL1_MASK (0x7FFFFULL << CE_URE_SEL1_SHFT)
663#define CE_URE_SEL2_MASK (0x7FFFFULL << CE_URE_SEL2_SHFT)
664#define CE_URE_SEL3_MASK (0x7FFFFULL << CE_URE_SEL3_SHFT)
665
666
667/* ce_ure_pipe_mask register bit masks & shifts */
668#define CE_URE_MASK1_SHFT 0
669#define CE_URE_MASK2_SHFT 20
670#define CE_URE_MASK3_SHFT 40
671#define CE_URE_MASK1_MASK (0x7FFFFULL << CE_URE_MASK1_SHFT)
672#define CE_URE_MASK2_MASK (0x7FFFFULL << CE_URE_MASK2_SHFT)
673#define CE_URE_MASK3_MASK (0x7FFFFULL << CE_URE_MASK3_SHFT)
674
675
676/* ce_ure_pcie_control1 register bit masks & shifts */
677#define CE_URE_SI (0x1ULL << 0)
678#define CE_URE_ELAL_SHFT 4
679#define CE_URE_ELAL_MASK (0x7ULL << CE_URE_ELAL_SHFT)
680#define CE_URE_ELAL_SET(n) (((u64)(n) << CE_URE_ELAL_SHFT) & \
681 CE_URE_ELAL_MASK)
682#define CE_URE_ELAL1_SHFT 8
683#define CE_URE_ELAL1_MASK (0x7ULL << CE_URE_ELAL1_SHFT)
684#define CE_URE_ELAL1_SET(n) (((u64)(n) << CE_URE_ELAL1_SHFT) & \
685 CE_URE_ELAL1_MASK)
686#define CE_URE_SCC (0x1ULL << 12)
687#define CE_URE_PN1_SHFT 16
688#define CE_URE_PN1_MASK (0xFFULL << CE_URE_PN1_SHFT)
689#define CE_URE_PN2_SHFT 24
690#define CE_URE_PN2_MASK (0xFFULL << CE_URE_PN2_SHFT)
691#define CE_URE_PN1_SET(n) (((u64)(n) << CE_URE_PN1_SHFT) & \
692 CE_URE_PN1_MASK)
693#define CE_URE_PN2_SET(n) (((u64)(n) << CE_URE_PN2_SHFT) & \
694 CE_URE_PN2_MASK)
695
696/* ce_ure_pcie_control2 register bit masks & shifts */
697#define CE_URE_ABP (0x1ULL << 0)
698#define CE_URE_PCP (0x1ULL << 1)
699#define CE_URE_MSP (0x1ULL << 2)
700#define CE_URE_AIP (0x1ULL << 3)
701#define CE_URE_PIP (0x1ULL << 4)
702#define CE_URE_HPS (0x1ULL << 5)
703#define CE_URE_HPC (0x1ULL << 6)
704#define CE_URE_SPLV_SHFT 7
705#define CE_URE_SPLV_MASK (0xFFULL << CE_URE_SPLV_SHFT)
706#define CE_URE_SPLV_SET(n) (((u64)(n) << CE_URE_SPLV_SHFT) & \
707 CE_URE_SPLV_MASK)
708#define CE_URE_SPLS_SHFT 15
709#define CE_URE_SPLS_MASK (0x3ULL << CE_URE_SPLS_SHFT)
710#define CE_URE_SPLS_SET(n) (((u64)(n) << CE_URE_SPLS_SHFT) & \
711 CE_URE_SPLS_MASK)
712#define CE_URE_PSN1_SHFT 19
713#define CE_URE_PSN1_MASK (0x1FFFULL << CE_URE_PSN1_SHFT)
714#define CE_URE_PSN2_SHFT 32
715#define CE_URE_PSN2_MASK (0x1FFFULL << CE_URE_PSN2_SHFT)
716#define CE_URE_PSN1_SET(n) (((u64)(n) << CE_URE_PSN1_SHFT) & \
717 CE_URE_PSN1_MASK)
718#define CE_URE_PSN2_SET(n) (((u64)(n) << CE_URE_PSN2_SHFT) & \
719 CE_URE_PSN2_MASK)
720
721/*
722 * PIO address space ranges for CE
723 */
724
725/* Local CE Registers Space */
726#define CE_PIO_MMR 0x00000000
727#define CE_PIO_MMR_LEN 0x04000000
728
729/* PCI Compatible Config Space */
730#define CE_PIO_CONFIG_SPACE 0x04000000
731#define CE_PIO_CONFIG_SPACE_LEN 0x04000000
732
733/* PCI I/O Space Alias */
734#define CE_PIO_IO_SPACE_ALIAS 0x08000000
735#define CE_PIO_IO_SPACE_ALIAS_LEN 0x08000000
736
737/* PCI Enhanced Config Space */
738#define CE_PIO_E_CONFIG_SPACE 0x10000000
739#define CE_PIO_E_CONFIG_SPACE_LEN 0x10000000
740
741/* PCI I/O Space */
742#define CE_PIO_IO_SPACE 0x100000000
743#define CE_PIO_IO_SPACE_LEN 0x100000000
744
745/* PCI MEM Space */
746#define CE_PIO_MEM_SPACE 0x200000000
747#define CE_PIO_MEM_SPACE_LEN TIO_HWIN_SIZE
748
749
750/*
751 * CE PCI Enhanced Config Space shifts & masks
752 */
753#define CE_E_CONFIG_BUS_SHFT 20
754#define CE_E_CONFIG_BUS_MASK (0xFF << CE_E_CONFIG_BUS_SHFT)
755#define CE_E_CONFIG_DEVICE_SHFT 15
756#define CE_E_CONFIG_DEVICE_MASK (0x1F << CE_E_CONFIG_DEVICE_SHFT)
757#define CE_E_CONFIG_FUNC_SHFT 12
758#define CE_E_CONFIG_FUNC_MASK (0x7 << CE_E_CONFIG_FUNC_SHFT)
759
760#endif /* __ASM_IA64_SN_TIOCE_H__ */
diff --git a/arch/ia64/include/asm/sn/tioce_provider.h b/arch/ia64/include/asm/sn/tioce_provider.h
new file mode 100644
index 000000000000..32c32f30b099
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tioce_provider.h
@@ -0,0 +1,63 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_CE_PROVIDER_H
10#define _ASM_IA64_SN_CE_PROVIDER_H
11
12#include <asm/sn/pcibus_provider_defs.h>
13#include <asm/sn/tioce.h>
14
15/*
16 * Common TIOCE structure shared between the prom and kernel
17 *
18 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES TO THE
19 * PROM VERSION.
20 */
21struct tioce_common {
22 struct pcibus_bussoft ce_pcibus; /* common pciio header */
23
24 u32 ce_rev;
25 u64 ce_kernel_private;
26 u64 ce_prom_private;
27};
28
29struct tioce_kernel {
30 struct tioce_common *ce_common;
31 spinlock_t ce_lock;
32 struct list_head ce_dmamap_list;
33
34 u64 ce_ate40_shadow[TIOCE_NUM_M40_ATES];
35 u64 ce_ate3240_shadow[TIOCE_NUM_M3240_ATES];
36 u32 ce_ate3240_pagesize;
37
38 u8 ce_port1_secondary;
39
40 /* per-port resources */
41 struct {
42 int dirmap_refcnt;
43 u64 dirmap_shadow;
44 } ce_port[TIOCE_NUM_PORTS];
45};
46
47struct tioce_dmamap {
48 struct list_head ce_dmamap_list; /* headed by tioce_kernel */
49 u32 refcnt;
50
51 u64 nbytes; /* # bytes mapped */
52
53 u64 ct_start; /* coretalk start address */
54 u64 pci_start; /* bus start address */
55
56 u64 __iomem *ate_hw;/* hw ptr of first ate in map */
57 u64 *ate_shadow; /* shadow ptr of firat ate */
58 u16 ate_count; /* # ate's in the map */
59};
60
61extern int tioce_init_provider(void);
62
63#endif /* __ASM_IA64_SN_CE_PROVIDER_H */
diff --git a/arch/ia64/include/asm/sn/tiocp.h b/arch/ia64/include/asm/sn/tiocp.h
new file mode 100644
index 000000000000..e8ad0bb5b6c5
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tiocp.h
@@ -0,0 +1,257 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_TIOCP_H
9#define _ASM_IA64_SN_PCI_TIOCP_H
10
11#define TIOCP_HOST_INTR_ADDR 0x003FFFFFFFFFFFFFUL
12#define TIOCP_PCI64_CMDTYPE_MEM (0x1ull << 60)
13#define TIOCP_PCI64_CMDTYPE_MSI (0x3ull << 60)
14
15
16/*****************************************************************************
17 *********************** TIOCP MMR structure mapping ***************************
18 *****************************************************************************/
19
20struct tiocp{
21
22 /* 0x000000-0x00FFFF -- Local Registers */
23
24 /* 0x000000-0x000057 -- (Legacy Widget Space) Configuration */
25 u64 cp_id; /* 0x000000 */
26 u64 cp_stat; /* 0x000008 */
27 u64 cp_err_upper; /* 0x000010 */
28 u64 cp_err_lower; /* 0x000018 */
29 #define cp_err cp_err_lower
30 u64 cp_control; /* 0x000020 */
31 u64 cp_req_timeout; /* 0x000028 */
32 u64 cp_intr_upper; /* 0x000030 */
33 u64 cp_intr_lower; /* 0x000038 */
34 #define cp_intr cp_intr_lower
35 u64 cp_err_cmdword; /* 0x000040 */
36 u64 _pad_000048; /* 0x000048 */
37 u64 cp_tflush; /* 0x000050 */
38
39 /* 0x000058-0x00007F -- Bridge-specific Configuration */
40 u64 cp_aux_err; /* 0x000058 */
41 u64 cp_resp_upper; /* 0x000060 */
42 u64 cp_resp_lower; /* 0x000068 */
43 #define cp_resp cp_resp_lower
44 u64 cp_tst_pin_ctrl; /* 0x000070 */
45 u64 cp_addr_lkerr; /* 0x000078 */
46
47 /* 0x000080-0x00008F -- PMU & MAP */
48 u64 cp_dir_map; /* 0x000080 */
49 u64 _pad_000088; /* 0x000088 */
50
51 /* 0x000090-0x00009F -- SSRAM */
52 u64 cp_map_fault; /* 0x000090 */
53 u64 _pad_000098; /* 0x000098 */
54
55 /* 0x0000A0-0x0000AF -- Arbitration */
56 u64 cp_arb; /* 0x0000A0 */
57 u64 _pad_0000A8; /* 0x0000A8 */
58
59 /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
60 u64 cp_ate_parity_err; /* 0x0000B0 */
61 u64 _pad_0000B8; /* 0x0000B8 */
62
63 /* 0x0000C0-0x0000FF -- PCI/GIO */
64 u64 cp_bus_timeout; /* 0x0000C0 */
65 u64 cp_pci_cfg; /* 0x0000C8 */
66 u64 cp_pci_err_upper; /* 0x0000D0 */
67 u64 cp_pci_err_lower; /* 0x0000D8 */
68 #define cp_pci_err cp_pci_err_lower
69 u64 _pad_0000E0[4]; /* 0x0000{E0..F8} */
70
71 /* 0x000100-0x0001FF -- Interrupt */
72 u64 cp_int_status; /* 0x000100 */
73 u64 cp_int_enable; /* 0x000108 */
74 u64 cp_int_rst_stat; /* 0x000110 */
75 u64 cp_int_mode; /* 0x000118 */
76 u64 cp_int_device; /* 0x000120 */
77 u64 cp_int_host_err; /* 0x000128 */
78 u64 cp_int_addr[8]; /* 0x0001{30,,,68} */
79 u64 cp_err_int_view; /* 0x000170 */
80 u64 cp_mult_int; /* 0x000178 */
81 u64 cp_force_always[8]; /* 0x0001{80,,,B8} */
82 u64 cp_force_pin[8]; /* 0x0001{C0,,,F8} */
83
84 /* 0x000200-0x000298 -- Device */
85 u64 cp_device[4]; /* 0x0002{00,,,18} */
86 u64 _pad_000220[4]; /* 0x0002{20,,,38} */
87 u64 cp_wr_req_buf[4]; /* 0x0002{40,,,58} */
88 u64 _pad_000260[4]; /* 0x0002{60,,,78} */
89 u64 cp_rrb_map[2]; /* 0x0002{80,,,88} */
90 #define cp_even_resp cp_rrb_map[0] /* 0x000280 */
91 #define cp_odd_resp cp_rrb_map[1] /* 0x000288 */
92 u64 cp_resp_status; /* 0x000290 */
93 u64 cp_resp_clear; /* 0x000298 */
94
95 u64 _pad_0002A0[12]; /* 0x0002{A0..F8} */
96
97 /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
98 struct {
99 u64 upper; /* 0x0003{00,,,F0} */
100 u64 lower; /* 0x0003{08,,,F8} */
101 } cp_buf_addr_match[16];
102
103 /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
104 struct {
105 u64 flush_w_touch; /* 0x000{400,,,5C0} */
106 u64 flush_wo_touch; /* 0x000{408,,,5C8} */
107 u64 inflight; /* 0x000{410,,,5D0} */
108 u64 prefetch; /* 0x000{418,,,5D8} */
109 u64 total_pci_retry; /* 0x000{420,,,5E0} */
110 u64 max_pci_retry; /* 0x000{428,,,5E8} */
111 u64 max_latency; /* 0x000{430,,,5F0} */
112 u64 clear_all; /* 0x000{438,,,5F8} */
113 } cp_buf_count[8];
114
115
116 /* 0x000600-0x0009FF -- PCI/X registers */
117 u64 cp_pcix_bus_err_addr; /* 0x000600 */
118 u64 cp_pcix_bus_err_attr; /* 0x000608 */
119 u64 cp_pcix_bus_err_data; /* 0x000610 */
120 u64 cp_pcix_pio_split_addr; /* 0x000618 */
121 u64 cp_pcix_pio_split_attr; /* 0x000620 */
122 u64 cp_pcix_dma_req_err_attr; /* 0x000628 */
123 u64 cp_pcix_dma_req_err_addr; /* 0x000630 */
124 u64 cp_pcix_timeout; /* 0x000638 */
125
126 u64 _pad_000640[24]; /* 0x000{640,,,6F8} */
127
128 /* 0x000700-0x000737 -- Debug Registers */
129 u64 cp_ct_debug_ctl; /* 0x000700 */
130 u64 cp_br_debug_ctl; /* 0x000708 */
131 u64 cp_mux3_debug_ctl; /* 0x000710 */
132 u64 cp_mux4_debug_ctl; /* 0x000718 */
133 u64 cp_mux5_debug_ctl; /* 0x000720 */
134 u64 cp_mux6_debug_ctl; /* 0x000728 */
135 u64 cp_mux7_debug_ctl; /* 0x000730 */
136
137 u64 _pad_000738[89]; /* 0x000{738,,,9F8} */
138
139 /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
140 struct {
141 u64 cp_buf_addr; /* 0x000{A00,,,AF0} */
142 u64 cp_buf_attr; /* 0X000{A08,,,AF8} */
143 } cp_pcix_read_buf_64[16];
144
145 struct {
146 u64 cp_buf_addr; /* 0x000{B00,,,BE0} */
147 u64 cp_buf_attr; /* 0x000{B08,,,BE8} */
148 u64 cp_buf_valid; /* 0x000{B10,,,BF0} */
149 u64 __pad1; /* 0x000{B18,,,BF8} */
150 } cp_pcix_write_buf_64[8];
151
152 /* End of Local Registers -- Start of Address Map space */
153
154 char _pad_000c00[0x010000 - 0x000c00];
155
156 /* 0x010000-0x011FF8 -- Internal ATE RAM (Auto Parity Generation) */
157 u64 cp_int_ate_ram[1024]; /* 0x010000-0x011FF8 */
158
159 char _pad_012000[0x14000 - 0x012000];
160
161 /* 0x014000-0x015FF8 -- Internal ATE RAM (Manual Parity Generation) */
162 u64 cp_int_ate_ram_mp[1024]; /* 0x014000-0x015FF8 */
163
164 char _pad_016000[0x18000 - 0x016000];
165
166 /* 0x18000-0x197F8 -- TIOCP Write Request Ram */
167 u64 cp_wr_req_lower[256]; /* 0x18000 - 0x187F8 */
168 u64 cp_wr_req_upper[256]; /* 0x18800 - 0x18FF8 */
169 u64 cp_wr_req_parity[256]; /* 0x19000 - 0x197F8 */
170
171 char _pad_019800[0x1C000 - 0x019800];
172
173 /* 0x1C000-0x1EFF8 -- TIOCP Read Response Ram */
174 u64 cp_rd_resp_lower[512]; /* 0x1C000 - 0x1CFF8 */
175 u64 cp_rd_resp_upper[512]; /* 0x1D000 - 0x1DFF8 */
176 u64 cp_rd_resp_parity[512]; /* 0x1E000 - 0x1EFF8 */
177
178 char _pad_01F000[0x20000 - 0x01F000];
179
180 /* 0x020000-0x021FFF -- Host Device (CP) Configuration Space (not used) */
181 char _pad_020000[0x021000 - 0x20000];
182
183 /* 0x021000-0x027FFF -- PCI Device Configuration Spaces */
184 union {
185 u8 c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */
186 u16 s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */
187 u32 l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */
188 u64 d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */
189 union {
190 u8 c[0x100 / 1];
191 u16 s[0x100 / 2];
192 u32 l[0x100 / 4];
193 u64 d[0x100 / 8];
194 } f[8];
195 } cp_type0_cfg_dev[7]; /* 0x02{1000,,,7FFF} */
196
197 /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
198 union {
199 u8 c[0x1000 / 1]; /* 0x028000-0x029000 */
200 u16 s[0x1000 / 2]; /* 0x028000-0x029000 */
201 u32 l[0x1000 / 4]; /* 0x028000-0x029000 */
202 u64 d[0x1000 / 8]; /* 0x028000-0x029000 */
203 union {
204 u8 c[0x100 / 1];
205 u16 s[0x100 / 2];
206 u32 l[0x100 / 4];
207 u64 d[0x100 / 8];
208 } f[8];
209 } cp_type1_cfg; /* 0x028000-0x029000 */
210
211 char _pad_029000[0x030000-0x029000];
212
213 /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
214 union {
215 u8 c[8 / 1];
216 u16 s[8 / 2];
217 u32 l[8 / 4];
218 u64 d[8 / 8];
219 } cp_pci_iack; /* 0x030000-0x030007 */
220
221 char _pad_030007[0x040000-0x030008];
222
223 /* 0x040000-0x040007 -- PCIX Special Cycle */
224 union {
225 u8 c[8 / 1];
226 u16 s[8 / 2];
227 u32 l[8 / 4];
228 u64 d[8 / 8];
229 } cp_pcix_cycle; /* 0x040000-0x040007 */
230
231 char _pad_040007[0x200000-0x040008];
232
233 /* 0x200000-0x7FFFFF -- PCI/GIO Device Spaces */
234 union {
235 u8 c[0x100000 / 1];
236 u16 s[0x100000 / 2];
237 u32 l[0x100000 / 4];
238 u64 d[0x100000 / 8];
239 } cp_devio_raw[6]; /* 0x200000-0x7FFFFF */
240
241 #define cp_devio(n) cp_devio_raw[((n)<2)?(n*2):(n+2)]
242
243 char _pad_800000[0xA00000-0x800000];
244
245 /* 0xA00000-0xBFFFFF -- PCI/GIO Device Spaces w/flush */
246 union {
247 u8 c[0x100000 / 1];
248 u16 s[0x100000 / 2];
249 u32 l[0x100000 / 4];
250 u64 d[0x100000 / 8];
251 } cp_devio_raw_flush[6]; /* 0xA00000-0xBFFFFF */
252
253 #define cp_devio_flush(n) cp_devio_raw_flush[((n)<2)?(n*2):(n+2)]
254
255};
256
257#endif /* _ASM_IA64_SN_PCI_TIOCP_H */
diff --git a/arch/ia64/include/asm/sn/tiocx.h b/arch/ia64/include/asm/sn/tiocx.h
new file mode 100644
index 000000000000..d29728492f36
--- /dev/null
+++ b/arch/ia64/include/asm/sn/tiocx.h
@@ -0,0 +1,72 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_TIOCX_H
10#define _ASM_IA64_SN_TIO_TIOCX_H
11
12#ifdef __KERNEL__
13
14struct cx_id_s {
15 unsigned int part_num;
16 unsigned int mfg_num;
17 int nasid;
18};
19
20struct cx_dev {
21 struct cx_id_s cx_id;
22 int bt; /* board/blade type */
23 void *soft; /* driver specific */
24 struct hubdev_info *hubdev;
25 struct device dev;
26 struct cx_drv *driver;
27};
28
29struct cx_device_id {
30 unsigned int part_num;
31 unsigned int mfg_num;
32};
33
34struct cx_drv {
35 char *name;
36 const struct cx_device_id *id_table;
37 struct device_driver driver;
38 int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
39 int (*remove) (struct cx_dev * dev);
40};
41
42/* create DMA address by stripping AS bits */
43#define TIOCX_DMA_ADDR(a) (u64)((u64)(a) & 0xffffcfffffffffUL)
44
45#define TIOCX_TO_TIOCX_DMA_ADDR(a) (u64)(((u64)(a) & 0xfffffffff) | \
46 ((((u64)(a)) & 0xffffc000000000UL) <<2))
47
48#define TIO_CE_ASIC_PARTNUM 0xce00
49#define TIOCX_CORELET 3
50
51/* These are taken from tio_mmr_as.h */
52#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
53#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
54#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
55#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
56
57#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
58#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
59
60extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
61extern void tiocx_irq_free(struct sn_irq_info *);
62extern int cx_device_unregister(struct cx_dev *);
63extern int cx_device_register(nasid_t, int, int, struct hubdev_info *, int);
64extern int cx_driver_unregister(struct cx_drv *);
65extern int cx_driver_register(struct cx_drv *);
66extern u64 tiocx_dma_addr(u64 addr);
67extern u64 tiocx_swin_base(int nasid);
68extern void tiocx_mmr_store(int nasid, u64 offset, u64 value);
69extern u64 tiocx_mmr_load(int nasid, u64 offset);
70
71#endif // __KERNEL__
72#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/arch/ia64/include/asm/sn/types.h b/arch/ia64/include/asm/sn/types.h
new file mode 100644
index 000000000000..8e04ee211e59
--- /dev/null
+++ b/arch/ia64/include/asm/sn/types.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999,2001-2003 Silicon Graphics, Inc. All Rights Reserved.
7 * Copyright (C) 1999 by Ralf Baechle
8 */
9#ifndef _ASM_IA64_SN_TYPES_H
10#define _ASM_IA64_SN_TYPES_H
11
12#include <linux/types.h>
13
14typedef unsigned long cpuid_t;
15typedef signed short nasid_t; /* node id in numa-as-id space */
16typedef signed char partid_t; /* partition ID type */
17typedef unsigned int moduleid_t; /* user-visible module number type */
18typedef unsigned int cmoduleid_t; /* kernel compact module id type */
19typedef unsigned char slotid_t; /* slot (blade) within module */
20typedef unsigned char slabid_t; /* slab (asic) within slot */
21typedef u64 nic_t;
22typedef unsigned long iopaddr_t;
23typedef unsigned long paddr_t;
24typedef short cnodeid_t;
25
26#endif /* _ASM_IA64_SN_TYPES_H */
diff --git a/arch/ia64/include/asm/socket.h b/arch/ia64/include/asm/socket.h
new file mode 100644
index 000000000000..d5ef0aa3e312
--- /dev/null
+++ b/arch/ia64/include/asm/socket.h
@@ -0,0 +1,66 @@
1#ifndef _ASM_IA64_SOCKET_H
2#define _ASM_IA64_SOCKET_H
3
4/*
5 * Socket related defines.
6 *
7 * Based on <asm-i386/socket.h>.
8 *
9 * Modified 1998-2000
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12
13#include <asm/sockios.h>
14
15/* For setsockopt(2) */
16#define SOL_SOCKET 1
17
18#define SO_DEBUG 1
19#define SO_REUSEADDR 2
20#define SO_TYPE 3
21#define SO_ERROR 4
22#define SO_DONTROUTE 5
23#define SO_BROADCAST 6
24#define SO_SNDBUF 7
25#define SO_RCVBUF 8
26#define SO_SNDBUFFORCE 32
27#define SO_RCVBUFFORCE 33
28#define SO_KEEPALIVE 9
29#define SO_OOBINLINE 10
30#define SO_NO_CHECK 11
31#define SO_PRIORITY 12
32#define SO_LINGER 13
33#define SO_BSDCOMPAT 14
34/* To add :#define SO_REUSEPORT 15 */
35#define SO_PASSCRED 16
36#define SO_PEERCRED 17
37#define SO_RCVLOWAT 18
38#define SO_SNDLOWAT 19
39#define SO_RCVTIMEO 20
40#define SO_SNDTIMEO 21
41
42/* Security levels - as per NRL IPv6 - don't actually do anything */
43#define SO_SECURITY_AUTHENTICATION 22
44#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
45#define SO_SECURITY_ENCRYPTION_NETWORK 24
46
47#define SO_BINDTODEVICE 25
48
49/* Socket filtering */
50#define SO_ATTACH_FILTER 26
51#define SO_DETACH_FILTER 27
52
53#define SO_PEERNAME 28
54#define SO_TIMESTAMP 29
55#define SCM_TIMESTAMP SO_TIMESTAMP
56
57#define SO_ACCEPTCONN 30
58
59#define SO_PEERSEC 31
60#define SO_PASSSEC 34
61#define SO_TIMESTAMPNS 35
62#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
63
64#define SO_MARK 36
65
66#endif /* _ASM_IA64_SOCKET_H */
diff --git a/arch/ia64/include/asm/sockios.h b/arch/ia64/include/asm/sockios.h
new file mode 100644
index 000000000000..15c92468ad38
--- /dev/null
+++ b/arch/ia64/include/asm/sockios.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_IA64_SOCKIOS_H
2#define _ASM_IA64_SOCKIOS_H
3
4/*
5 * Socket-level I/O control calls.
6 *
7 * Based on <asm-i386/sockios.h>.
8 *
9 * Modified 1998, 1999
10 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
11 */
12#define FIOSETOWN 0x8901
13#define SIOCSPGRP 0x8902
14#define FIOGETOWN 0x8903
15#define SIOCGPGRP 0x8904
16#define SIOCATMARK 0x8905
17#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
18#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
19
20#endif /* _ASM_IA64_SOCKIOS_H */
diff --git a/arch/ia64/include/asm/sparsemem.h b/arch/ia64/include/asm/sparsemem.h
new file mode 100644
index 000000000000..67a7c40ec27f
--- /dev/null
+++ b/arch/ia64/include/asm/sparsemem.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_IA64_SPARSEMEM_H
2#define _ASM_IA64_SPARSEMEM_H
3
4#ifdef CONFIG_SPARSEMEM
5/*
6 * SECTION_SIZE_BITS 2^N: how big each section will be
7 * MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
8 */
9
10#define SECTION_SIZE_BITS (30)
11#define MAX_PHYSMEM_BITS (50)
12#ifdef CONFIG_FORCE_MAX_ZONEORDER
13#if ((CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT) > SECTION_SIZE_BITS)
14#undef SECTION_SIZE_BITS
15#define SECTION_SIZE_BITS (CONFIG_FORCE_MAX_ZONEORDER - 1 + PAGE_SHIFT)
16#endif
17#endif
18
19#endif /* CONFIG_SPARSEMEM */
20#endif /* _ASM_IA64_SPARSEMEM_H */
diff --git a/arch/ia64/include/asm/spinlock.h b/arch/ia64/include/asm/spinlock.h
new file mode 100644
index 000000000000..0229fb95fb38
--- /dev/null
+++ b/arch/ia64/include/asm/spinlock.h
@@ -0,0 +1,220 @@
1#ifndef _ASM_IA64_SPINLOCK_H
2#define _ASM_IA64_SPINLOCK_H
3
4/*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *
9 * This file is used for SMP configurations only.
10 */
11
12#include <linux/compiler.h>
13#include <linux/kernel.h>
14#include <linux/bitops.h>
15
16#include <asm/atomic.h>
17#include <asm/intrinsics.h>
18#include <asm/system.h>
19
20#define __raw_spin_lock_init(x) ((x)->lock = 0)
21
22#ifdef ASM_SUPPORTED
23/*
24 * Try to get the lock. If we fail to get the lock, make a non-standard call to
25 * ia64_spinlock_contention(). We do not use a normal call because that would force all
26 * callers of __raw_spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
27 * carefully coded to touch only those registers that __raw_spin_lock() marks "clobbered".
28 */
29
30#define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
31
32static inline void
33__raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
34{
35 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
36
37#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
38# ifdef CONFIG_ITANIUM
39 /* don't use brl on Itanium... */
40 asm volatile ("{\n\t"
41 " mov ar.ccv = r0\n\t"
42 " mov r28 = ip\n\t"
43 " mov r30 = 1;;\n\t"
44 "}\n\t"
45 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
46 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
47 "cmp4.ne p14, p0 = r30, r0\n\t"
48 "mov b6 = r29;;\n\t"
49 "mov r27=%2\n\t"
50 "(p14) br.cond.spnt.many b6"
51 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
52# else
53 asm volatile ("{\n\t"
54 " mov ar.ccv = r0\n\t"
55 " mov r28 = ip\n\t"
56 " mov r30 = 1;;\n\t"
57 "}\n\t"
58 "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
59 "cmp4.ne p14, p0 = r30, r0\n\t"
60 "mov r27=%2\n\t"
61 "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
62 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
63# endif /* CONFIG_MCKINLEY */
64#else
65# ifdef CONFIG_ITANIUM
66 /* don't use brl on Itanium... */
67 /* mis-declare, so we get the entry-point, not it's function descriptor: */
68 asm volatile ("mov r30 = 1\n\t"
69 "mov r27=%2\n\t"
70 "mov ar.ccv = r0;;\n\t"
71 "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
72 "movl r29 = ia64_spinlock_contention;;\n\t"
73 "cmp4.ne p14, p0 = r30, r0\n\t"
74 "mov b6 = r29;;\n\t"
75 "(p14) br.call.spnt.many b6 = b6"
76 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
77# else
78 asm volatile ("mov r30 = 1\n\t"
79 "mov r27=%2\n\t"
80 "mov ar.ccv = r0;;\n\t"
81 "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
82 "cmp4.ne p14, p0 = r30, r0\n\t"
83 "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
84 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
85# endif /* CONFIG_MCKINLEY */
86#endif
87}
88
89#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
90
91/* Unlock by doing an ordered store and releasing the cacheline with nta */
92static inline void __raw_spin_unlock(raw_spinlock_t *x) {
93 barrier();
94 asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
95}
96
97#else /* !ASM_SUPPORTED */
98#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
99# define __raw_spin_lock(x) \
100do { \
101 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
102 __u64 ia64_spinlock_val; \
103 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
104 if (unlikely(ia64_spinlock_val)) { \
105 do { \
106 while (*ia64_spinlock_ptr) \
107 ia64_barrier(); \
108 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
109 } while (ia64_spinlock_val); \
110 } \
111} while (0)
112#define __raw_spin_unlock(x) do { barrier(); ((raw_spinlock_t *) x)->lock = 0; } while (0)
113#endif /* !ASM_SUPPORTED */
114
115#define __raw_spin_is_locked(x) ((x)->lock != 0)
116#define __raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
117#define __raw_spin_unlock_wait(lock) \
118 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
119
120#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
121#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
122
123#define __raw_read_lock(rw) \
124do { \
125 raw_rwlock_t *__read_lock_ptr = (rw); \
126 \
127 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
128 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
129 while (*(volatile int *)__read_lock_ptr < 0) \
130 cpu_relax(); \
131 } \
132} while (0)
133
134#define __raw_read_unlock(rw) \
135do { \
136 raw_rwlock_t *__read_lock_ptr = (rw); \
137 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
138} while (0)
139
140#ifdef ASM_SUPPORTED
141#define __raw_write_lock(rw) \
142do { \
143 __asm__ __volatile__ ( \
144 "mov ar.ccv = r0\n" \
145 "dep r29 = -1, r0, 31, 1;;\n" \
146 "1:\n" \
147 "ld4 r2 = [%0];;\n" \
148 "cmp4.eq p0,p7 = r0,r2\n" \
149 "(p7) br.cond.spnt.few 1b \n" \
150 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
151 "cmp4.eq p0,p7 = r0, r2\n" \
152 "(p7) br.cond.spnt.few 1b;;\n" \
153 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
154} while(0)
155
156#define __raw_write_trylock(rw) \
157({ \
158 register long result; \
159 \
160 __asm__ __volatile__ ( \
161 "mov ar.ccv = r0\n" \
162 "dep r29 = -1, r0, 31, 1;;\n" \
163 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
164 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
165 (result == 0); \
166})
167
168static inline void __raw_write_unlock(raw_rwlock_t *x)
169{
170 u8 *y = (u8 *)x;
171 barrier();
172 asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
173}
174
175#else /* !ASM_SUPPORTED */
176
177#define __raw_write_lock(l) \
178({ \
179 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
180 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
181 do { \
182 while (*ia64_write_lock_ptr) \
183 ia64_barrier(); \
184 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
185 } while (ia64_val); \
186})
187
188#define __raw_write_trylock(rw) \
189({ \
190 __u64 ia64_val; \
191 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
192 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
193 (ia64_val == 0); \
194})
195
196static inline void __raw_write_unlock(raw_rwlock_t *x)
197{
198 barrier();
199 x->write_lock = 0;
200}
201
202#endif /* !ASM_SUPPORTED */
203
204static inline int __raw_read_trylock(raw_rwlock_t *x)
205{
206 union {
207 raw_rwlock_t lock;
208 __u32 word;
209 } old, new;
210 old.lock = new.lock = *x;
211 old.lock.write_lock = new.lock.write_lock = 0;
212 ++new.lock.read_counter;
213 return (u32)ia64_cmpxchg4_acq((__u32 *)(x), new.word, old.word) == old.word;
214}
215
216#define _raw_spin_relax(lock) cpu_relax()
217#define _raw_read_relax(lock) cpu_relax()
218#define _raw_write_relax(lock) cpu_relax()
219
220#endif /* _ASM_IA64_SPINLOCK_H */
diff --git a/arch/ia64/include/asm/spinlock_types.h b/arch/ia64/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..474e46f1ab4a
--- /dev/null
+++ b/arch/ia64/include/asm/spinlock_types.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_IA64_SPINLOCK_TYPES_H
2#define _ASM_IA64_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile unsigned int read_counter : 31;
16 volatile unsigned int write_lock : 1;
17} raw_rwlock_t;
18
19#define __RAW_RW_LOCK_UNLOCKED { 0, 0 }
20
21#endif
diff --git a/arch/ia64/include/asm/stat.h b/arch/ia64/include/asm/stat.h
new file mode 100644
index 000000000000..367bb90cdffa
--- /dev/null
+++ b/arch/ia64/include/asm/stat.h
@@ -0,0 +1,51 @@
1#ifndef _ASM_IA64_STAT_H
2#define _ASM_IA64_STAT_H
3
4/*
5 * Modified 1998, 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 */
8
9struct stat {
10 unsigned long st_dev;
11 unsigned long st_ino;
12 unsigned long st_nlink;
13 unsigned int st_mode;
14 unsigned int st_uid;
15 unsigned int st_gid;
16 unsigned int __pad0;
17 unsigned long st_rdev;
18 unsigned long st_size;
19 unsigned long st_atime;
20 unsigned long st_atime_nsec;
21 unsigned long st_mtime;
22 unsigned long st_mtime_nsec;
23 unsigned long st_ctime;
24 unsigned long st_ctime_nsec;
25 unsigned long st_blksize;
26 long st_blocks;
27 unsigned long __unused[3];
28};
29
30#define STAT_HAVE_NSEC 1
31
32struct ia64_oldstat {
33 unsigned int st_dev;
34 unsigned int st_ino;
35 unsigned int st_mode;
36 unsigned int st_nlink;
37 unsigned int st_uid;
38 unsigned int st_gid;
39 unsigned int st_rdev;
40 unsigned int __pad1;
41 unsigned long st_size;
42 unsigned long st_atime;
43 unsigned long st_mtime;
44 unsigned long st_ctime;
45 unsigned int st_blksize;
46 int st_blocks;
47 unsigned int __unused1;
48 unsigned int __unused2;
49};
50
51#endif /* _ASM_IA64_STAT_H */
diff --git a/arch/ia64/include/asm/statfs.h b/arch/ia64/include/asm/statfs.h
new file mode 100644
index 000000000000..811097974f31
--- /dev/null
+++ b/arch/ia64/include/asm/statfs.h
@@ -0,0 +1,62 @@
1#ifndef _ASM_IA64_STATFS_H
2#define _ASM_IA64_STATFS_H
3
4/*
5 * Based on <asm-i386/statfs.h>.
6 *
7 * Modified 1998, 1999, 2003
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 */
10
11#ifndef __KERNEL_STRICT_NAMES
12# include <linux/types.h>
13typedef __kernel_fsid_t fsid_t;
14#endif
15
16/*
17 * This is ugly --- we're already 64-bit, so just duplicate the definitions
18 */
19struct statfs {
20 long f_type;
21 long f_bsize;
22 long f_blocks;
23 long f_bfree;
24 long f_bavail;
25 long f_files;
26 long f_ffree;
27 __kernel_fsid_t f_fsid;
28 long f_namelen;
29 long f_frsize;
30 long f_spare[5];
31};
32
33
34struct statfs64 {
35 long f_type;
36 long f_bsize;
37 long f_blocks;
38 long f_bfree;
39 long f_bavail;
40 long f_files;
41 long f_ffree;
42 __kernel_fsid_t f_fsid;
43 long f_namelen;
44 long f_frsize;
45 long f_spare[5];
46};
47
48struct compat_statfs64 {
49 __u32 f_type;
50 __u32 f_bsize;
51 __u64 f_blocks;
52 __u64 f_bfree;
53 __u64 f_bavail;
54 __u64 f_files;
55 __u64 f_ffree;
56 __kernel_fsid_t f_fsid;
57 __u32 f_namelen;
58 __u32 f_frsize;
59 __u32 f_spare[5];
60} __attribute__((packed));
61
62#endif /* _ASM_IA64_STATFS_H */
diff --git a/arch/ia64/include/asm/string.h b/arch/ia64/include/asm/string.h
new file mode 100644
index 000000000000..85fd65c52a8c
--- /dev/null
+++ b/arch/ia64/include/asm/string.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_IA64_STRING_H
2#define _ASM_IA64_STRING_H
3
4/*
5 * Here is where we want to put optimized versions of the string
6 * routines.
7 *
8 * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 */
11
12
13#define __HAVE_ARCH_STRLEN 1 /* see arch/ia64/lib/strlen.S */
14#define __HAVE_ARCH_MEMSET 1 /* see arch/ia64/lib/memset.S */
15#define __HAVE_ARCH_MEMCPY 1 /* see arch/ia64/lib/memcpy.S */
16
17extern __kernel_size_t strlen (const char *);
18extern void *memcpy (void *, const void *, __kernel_size_t);
19extern void *memset (void *, int, __kernel_size_t);
20
21#endif /* _ASM_IA64_STRING_H */
diff --git a/arch/ia64/include/asm/suspend.h b/arch/ia64/include/asm/suspend.h
new file mode 100644
index 000000000000..b05bbb6074e2
--- /dev/null
+++ b/arch/ia64/include/asm/suspend.h
@@ -0,0 +1 @@
/* dummy (must be non-empty to prevent prejudicial removal...) */
diff --git a/arch/ia64/include/asm/system.h b/arch/ia64/include/asm/system.h
new file mode 100644
index 000000000000..927a381c20ca
--- /dev/null
+++ b/arch/ia64/include/asm/system.h
@@ -0,0 +1,292 @@
1#ifndef _ASM_IA64_SYSTEM_H
2#define _ASM_IA64_SYSTEM_H
3
4/*
5 * System defines. Note that this is included both from .c and .S
6 * files, so it does only defines, not any C code. This is based
7 * on information published in the Processor Abstraction Layer
8 * and the System Abstraction Layer manual.
9 *
10 * Copyright (C) 1998-2003 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
13 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
14 */
15
16#include <asm/kregs.h>
17#include <asm/page.h>
18#include <asm/pal.h>
19#include <asm/percpu.h>
20
21#define GATE_ADDR RGN_BASE(RGN_GATE)
22
23/*
24 * 0xa000000000000000+2*PERCPU_PAGE_SIZE
25 * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
26 */
27#define KERNEL_START (GATE_ADDR+__IA64_UL_CONST(0x100000000))
28#define PERCPU_ADDR (-PERCPU_PAGE_SIZE)
29#define LOAD_OFFSET (KERNEL_START - KERNEL_TR_PAGE_SIZE)
30
31#ifndef __ASSEMBLY__
32
33#include <linux/kernel.h>
34#include <linux/types.h>
35
36#define AT_VECTOR_SIZE_ARCH 2 /* entries in ARCH_DLINFO */
37
38struct pci_vector_struct {
39 __u16 segment; /* PCI Segment number */
40 __u16 bus; /* PCI Bus number */
41 __u32 pci_id; /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
42 __u8 pin; /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
43 __u32 irq; /* IRQ assigned */
44};
45
46extern struct ia64_boot_param {
47 __u64 command_line; /* physical address of command line arguments */
48 __u64 efi_systab; /* physical address of EFI system table */
49 __u64 efi_memmap; /* physical address of EFI memory map */
50 __u64 efi_memmap_size; /* size of EFI memory map */
51 __u64 efi_memdesc_size; /* size of an EFI memory map descriptor */
52 __u32 efi_memdesc_version; /* memory descriptor version */
53 struct {
54 __u16 num_cols; /* number of columns on console output device */
55 __u16 num_rows; /* number of rows on console output device */
56 __u16 orig_x; /* cursor's x position */
57 __u16 orig_y; /* cursor's y position */
58 } console_info;
59 __u64 fpswa; /* physical address of the fpswa interface */
60 __u64 initrd_start;
61 __u64 initrd_size;
62} *ia64_boot_param;
63
64/*
65 * Macros to force memory ordering. In these descriptions, "previous"
66 * and "subsequent" refer to program order; "visible" means that all
67 * architecturally visible effects of a memory access have occurred
68 * (at a minimum, this means the memory has been read or written).
69 *
70 * wmb(): Guarantees that all preceding stores to memory-
71 * like regions are visible before any subsequent
72 * stores and that all following stores will be
73 * visible only after all previous stores.
74 * rmb(): Like wmb(), but for reads.
75 * mb(): wmb()/rmb() combo, i.e., all previous memory
76 * accesses are visible before all subsequent
77 * accesses and vice versa. This is also known as
78 * a "fence."
79 *
80 * Note: "mb()" and its variants cannot be used as a fence to order
81 * accesses to memory mapped I/O registers. For that, mf.a needs to
82 * be used. However, we don't want to always use mf.a because (a)
83 * it's (presumably) much slower than mf and (b) mf.a is supported for
84 * sequential memory pages only.
85 */
86#define mb() ia64_mf()
87#define rmb() mb()
88#define wmb() mb()
89#define read_barrier_depends() do { } while(0)
90
91#ifdef CONFIG_SMP
92# define smp_mb() mb()
93# define smp_rmb() rmb()
94# define smp_wmb() wmb()
95# define smp_read_barrier_depends() read_barrier_depends()
96#else
97# define smp_mb() barrier()
98# define smp_rmb() barrier()
99# define smp_wmb() barrier()
100# define smp_read_barrier_depends() do { } while(0)
101#endif
102
103/*
104 * XXX check on this ---I suspect what Linus really wants here is
105 * acquire vs release semantics but we can't discuss this stuff with
106 * Linus just yet. Grrr...
107 */
108#define set_mb(var, value) do { (var) = (value); mb(); } while (0)
109
110#define safe_halt() ia64_pal_halt_light() /* PAL_HALT_LIGHT */
111
112/*
113 * The group barrier in front of the rsm & ssm are necessary to ensure
114 * that none of the previous instructions in the same group are
115 * affected by the rsm/ssm.
116 */
117/* For spinlocks etc */
118
119/*
120 * - clearing psr.i is implicitly serialized (visible by next insn)
121 * - setting psr.i requires data serialization
122 * - we need a stop-bit before reading PSR because we sometimes
123 * write a floating-point register right before reading the PSR
124 * and that writes to PSR.mfl
125 */
126#ifdef CONFIG_PARAVIRT
127#define __local_save_flags() ia64_get_psr_i()
128#else
129#define __local_save_flags() ia64_getreg(_IA64_REG_PSR)
130#endif
131
132#define __local_irq_save(x) \
133do { \
134 ia64_stop(); \
135 (x) = __local_save_flags(); \
136 ia64_stop(); \
137 ia64_rsm(IA64_PSR_I); \
138} while (0)
139
140#define __local_irq_disable() \
141do { \
142 ia64_stop(); \
143 ia64_rsm(IA64_PSR_I); \
144} while (0)
145
146#define __local_irq_restore(x) ia64_intrin_local_irq_restore((x) & IA64_PSR_I)
147
148#ifdef CONFIG_IA64_DEBUG_IRQ
149
150 extern unsigned long last_cli_ip;
151
152# define __save_ip() last_cli_ip = ia64_getreg(_IA64_REG_IP)
153
154# define local_irq_save(x) \
155do { \
156 unsigned long __psr; \
157 \
158 __local_irq_save(__psr); \
159 if (__psr & IA64_PSR_I) \
160 __save_ip(); \
161 (x) = __psr; \
162} while (0)
163
164# define local_irq_disable() do { unsigned long __x; local_irq_save(__x); } while (0)
165
166# define local_irq_restore(x) \
167do { \
168 unsigned long __old_psr, __psr = (x); \
169 \
170 local_save_flags(__old_psr); \
171 __local_irq_restore(__psr); \
172 if ((__old_psr & IA64_PSR_I) && !(__psr & IA64_PSR_I)) \
173 __save_ip(); \
174} while (0)
175
176#else /* !CONFIG_IA64_DEBUG_IRQ */
177# define local_irq_save(x) __local_irq_save(x)
178# define local_irq_disable() __local_irq_disable()
179# define local_irq_restore(x) __local_irq_restore(x)
180#endif /* !CONFIG_IA64_DEBUG_IRQ */
181
182#define local_irq_enable() ({ ia64_stop(); ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
183#define local_save_flags(flags) ({ ia64_stop(); (flags) = __local_save_flags(); })
184
185#define irqs_disabled() \
186({ \
187 unsigned long __ia64_id_flags; \
188 local_save_flags(__ia64_id_flags); \
189 (__ia64_id_flags & IA64_PSR_I) == 0; \
190})
191
192#ifdef __KERNEL__
193
194#ifdef CONFIG_IA32_SUPPORT
195# define IS_IA32_PROCESS(regs) (ia64_psr(regs)->is != 0)
196#else
197# define IS_IA32_PROCESS(regs) 0
198struct task_struct;
199static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
200static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
201#endif
202
203/*
204 * Context switch from one thread to another. If the two threads have
205 * different address spaces, schedule() has already taken care of
206 * switching to the new address space by calling switch_mm().
207 *
208 * Disabling access to the fph partition and the debug-register
209 * context switch MUST be done before calling ia64_switch_to() since a
210 * newly created thread returns directly to
211 * ia64_ret_from_syscall_clear_r8.
212 */
213extern struct task_struct *ia64_switch_to (void *next_task);
214
215struct task_struct;
216
217extern void ia64_save_extra (struct task_struct *task);
218extern void ia64_load_extra (struct task_struct *task);
219
220#ifdef CONFIG_VIRT_CPU_ACCOUNTING
221extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct *next);
222# define IA64_ACCOUNT_ON_SWITCH(p,n) ia64_account_on_switch(p,n)
223#else
224# define IA64_ACCOUNT_ON_SWITCH(p,n)
225#endif
226
227#ifdef CONFIG_PERFMON
228 DECLARE_PER_CPU(unsigned long, pfm_syst_info);
229# define PERFMON_IS_SYSWIDE() (__get_cpu_var(pfm_syst_info) & 0x1)
230#else
231# define PERFMON_IS_SYSWIDE() (0)
232#endif
233
234#define IA64_HAS_EXTRA_STATE(t) \
235 ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID) \
236 || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
237
238#define __switch_to(prev,next,last) do { \
239 IA64_ACCOUNT_ON_SWITCH(prev, next); \
240 if (IA64_HAS_EXTRA_STATE(prev)) \
241 ia64_save_extra(prev); \
242 if (IA64_HAS_EXTRA_STATE(next)) \
243 ia64_load_extra(next); \
244 ia64_psr(task_pt_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
245 (last) = ia64_switch_to((next)); \
246} while (0)
247
248#ifdef CONFIG_SMP
249/*
250 * In the SMP case, we save the fph state when context-switching away from a thread that
251 * modified fph. This way, when the thread gets scheduled on another CPU, the CPU can
252 * pick up the state from task->thread.fph, avoiding the complication of having to fetch
253 * the latest fph state from another CPU. In other words: eager save, lazy restore.
254 */
255# define switch_to(prev,next,last) do { \
256 if (ia64_psr(task_pt_regs(prev))->mfh && ia64_is_local_fpu_owner(prev)) { \
257 ia64_psr(task_pt_regs(prev))->mfh = 0; \
258 (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \
259 __ia64_save_fpu((prev)->thread.fph); \
260 } \
261 __switch_to(prev, next, last); \
262 /* "next" in old context is "current" in new context */ \
263 if (unlikely((current->thread.flags & IA64_THREAD_MIGRATION) && \
264 (task_cpu(current) != \
265 task_thread_info(current)->last_cpu))) { \
266 platform_migrate(current); \
267 task_thread_info(current)->last_cpu = task_cpu(current); \
268 } \
269} while (0)
270#else
271# define switch_to(prev,next,last) __switch_to(prev, next, last)
272#endif
273
274#define __ARCH_WANT_UNLOCKED_CTXSW
275#define ARCH_HAS_PREFETCH_SWITCH_STACK
276#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
277
278void cpu_idle_wait(void);
279
280#define arch_align_stack(x) (x)
281
282void default_idle(void);
283
284#ifdef CONFIG_VIRT_CPU_ACCOUNTING
285extern void account_system_vtime(struct task_struct *);
286#endif
287
288#endif /* __KERNEL__ */
289
290#endif /* __ASSEMBLY__ */
291
292#endif /* _ASM_IA64_SYSTEM_H */
diff --git a/arch/ia64/include/asm/termbits.h b/arch/ia64/include/asm/termbits.h
new file mode 100644
index 000000000000..9f162e0089ad
--- /dev/null
+++ b/arch/ia64/include/asm/termbits.h
@@ -0,0 +1,207 @@
1#ifndef _ASM_IA64_TERMBITS_H
2#define _ASM_IA64_TERMBITS_H
3
4/*
5 * Based on <asm-i386/termbits.h>.
6 *
7 * Modified 1999
8 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
9 *
10 * 99/01/28 Added new baudrates
11 */
12
13#include <linux/posix_types.h>
14
15typedef unsigned char cc_t;
16typedef unsigned int speed_t;
17typedef unsigned int tcflag_t;
18
19#define NCCS 19
20struct termios {
21 tcflag_t c_iflag; /* input mode flags */
22 tcflag_t c_oflag; /* output mode flags */
23 tcflag_t c_cflag; /* control mode flags */
24 tcflag_t c_lflag; /* local mode flags */
25 cc_t c_line; /* line discipline */
26 cc_t c_cc[NCCS]; /* control characters */
27};
28
29struct termios2 {
30 tcflag_t c_iflag; /* input mode flags */
31 tcflag_t c_oflag; /* output mode flags */
32 tcflag_t c_cflag; /* control mode flags */
33 tcflag_t c_lflag; /* local mode flags */
34 cc_t c_line; /* line discipline */
35 cc_t c_cc[NCCS]; /* control characters */
36 speed_t c_ispeed; /* input speed */
37 speed_t c_ospeed; /* output speed */
38};
39
40struct ktermios {
41 tcflag_t c_iflag; /* input mode flags */
42 tcflag_t c_oflag; /* output mode flags */
43 tcflag_t c_cflag; /* control mode flags */
44 tcflag_t c_lflag; /* local mode flags */
45 cc_t c_line; /* line discipline */
46 cc_t c_cc[NCCS]; /* control characters */
47 speed_t c_ispeed; /* input speed */
48 speed_t c_ospeed; /* output speed */
49};
50
51/* c_cc characters */
52#define VINTR 0
53#define VQUIT 1
54#define VERASE 2
55#define VKILL 3
56#define VEOF 4
57#define VTIME 5
58#define VMIN 6
59#define VSWTC 7
60#define VSTART 8
61#define VSTOP 9
62#define VSUSP 10
63#define VEOL 11
64#define VREPRINT 12
65#define VDISCARD 13
66#define VWERASE 14
67#define VLNEXT 15
68#define VEOL2 16
69
70/* c_iflag bits */
71#define IGNBRK 0000001
72#define BRKINT 0000002
73#define IGNPAR 0000004
74#define PARMRK 0000010
75#define INPCK 0000020
76#define ISTRIP 0000040
77#define INLCR 0000100
78#define IGNCR 0000200
79#define ICRNL 0000400
80#define IUCLC 0001000
81#define IXON 0002000
82#define IXANY 0004000
83#define IXOFF 0010000
84#define IMAXBEL 0020000
85#define IUTF8 0040000
86
87/* c_oflag bits */
88#define OPOST 0000001
89#define OLCUC 0000002
90#define ONLCR 0000004
91#define OCRNL 0000010
92#define ONOCR 0000020
93#define ONLRET 0000040
94#define OFILL 0000100
95#define OFDEL 0000200
96#define NLDLY 0000400
97#define NL0 0000000
98#define NL1 0000400
99#define CRDLY 0003000
100#define CR0 0000000
101#define CR1 0001000
102#define CR2 0002000
103#define CR3 0003000
104#define TABDLY 0014000
105#define TAB0 0000000
106#define TAB1 0004000
107#define TAB2 0010000
108#define TAB3 0014000
109#define XTABS 0014000
110#define BSDLY 0020000
111#define BS0 0000000
112#define BS1 0020000
113#define VTDLY 0040000
114#define VT0 0000000
115#define VT1 0040000
116#define FFDLY 0100000
117#define FF0 0000000
118#define FF1 0100000
119
120/* c_cflag bit meaning */
121#define CBAUD 0010017
122#define B0 0000000 /* hang up */
123#define B50 0000001
124#define B75 0000002
125#define B110 0000003
126#define B134 0000004
127#define B150 0000005
128#define B200 0000006
129#define B300 0000007
130#define B600 0000010
131#define B1200 0000011
132#define B1800 0000012
133#define B2400 0000013
134#define B4800 0000014
135#define B9600 0000015
136#define B19200 0000016
137#define B38400 0000017
138#define EXTA B19200
139#define EXTB B38400
140#define CSIZE 0000060
141#define CS5 0000000
142#define CS6 0000020
143#define CS7 0000040
144#define CS8 0000060
145#define CSTOPB 0000100
146#define CREAD 0000200
147#define PARENB 0000400
148#define PARODD 0001000
149#define HUPCL 0002000
150#define CLOCAL 0004000
151#define CBAUDEX 0010000
152#define BOTHER 0010000
153#define B57600 0010001
154#define B115200 0010002
155#define B230400 0010003
156#define B460800 0010004
157#define B500000 0010005
158#define B576000 0010006
159#define B921600 0010007
160#define B1000000 0010010
161#define B1152000 0010011
162#define B1500000 0010012
163#define B2000000 0010013
164#define B2500000 0010014
165#define B3000000 0010015
166#define B3500000 0010016
167#define B4000000 0010017
168#define CIBAUD 002003600000 /* input baud rate */
169#define CMSPAR 010000000000 /* mark or space (stick) parity */
170#define CRTSCTS 020000000000 /* flow control */
171
172#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
173
174/* c_lflag bits */
175#define ISIG 0000001
176#define ICANON 0000002
177#define XCASE 0000004
178#define ECHO 0000010
179#define ECHOE 0000020
180#define ECHOK 0000040
181#define ECHONL 0000100
182#define NOFLSH 0000200
183#define TOSTOP 0000400
184#define ECHOCTL 0001000
185#define ECHOPRT 0002000
186#define ECHOKE 0004000
187#define FLUSHO 0010000
188#define PENDIN 0040000
189#define IEXTEN 0100000
190
191/* tcflow() and TCXONC use these */
192#define TCOOFF 0
193#define TCOON 1
194#define TCIOFF 2
195#define TCION 3
196
197/* tcflush() and TCFLSH use these */
198#define TCIFLUSH 0
199#define TCOFLUSH 1
200#define TCIOFLUSH 2
201
202/* tcsetattr uses these */
203#define TCSANOW 0
204#define TCSADRAIN 1
205#define TCSAFLUSH 2
206
207#endif /* _ASM_IA64_TERMBITS_H */
diff --git a/arch/ia64/include/asm/termios.h b/arch/ia64/include/asm/termios.h
new file mode 100644
index 000000000000..689d218c0c28
--- /dev/null
+++ b/arch/ia64/include/asm/termios.h
@@ -0,0 +1,97 @@
1#ifndef _ASM_IA64_TERMIOS_H
2#define _ASM_IA64_TERMIOS_H
3
4/*
5 * Modified 1999
6 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
7 *
8 * 99/01/28 Added N_IRDA and N_SMSBLOCK
9 */
10
11#include <asm/termbits.h>
12#include <asm/ioctls.h>
13
14struct winsize {
15 unsigned short ws_row;
16 unsigned short ws_col;
17 unsigned short ws_xpixel;
18 unsigned short ws_ypixel;
19};
20
21#define NCC 8
22struct termio {
23 unsigned short c_iflag; /* input mode flags */
24 unsigned short c_oflag; /* output mode flags */
25 unsigned short c_cflag; /* control mode flags */
26 unsigned short c_lflag; /* local mode flags */
27 unsigned char c_line; /* line discipline */
28 unsigned char c_cc[NCC]; /* control characters */
29};
30
31/* modem lines */
32#define TIOCM_LE 0x001
33#define TIOCM_DTR 0x002
34#define TIOCM_RTS 0x004
35#define TIOCM_ST 0x008
36#define TIOCM_SR 0x010
37#define TIOCM_CTS 0x020
38#define TIOCM_CAR 0x040
39#define TIOCM_RNG 0x080
40#define TIOCM_DSR 0x100
41#define TIOCM_CD TIOCM_CAR
42#define TIOCM_RI TIOCM_RNG
43#define TIOCM_OUT1 0x2000
44#define TIOCM_OUT2 0x4000
45#define TIOCM_LOOP 0x8000
46
47/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
48
49# ifdef __KERNEL__
50
51/* intr=^C quit=^\ erase=del kill=^U
52 eof=^D vtime=\0 vmin=\1 sxtc=\0
53 start=^Q stop=^S susp=^Z eol=\0
54 reprint=^R discard=^U werase=^W lnext=^V
55 eol2=\0
56*/
57#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
58
59/*
60 * Translate a "termio" structure into a "termios". Ugh.
61 */
62#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
63 unsigned short __tmp; \
64 get_user(__tmp,&(termio)->x); \
65 *(unsigned short *) &(termios)->x = __tmp; \
66}
67
68#define user_termio_to_kernel_termios(termios, termio) \
69({ \
70 SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
71 SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
72 SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
73 SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
74 copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
75})
76
77/*
78 * Translate a "termios" structure into a "termio". Ugh.
79 */
80#define kernel_termios_to_user_termio(termio, termios) \
81({ \
82 put_user((termios)->c_iflag, &(termio)->c_iflag); \
83 put_user((termios)->c_oflag, &(termio)->c_oflag); \
84 put_user((termios)->c_cflag, &(termio)->c_cflag); \
85 put_user((termios)->c_lflag, &(termio)->c_lflag); \
86 put_user((termios)->c_line, &(termio)->c_line); \
87 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
88})
89
90#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
91#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
92#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
93#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
94
95# endif /* __KERNEL__ */
96
97#endif /* _ASM_IA64_TERMIOS_H */
diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h
new file mode 100644
index 000000000000..7c60fcdd2efd
--- /dev/null
+++ b/arch/ia64/include/asm/thread_info.h
@@ -0,0 +1,148 @@
1/*
2 * Copyright (C) 2002-2003 Hewlett-Packard Co
3 * David Mosberger-Tang <davidm@hpl.hp.com>
4 */
5#ifndef _ASM_IA64_THREAD_INFO_H
6#define _ASM_IA64_THREAD_INFO_H
7
8#ifndef ASM_OFFSETS_C
9#include <asm/asm-offsets.h>
10#endif
11#include <asm/processor.h>
12#include <asm/ptrace.h>
13
14#define PREEMPT_ACTIVE_BIT 30
15#define PREEMPT_ACTIVE (1 << PREEMPT_ACTIVE_BIT)
16
17#ifndef __ASSEMBLY__
18
19/*
20 * On IA-64, we want to keep the task structure and kernel stack together, so they can be
21 * mapped by a single TLB entry and so they can be addressed by the "current" pointer
22 * without having to do pointer masking.
23 */
24struct thread_info {
25 struct task_struct *task; /* XXX not really needed, except for dup_task_struct() */
26 struct exec_domain *exec_domain;/* execution domain */
27 __u32 flags; /* thread_info flags (see TIF_*) */
28 __u32 cpu; /* current CPU */
29 __u32 last_cpu; /* Last CPU thread ran on */
30 __u32 status; /* Thread synchronous flags */
31 mm_segment_t addr_limit; /* user-level address space limit */
32 int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */
33 struct restart_block restart_block;
34#ifdef CONFIG_VIRT_CPU_ACCOUNTING
35 __u64 ac_stamp;
36 __u64 ac_leave;
37 __u64 ac_stime;
38 __u64 ac_utime;
39#endif
40};
41
42#define THREAD_SIZE KERNEL_STACK_SIZE
43
44#define INIT_THREAD_INFO(tsk) \
45{ \
46 .task = &tsk, \
47 .exec_domain = &default_exec_domain, \
48 .flags = 0, \
49 .cpu = 0, \
50 .addr_limit = KERNEL_DS, \
51 .preempt_count = 0, \
52 .restart_block = { \
53 .fn = do_no_restart_syscall, \
54 }, \
55}
56
57#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
58
59#ifndef ASM_OFFSETS_C
60/* how to get the thread information struct from C */
61#define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE))
62#define alloc_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
63#define task_thread_info(tsk) ((struct thread_info *) ((char *) (tsk) + IA64_TASK_SIZE))
64#else
65#define current_thread_info() ((struct thread_info *) 0)
66#define alloc_thread_info(tsk) ((struct thread_info *) 0)
67#define task_thread_info(tsk) ((struct thread_info *) 0)
68#endif
69#define free_thread_info(ti) /* nothing */
70#define task_stack_page(tsk) ((void *)(tsk))
71
72#define __HAVE_THREAD_FUNCTIONS
73#ifdef CONFIG_VIRT_CPU_ACCOUNTING
74#define setup_thread_stack(p, org) \
75 *task_thread_info(p) = *task_thread_info(org); \
76 task_thread_info(p)->ac_stime = 0; \
77 task_thread_info(p)->ac_utime = 0; \
78 task_thread_info(p)->task = (p);
79#else
80#define setup_thread_stack(p, org) \
81 *task_thread_info(p) = *task_thread_info(org); \
82 task_thread_info(p)->task = (p);
83#endif
84#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
85
86#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
87#define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER))
88#define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER)
89
90#define tsk_set_notify_resume(tsk) \
91 set_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME)
92extern void tsk_clear_notify_resume(struct task_struct *tsk);
93#endif /* !__ASSEMBLY */
94
95/*
96 * thread information flags
97 * - these are process state flags that various assembly files may need to access
98 * - pending work-to-be-done flags are in least-significant 16 bits, other flags
99 * in top 16 bits
100 */
101#define TIF_SIGPENDING 0 /* signal pending */
102#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
103#define TIF_SYSCALL_TRACE 2 /* syscall trace active */
104#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
105#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
106#define TIF_NOTIFY_RESUME 6 /* resumption notification requested */
107#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
108#define TIF_MEMDIE 17
109#define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */
110#define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */
111#define TIF_FREEZE 20 /* is freezing for suspend */
112#define TIF_RESTORE_RSE 21 /* user RBS is newer than kernel RBS */
113
114#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
115#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
116#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
117#define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP)
118#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
119#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
120#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
121#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
122#define _TIF_MCA_INIT (1 << TIF_MCA_INIT)
123#define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED)
124#define _TIF_FREEZE (1 << TIF_FREEZE)
125#define _TIF_RESTORE_RSE (1 << TIF_RESTORE_RSE)
126
127/* "work to do on user-return" bits */
128#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\
129 _TIF_NEED_RESCHED|_TIF_SYSCALL_TRACE)
130/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */
131#define TIF_WORK_MASK (TIF_ALLWORK_MASK&~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT))
132
133#define TS_POLLING 1 /* true if in idle loop and not sleeping */
134#define TS_RESTORE_SIGMASK 2 /* restore signal mask in do_signal() */
135
136#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
137
138#ifndef __ASSEMBLY__
139#define HAVE_SET_RESTORE_SIGMASK 1
140static inline void set_restore_sigmask(void)
141{
142 struct thread_info *ti = current_thread_info();
143 ti->status |= TS_RESTORE_SIGMASK;
144 set_bit(TIF_SIGPENDING, &ti->flags);
145}
146#endif /* !__ASSEMBLY__ */
147
148#endif /* _ASM_IA64_THREAD_INFO_H */
diff --git a/arch/ia64/include/asm/timex.h b/arch/ia64/include/asm/timex.h
new file mode 100644
index 000000000000..05a6baf8a472
--- /dev/null
+++ b/arch/ia64/include/asm/timex.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_IA64_TIMEX_H
2#define _ASM_IA64_TIMEX_H
3
4/*
5 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8/*
9 * 2001/01/18 davidm Removed CLOCK_TICK_RATE. It makes no sense on IA-64.
10 * Also removed cacheflush_time as it's entirely unused.
11 */
12
13#include <asm/intrinsics.h>
14#include <asm/processor.h>
15
16typedef unsigned long cycles_t;
17
18extern void (*ia64_udelay)(unsigned long usecs);
19
20/*
21 * For performance reasons, we don't want to define CLOCK_TICK_TRATE as
22 * local_cpu_data->itc_rate. Fortunately, we don't have to, either: according to George
23 * Anzinger, 1/CLOCK_TICK_RATE is taken as the resolution of the timer clock. The time
24 * calculation assumes that you will use enough of these so that your tick size <= 1/HZ.
25 * If the calculation shows that your CLOCK_TICK_RATE can not supply exactly 1/HZ ticks,
26 * the actual value is calculated and used to update the wall clock each jiffie. Setting
27 * the CLOCK_TICK_RATE to x*HZ insures that the calculation will find no errors. Hence we
28 * pick a multiple of HZ which gives us a (totally virtual) CLOCK_TICK_RATE of about
29 * 100MHz.
30 */
31#define CLOCK_TICK_RATE (HZ * 100000UL)
32
33static inline cycles_t
34get_cycles (void)
35{
36 cycles_t ret;
37
38 ret = ia64_getreg(_IA64_REG_AR_ITC);
39 return ret;
40}
41
42#endif /* _ASM_IA64_TIMEX_H */
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
new file mode 100644
index 000000000000..20d8a39680c2
--- /dev/null
+++ b/arch/ia64/include/asm/tlb.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_IA64_TLB_H
2#define _ASM_IA64_TLB_H
3/*
4 * Based on <asm-generic/tlb.h>.
5 *
6 * Copyright (C) 2002-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
8 */
9/*
10 * Removing a translation from a page table (including TLB-shootdown) is a four-step
11 * procedure:
12 *
13 * (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory
14 * (this is a no-op on ia64).
15 * (2) Clear the relevant portions of the page-table
16 * (3) Flush the TLBs --- ensures that stale content is gone from CPU TLBs
17 * (4) Release the pages that were freed up in step (2).
18 *
19 * Note that the ordering of these steps is crucial to avoid races on MP machines.
20 *
21 * The Linux kernel defines several platform-specific hooks for TLB-shootdown. When
22 * unmapping a portion of the virtual address space, these hooks are called according to
23 * the following template:
24 *
25 * tlb <- tlb_gather_mmu(mm, full_mm_flush); // start unmap for address space MM
26 * {
27 * for each vma that needs a shootdown do {
28 * tlb_start_vma(tlb, vma);
29 * for each page-table-entry PTE that needs to be removed do {
30 * tlb_remove_tlb_entry(tlb, pte, address);
31 * if (pte refers to a normal page) {
32 * tlb_remove_page(tlb, page);
33 * }
34 * }
35 * tlb_end_vma(tlb, vma);
36 * }
37 * }
38 * tlb_finish_mmu(tlb, start, end); // finish unmap for address space MM
39 */
40#include <linux/mm.h>
41#include <linux/pagemap.h>
42#include <linux/swap.h>
43
44#include <asm/pgalloc.h>
45#include <asm/processor.h>
46#include <asm/tlbflush.h>
47#include <asm/machvec.h>
48
49#ifdef CONFIG_SMP
50# define FREE_PTE_NR 2048
51# define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
52#else
53# define FREE_PTE_NR 0
54# define tlb_fast_mode(tlb) (1)
55#endif
56
57struct mmu_gather {
58 struct mm_struct *mm;
59 unsigned int nr; /* == ~0U => fast mode */
60 unsigned char fullmm; /* non-zero means full mm flush */
61 unsigned char need_flush; /* really unmapped some PTEs? */
62 unsigned long start_addr;
63 unsigned long end_addr;
64 struct page *pages[FREE_PTE_NR];
65};
66
67struct ia64_tr_entry {
68 u64 ifa;
69 u64 itir;
70 u64 pte;
71 u64 rr;
72}; /*Record for tr entry!*/
73
74extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
75extern void ia64_ptr_entry(u64 target_mask, int slot);
76
77extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
78
79/*
80 region register macros
81*/
82#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
83#define RR_VE(val) (((val) & 0x0000000000000001) << 0)
84#define RR_VE_MASK 0x0000000000000001L
85#define RR_VE_SHIFT 0
86#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
87#define RR_PS(val) (((val) & 0x000000000000003f) << 2)
88#define RR_PS_MASK 0x00000000000000fcL
89#define RR_PS_SHIFT 2
90#define RR_RID_MASK 0x00000000ffffff00L
91#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
92
93/* Users of the generic TLB shootdown code must declare this storage space. */
94DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
95
96/*
97 * Flush the TLB for address range START to END and, if not in fast mode, release the
98 * freed pages that where gathered up to this point.
99 */
100static inline void
101ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
102{
103 unsigned int nr;
104
105 if (!tlb->need_flush)
106 return;
107 tlb->need_flush = 0;
108
109 if (tlb->fullmm) {
110 /*
111 * Tearing down the entire address space. This happens both as a result
112 * of exit() and execve(). The latter case necessitates the call to
113 * flush_tlb_mm() here.
114 */
115 flush_tlb_mm(tlb->mm);
116 } else if (unlikely (end - start >= 1024*1024*1024*1024UL
117 || REGION_NUMBER(start) != REGION_NUMBER(end - 1)))
118 {
119 /*
120 * If we flush more than a tera-byte or across regions, we're probably
121 * better off just flushing the entire TLB(s). This should be very rare
122 * and is not worth optimizing for.
123 */
124 flush_tlb_all();
125 } else {
126 /*
127 * XXX fix me: flush_tlb_range() should take an mm pointer instead of a
128 * vma pointer.
129 */
130 struct vm_area_struct vma;
131
132 vma.vm_mm = tlb->mm;
133 /* flush the address range from the tlb: */
134 flush_tlb_range(&vma, start, end);
135 /* now flush the virt. page-table area mapping the address range: */
136 flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end));
137 }
138
139 /* lastly, release the freed pages */
140 nr = tlb->nr;
141 if (!tlb_fast_mode(tlb)) {
142 unsigned long i;
143 tlb->nr = 0;
144 tlb->start_addr = ~0UL;
145 for (i = 0; i < nr; ++i)
146 free_page_and_swap_cache(tlb->pages[i]);
147 }
148}
149
150/*
151 * Return a pointer to an initialized struct mmu_gather.
152 */
153static inline struct mmu_gather *
154tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
155{
156 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
157
158 tlb->mm = mm;
159 /*
160 * Use fast mode if only 1 CPU is online.
161 *
162 * It would be tempting to turn on fast-mode for full_mm_flush as well. But this
163 * doesn't work because of speculative accesses and software prefetching: the page
164 * table of "mm" may (and usually is) the currently active page table and even
165 * though the kernel won't do any user-space accesses during the TLB shoot down, a
166 * compiler might use speculation or lfetch.fault on what happens to be a valid
167 * user-space address. This in turn could trigger a TLB miss fault (or a VHPT
168 * walk) and re-insert a TLB entry we just removed. Slow mode avoids such
169 * problems. (We could make fast-mode work by switching the current task to a
170 * different "mm" during the shootdown.) --davidm 08/02/2002
171 */
172 tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
173 tlb->fullmm = full_mm_flush;
174 tlb->start_addr = ~0UL;
175 return tlb;
176}
177
178/*
179 * Called at the end of the shootdown operation to free up any resources that were
180 * collected.
181 */
182static inline void
183tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
184{
185 /*
186 * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
187 * tlb->end_addr.
188 */
189 ia64_tlb_flush_mmu(tlb, start, end);
190
191 /* keep the page table cache within bounds */
192 check_pgt_cache();
193
194 put_cpu_var(mmu_gathers);
195}
196
197/*
198 * Logically, this routine frees PAGE. On MP machines, the actual freeing of the page
199 * must be delayed until after the TLB has been flushed (see comments at the beginning of
200 * this file).
201 */
202static inline void
203tlb_remove_page (struct mmu_gather *tlb, struct page *page)
204{
205 tlb->need_flush = 1;
206
207 if (tlb_fast_mode(tlb)) {
208 free_page_and_swap_cache(page);
209 return;
210 }
211 tlb->pages[tlb->nr++] = page;
212 if (tlb->nr >= FREE_PTE_NR)
213 ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
214}
215
216/*
217 * Remove TLB entry for PTE mapped at virtual address ADDRESS. This is called for any
218 * PTE, not just those pointing to (normal) physical memory.
219 */
220static inline void
221__tlb_remove_tlb_entry (struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
222{
223 if (tlb->start_addr == ~0UL)
224 tlb->start_addr = address;
225 tlb->end_addr = address + PAGE_SIZE;
226}
227
228#define tlb_migrate_finish(mm) platform_tlb_migrate_finish(mm)
229
230#define tlb_start_vma(tlb, vma) do { } while (0)
231#define tlb_end_vma(tlb, vma) do { } while (0)
232
233#define tlb_remove_tlb_entry(tlb, ptep, addr) \
234do { \
235 tlb->need_flush = 1; \
236 __tlb_remove_tlb_entry(tlb, ptep, addr); \
237} while (0)
238
239#define pte_free_tlb(tlb, ptep) \
240do { \
241 tlb->need_flush = 1; \
242 __pte_free_tlb(tlb, ptep); \
243} while (0)
244
245#define pmd_free_tlb(tlb, ptep) \
246do { \
247 tlb->need_flush = 1; \
248 __pmd_free_tlb(tlb, ptep); \
249} while (0)
250
251#define pud_free_tlb(tlb, pudp) \
252do { \
253 tlb->need_flush = 1; \
254 __pud_free_tlb(tlb, pudp); \
255} while (0)
256
257#endif /* _ASM_IA64_TLB_H */
diff --git a/arch/ia64/include/asm/tlbflush.h b/arch/ia64/include/asm/tlbflush.h
new file mode 100644
index 000000000000..3be25dfed164
--- /dev/null
+++ b/arch/ia64/include/asm/tlbflush.h
@@ -0,0 +1,102 @@
1#ifndef _ASM_IA64_TLBFLUSH_H
2#define _ASM_IA64_TLBFLUSH_H
3
4/*
5 * Copyright (C) 2002 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
8
9
10#include <linux/mm.h>
11
12#include <asm/intrinsics.h>
13#include <asm/mmu_context.h>
14#include <asm/page.h>
15
16/*
17 * Now for some TLB flushing routines. This is the kind of stuff that
18 * can be very expensive, so try to avoid them whenever possible.
19 */
20extern void setup_ptcg_sem(int max_purges, int from_palo);
21
22/*
23 * Flush everything (kernel mapping may also have changed due to
24 * vmalloc/vfree).
25 */
26extern void local_flush_tlb_all (void);
27
28#ifdef CONFIG_SMP
29 extern void smp_flush_tlb_all (void);
30 extern void smp_flush_tlb_mm (struct mm_struct *mm);
31 extern void smp_flush_tlb_cpumask (cpumask_t xcpumask);
32# define flush_tlb_all() smp_flush_tlb_all()
33#else
34# define flush_tlb_all() local_flush_tlb_all()
35# define smp_flush_tlb_cpumask(m) local_flush_tlb_all()
36#endif
37
38static inline void
39local_finish_flush_tlb_mm (struct mm_struct *mm)
40{
41 if (mm == current->active_mm)
42 activate_context(mm);
43}
44
45/*
46 * Flush a specified user mapping. This is called, e.g., as a result of fork() and
47 * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect
48 * the PTEs of the parent task.
49 */
50static inline void
51flush_tlb_mm (struct mm_struct *mm)
52{
53 if (!mm)
54 return;
55
56 set_bit(mm->context, ia64_ctx.flushmap);
57 mm->context = 0;
58
59 if (atomic_read(&mm->mm_users) == 0)
60 return; /* happens as a result of exit_mmap() */
61
62#ifdef CONFIG_SMP
63 smp_flush_tlb_mm(mm);
64#else
65 local_finish_flush_tlb_mm(mm);
66#endif
67}
68
69extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end);
70
71/*
72 * Page-granular tlb flush.
73 */
74static inline void
75flush_tlb_page (struct vm_area_struct *vma, unsigned long addr)
76{
77#ifdef CONFIG_SMP
78 flush_tlb_range(vma, (addr & PAGE_MASK), (addr & PAGE_MASK) + PAGE_SIZE);
79#else
80 if (vma->vm_mm == current->active_mm)
81 ia64_ptcl(addr, (PAGE_SHIFT << 2));
82 else
83 vma->vm_mm->context = 0;
84#endif
85}
86
87/*
88 * Flush the local TLB. Invoked from another cpu using an IPI.
89 */
90#ifdef CONFIG_SMP
91void smp_local_flush_tlb(void);
92#else
93#define smp_local_flush_tlb()
94#endif
95
96static inline void flush_tlb_kernel_range(unsigned long start,
97 unsigned long end)
98{
99 flush_tlb_all(); /* XXX fix me */
100}
101
102#endif /* _ASM_IA64_TLBFLUSH_H */
diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h
new file mode 100644
index 000000000000..35bcb641c9e5
--- /dev/null
+++ b/arch/ia64/include/asm/topology.h
@@ -0,0 +1,126 @@
1/*
2 * Copyright (C) 2002, Erich Focht, NEC
3 *
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11#ifndef _ASM_IA64_TOPOLOGY_H
12#define _ASM_IA64_TOPOLOGY_H
13
14#include <asm/acpi.h>
15#include <asm/numa.h>
16#include <asm/smp.h>
17
18#ifdef CONFIG_NUMA
19
20/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
21#define PENALTY_FOR_NODE_WITH_CPUS 255
22
23/*
24 * Distance above which we begin to use zone reclaim
25 */
26#define RECLAIM_DISTANCE 15
27
28/*
29 * Returns the number of the node containing CPU 'cpu'
30 */
31#define cpu_to_node(cpu) (int)(cpu_to_node_map[cpu])
32
33/*
34 * Returns a bitmask of CPUs on Node 'node'.
35 */
36#define node_to_cpumask(node) (node_to_cpu_mask[node])
37
38/*
39 * Returns the number of the node containing Node 'nid'.
40 * Not implemented here. Multi-level hierarchies detected with
41 * the help of node_distance().
42 */
43#define parent_node(nid) (nid)
44
45/*
46 * Returns the number of the first CPU on Node 'node'.
47 */
48#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
49
50/*
51 * Determines the node for a given pci bus
52 */
53#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
54
55void build_cpu_to_node_map(void);
56
57#define SD_CPU_INIT (struct sched_domain) { \
58 .span = CPU_MASK_NONE, \
59 .parent = NULL, \
60 .child = NULL, \
61 .groups = NULL, \
62 .min_interval = 1, \
63 .max_interval = 4, \
64 .busy_factor = 64, \
65 .imbalance_pct = 125, \
66 .cache_nice_tries = 2, \
67 .busy_idx = 2, \
68 .idle_idx = 1, \
69 .newidle_idx = 2, \
70 .wake_idx = 1, \
71 .forkexec_idx = 1, \
72 .flags = SD_LOAD_BALANCE \
73 | SD_BALANCE_NEWIDLE \
74 | SD_BALANCE_EXEC \
75 | SD_WAKE_AFFINE, \
76 .last_balance = jiffies, \
77 .balance_interval = 1, \
78 .nr_balance_failed = 0, \
79}
80
81/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
82#define SD_NODE_INIT (struct sched_domain) { \
83 .span = CPU_MASK_NONE, \
84 .parent = NULL, \
85 .child = NULL, \
86 .groups = NULL, \
87 .min_interval = 8, \
88 .max_interval = 8*(min(num_online_cpus(), 32)), \
89 .busy_factor = 64, \
90 .imbalance_pct = 125, \
91 .cache_nice_tries = 2, \
92 .busy_idx = 3, \
93 .idle_idx = 2, \
94 .newidle_idx = 2, \
95 .wake_idx = 1, \
96 .forkexec_idx = 1, \
97 .flags = SD_LOAD_BALANCE \
98 | SD_BALANCE_EXEC \
99 | SD_BALANCE_FORK \
100 | SD_SERIALIZE \
101 | SD_WAKE_BALANCE, \
102 .last_balance = jiffies, \
103 .balance_interval = 64, \
104 .nr_balance_failed = 0, \
105}
106
107#endif /* CONFIG_NUMA */
108
109#ifdef CONFIG_SMP
110#define topology_physical_package_id(cpu) (cpu_data(cpu)->socket_id)
111#define topology_core_id(cpu) (cpu_data(cpu)->core_id)
112#define topology_core_siblings(cpu) (cpu_core_map[cpu])
113#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
114#define smt_capable() (smp_num_siblings > 1)
115#endif
116
117extern void arch_fix_phys_package_id(int num, u32 slot);
118
119#define pcibus_to_cpumask(bus) (pcibus_to_node(bus) == -1 ? \
120 CPU_MASK_ALL : \
121 node_to_cpumask(pcibus_to_node(bus)) \
122 )
123
124#include <asm-generic/topology.h>
125
126#endif /* _ASM_IA64_TOPOLOGY_H */
diff --git a/arch/ia64/include/asm/types.h b/arch/ia64/include/asm/types.h
new file mode 100644
index 000000000000..e36b3716e718
--- /dev/null
+++ b/arch/ia64/include/asm/types.h
@@ -0,0 +1,46 @@
1#ifndef _ASM_IA64_TYPES_H
2#define _ASM_IA64_TYPES_H
3
4/*
5 * This file is never included by application software unless explicitly requested (e.g.,
6 * via linux/types.h) in which case the application is Linux specific so (user-) name
7 * space pollution is not a major issue. However, for interoperability, libraries still
8 * need to be careful to avoid a name clashes.
9 *
10 * Based on <asm-alpha/types.h>.
11 *
12 * Modified 1998-2000, 2002
13 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
14 */
15
16#include <asm-generic/int-l64.h>
17
18#ifdef __ASSEMBLY__
19# define __IA64_UL(x) (x)
20# define __IA64_UL_CONST(x) x
21
22# ifdef __KERNEL__
23# define BITS_PER_LONG 64
24# endif
25
26#else
27# define __IA64_UL(x) ((unsigned long)(x))
28# define __IA64_UL_CONST(x) x##UL
29
30typedef unsigned int umode_t;
31
32/*
33 * These aren't exported outside the kernel to avoid name space clashes
34 */
35# ifdef __KERNEL__
36
37#define BITS_PER_LONG 64
38
39/* DMA addresses are 64-bits wide, in general. */
40
41typedef u64 dma_addr_t;
42
43# endif /* __KERNEL__ */
44#endif /* !__ASSEMBLY__ */
45
46#endif /* _ASM_IA64_TYPES_H */
diff --git a/arch/ia64/include/asm/uaccess.h b/arch/ia64/include/asm/uaccess.h
new file mode 100644
index 000000000000..449c8c0fa2bd
--- /dev/null
+++ b/arch/ia64/include/asm/uaccess.h
@@ -0,0 +1,401 @@
1#ifndef _ASM_IA64_UACCESS_H
2#define _ASM_IA64_UACCESS_H
3
4/*
5 * This file defines various macros to transfer memory areas across
6 * the user/kernel boundary. This needs to be done carefully because
7 * this code is executed in kernel mode and uses user-specified
8 * addresses. Thus, we need to be careful not to let the user to
9 * trick us into accessing kernel memory that would normally be
10 * inaccessible. This code is also fairly performance sensitive,
11 * so we want to spend as little time doing safety checks as
12 * possible.
13 *
14 * To make matters a bit more interesting, these macros sometimes also
15 * called from within the kernel itself, in which case the address
16 * validity check must be skipped. The get_fs() macro tells us what
17 * to do: if get_fs()==USER_DS, checking is performed, if
18 * get_fs()==KERNEL_DS, checking is bypassed.
19 *
20 * Note that even if the memory area specified by the user is in a
21 * valid address range, it is still possible that we'll get a page
22 * fault while accessing it. This is handled by filling out an
23 * exception handler fixup entry for each instruction that has the
24 * potential to fault. When such a fault occurs, the page fault
25 * handler checks to see whether the faulting instruction has a fixup
26 * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and
27 * then resumes execution at the continuation point.
28 *
29 * Based on <asm-alpha/uaccess.h>.
30 *
31 * Copyright (C) 1998, 1999, 2001-2004 Hewlett-Packard Co
32 * David Mosberger-Tang <davidm@hpl.hp.com>
33 */
34
35#include <linux/compiler.h>
36#include <linux/errno.h>
37#include <linux/sched.h>
38#include <linux/page-flags.h>
39#include <linux/mm.h>
40
41#include <asm/intrinsics.h>
42#include <asm/pgtable.h>
43#include <asm/io.h>
44
45/*
46 * For historical reasons, the following macros are grossly misnamed:
47 */
48#define KERNEL_DS ((mm_segment_t) { ~0UL }) /* cf. access_ok() */
49#define USER_DS ((mm_segment_t) { TASK_SIZE-1 }) /* cf. access_ok() */
50
51#define VERIFY_READ 0
52#define VERIFY_WRITE 1
53
54#define get_ds() (KERNEL_DS)
55#define get_fs() (current_thread_info()->addr_limit)
56#define set_fs(x) (current_thread_info()->addr_limit = (x))
57
58#define segment_eq(a, b) ((a).seg == (b).seg)
59
60/*
61 * When accessing user memory, we need to make sure the entire area really is in
62 * user-level space. In order to do this efficiently, we make sure that the page at
63 * address TASK_SIZE is never valid. We also need to make sure that the address doesn't
64 * point inside the virtually mapped linear page table.
65 */
66#define __access_ok(addr, size, segment) \
67({ \
68 __chk_user_ptr(addr); \
69 (likely((unsigned long) (addr) <= (segment).seg) \
70 && ((segment).seg == KERNEL_DS.seg \
71 || likely(REGION_OFFSET((unsigned long) (addr)) < RGN_MAP_LIMIT))); \
72})
73#define access_ok(type, addr, size) __access_ok((addr), (size), get_fs())
74
75/*
76 * These are the main single-value transfer routines. They automatically
77 * use the right size if we just have the right pointer type.
78 *
79 * Careful to not
80 * (a) re-use the arguments for side effects (sizeof/typeof is ok)
81 * (b) require any knowledge of processes at this stage
82 */
83#define put_user(x, ptr) __put_user_check((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)), get_fs())
84#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr)), get_fs())
85
86/*
87 * The "__xxx" versions do not do address space checking, useful when
88 * doing multiple accesses to the same area (the programmer has to do the
89 * checks by hand with "access_ok()")
90 */
91#define __put_user(x, ptr) __put_user_nocheck((__typeof__(*(ptr))) (x), (ptr), sizeof(*(ptr)))
92#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
93
94extern long __put_user_unaligned_unknown (void);
95
96#define __put_user_unaligned(x, ptr) \
97({ \
98 long __ret; \
99 switch (sizeof(*(ptr))) { \
100 case 1: __ret = __put_user((x), (ptr)); break; \
101 case 2: __ret = (__put_user((x), (u8 __user *)(ptr))) \
102 | (__put_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break; \
103 case 4: __ret = (__put_user((x), (u16 __user *)(ptr))) \
104 | (__put_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break; \
105 case 8: __ret = (__put_user((x), (u32 __user *)(ptr))) \
106 | (__put_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break; \
107 default: __ret = __put_user_unaligned_unknown(); \
108 } \
109 __ret; \
110})
111
112extern long __get_user_unaligned_unknown (void);
113
114#define __get_user_unaligned(x, ptr) \
115({ \
116 long __ret; \
117 switch (sizeof(*(ptr))) { \
118 case 1: __ret = __get_user((x), (ptr)); break; \
119 case 2: __ret = (__get_user((x), (u8 __user *)(ptr))) \
120 | (__get_user((x) >> 8, ((u8 __user *)(ptr) + 1))); break; \
121 case 4: __ret = (__get_user((x), (u16 __user *)(ptr))) \
122 | (__get_user((x) >> 16, ((u16 __user *)(ptr) + 1))); break; \
123 case 8: __ret = (__get_user((x), (u32 __user *)(ptr))) \
124 | (__get_user((x) >> 32, ((u32 __user *)(ptr) + 1))); break; \
125 default: __ret = __get_user_unaligned_unknown(); \
126 } \
127 __ret; \
128})
129
130#ifdef ASM_SUPPORTED
131 struct __large_struct { unsigned long buf[100]; };
132# define __m(x) (*(struct __large_struct __user *)(x))
133
134/* We need to declare the __ex_table section before we can use it in .xdata. */
135asm (".section \"__ex_table\", \"a\"\n\t.previous");
136
137# define __get_user_size(val, addr, n, err) \
138do { \
139 register long __gu_r8 asm ("r8") = 0; \
140 register long __gu_r9 asm ("r9"); \
141 asm ("\n[1:]\tld"#n" %0=%2%P2\t// %0 and %1 get overwritten by exception handler\n" \
142 "\t.xdata4 \"__ex_table\", 1b-., 1f-.+4\n" \
143 "[1:]" \
144 : "=r"(__gu_r9), "=r"(__gu_r8) : "m"(__m(addr)), "1"(__gu_r8)); \
145 (err) = __gu_r8; \
146 (val) = __gu_r9; \
147} while (0)
148
149/*
150 * The "__put_user_size()" macro tells gcc it reads from memory instead of writing it. This
151 * is because they do not write to any memory gcc knows about, so there are no aliasing
152 * issues.
153 */
154# define __put_user_size(val, addr, n, err) \
155do { \
156 register long __pu_r8 asm ("r8") = 0; \
157 asm volatile ("\n[1:]\tst"#n" %1=%r2%P1\t// %0 gets overwritten by exception handler\n" \
158 "\t.xdata4 \"__ex_table\", 1b-., 1f-.\n" \
159 "[1:]" \
160 : "=r"(__pu_r8) : "m"(__m(addr)), "rO"(val), "0"(__pu_r8)); \
161 (err) = __pu_r8; \
162} while (0)
163
164#else /* !ASM_SUPPORTED */
165# define RELOC_TYPE 2 /* ip-rel */
166# define __get_user_size(val, addr, n, err) \
167do { \
168 __ld_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE); \
169 (err) = ia64_getreg(_IA64_REG_R8); \
170 (val) = ia64_getreg(_IA64_REG_R9); \
171} while (0)
172# define __put_user_size(val, addr, n, err) \
173do { \
174 __st_user("__ex_table", (unsigned long) addr, n, RELOC_TYPE, (unsigned long) (val)); \
175 (err) = ia64_getreg(_IA64_REG_R8); \
176} while (0)
177#endif /* !ASM_SUPPORTED */
178
179extern void __get_user_unknown (void);
180
181/*
182 * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
183 * could clobber r8 and r9 (among others). Thus, be careful not to evaluate it while
184 * using r8/r9.
185 */
186#define __do_get_user(check, x, ptr, size, segment) \
187({ \
188 const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \
189 __typeof__ (size) __gu_size = (size); \
190 long __gu_err = -EFAULT; \
191 unsigned long __gu_val = 0; \
192 if (!check || __access_ok(__gu_ptr, size, segment)) \
193 switch (__gu_size) { \
194 case 1: __get_user_size(__gu_val, __gu_ptr, 1, __gu_err); break; \
195 case 2: __get_user_size(__gu_val, __gu_ptr, 2, __gu_err); break; \
196 case 4: __get_user_size(__gu_val, __gu_ptr, 4, __gu_err); break; \
197 case 8: __get_user_size(__gu_val, __gu_ptr, 8, __gu_err); break; \
198 default: __get_user_unknown(); break; \
199 } \
200 (x) = (__typeof__(*(__gu_ptr))) __gu_val; \
201 __gu_err; \
202})
203
204#define __get_user_nocheck(x, ptr, size) __do_get_user(0, x, ptr, size, KERNEL_DS)
205#define __get_user_check(x, ptr, size, segment) __do_get_user(1, x, ptr, size, segment)
206
207extern void __put_user_unknown (void);
208
209/*
210 * Evaluating arguments X, PTR, SIZE, and SEGMENT may involve subroutine-calls, which
211 * could clobber r8 (among others). Thus, be careful not to evaluate them while using r8.
212 */
213#define __do_put_user(check, x, ptr, size, segment) \
214({ \
215 __typeof__ (x) __pu_x = (x); \
216 __typeof__ (*(ptr)) __user *__pu_ptr = (ptr); \
217 __typeof__ (size) __pu_size = (size); \
218 long __pu_err = -EFAULT; \
219 \
220 if (!check || __access_ok(__pu_ptr, __pu_size, segment)) \
221 switch (__pu_size) { \
222 case 1: __put_user_size(__pu_x, __pu_ptr, 1, __pu_err); break; \
223 case 2: __put_user_size(__pu_x, __pu_ptr, 2, __pu_err); break; \
224 case 4: __put_user_size(__pu_x, __pu_ptr, 4, __pu_err); break; \
225 case 8: __put_user_size(__pu_x, __pu_ptr, 8, __pu_err); break; \
226 default: __put_user_unknown(); break; \
227 } \
228 __pu_err; \
229})
230
231#define __put_user_nocheck(x, ptr, size) __do_put_user(0, x, ptr, size, KERNEL_DS)
232#define __put_user_check(x, ptr, size, segment) __do_put_user(1, x, ptr, size, segment)
233
234/*
235 * Complex access routines
236 */
237extern unsigned long __must_check __copy_user (void __user *to, const void __user *from,
238 unsigned long count);
239
240static inline unsigned long
241__copy_to_user (void __user *to, const void *from, unsigned long count)
242{
243 return __copy_user(to, (__force void __user *) from, count);
244}
245
246static inline unsigned long
247__copy_from_user (void *to, const void __user *from, unsigned long count)
248{
249 return __copy_user((__force void __user *) to, from, count);
250}
251
252#define __copy_to_user_inatomic __copy_to_user
253#define __copy_from_user_inatomic __copy_from_user
254#define copy_to_user(to, from, n) \
255({ \
256 void __user *__cu_to = (to); \
257 const void *__cu_from = (from); \
258 long __cu_len = (n); \
259 \
260 if (__access_ok(__cu_to, __cu_len, get_fs())) \
261 __cu_len = __copy_user(__cu_to, (__force void __user *) __cu_from, __cu_len); \
262 __cu_len; \
263})
264
265#define copy_from_user(to, from, n) \
266({ \
267 void *__cu_to = (to); \
268 const void __user *__cu_from = (from); \
269 long __cu_len = (n); \
270 \
271 __chk_user_ptr(__cu_from); \
272 if (__access_ok(__cu_from, __cu_len, get_fs())) \
273 __cu_len = __copy_user((__force void __user *) __cu_to, __cu_from, __cu_len); \
274 __cu_len; \
275})
276
277#define __copy_in_user(to, from, size) __copy_user((to), (from), (size))
278
279static inline unsigned long
280copy_in_user (void __user *to, const void __user *from, unsigned long n)
281{
282 if (likely(access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)))
283 n = __copy_user(to, from, n);
284 return n;
285}
286
287extern unsigned long __do_clear_user (void __user *, unsigned long);
288
289#define __clear_user(to, n) __do_clear_user(to, n)
290
291#define clear_user(to, n) \
292({ \
293 unsigned long __cu_len = (n); \
294 if (__access_ok(to, __cu_len, get_fs())) \
295 __cu_len = __do_clear_user(to, __cu_len); \
296 __cu_len; \
297})
298
299
300/*
301 * Returns: -EFAULT if exception before terminator, N if the entire buffer filled, else
302 * strlen.
303 */
304extern long __must_check __strncpy_from_user (char *to, const char __user *from, long to_len);
305
306#define strncpy_from_user(to, from, n) \
307({ \
308 const char __user * __sfu_from = (from); \
309 long __sfu_ret = -EFAULT; \
310 if (__access_ok(__sfu_from, 0, get_fs())) \
311 __sfu_ret = __strncpy_from_user((to), __sfu_from, (n)); \
312 __sfu_ret; \
313})
314
315/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
316extern unsigned long __strlen_user (const char __user *);
317
318#define strlen_user(str) \
319({ \
320 const char __user *__su_str = (str); \
321 unsigned long __su_ret = 0; \
322 if (__access_ok(__su_str, 0, get_fs())) \
323 __su_ret = __strlen_user(__su_str); \
324 __su_ret; \
325})
326
327/*
328 * Returns: 0 if exception before NUL or reaching the supplied limit
329 * (N), a value greater than N if the limit would be exceeded, else
330 * strlen.
331 */
332extern unsigned long __strnlen_user (const char __user *, long);
333
334#define strnlen_user(str, len) \
335({ \
336 const char __user *__su_str = (str); \
337 unsigned long __su_ret = 0; \
338 if (__access_ok(__su_str, 0, get_fs())) \
339 __su_ret = __strnlen_user(__su_str, len); \
340 __su_ret; \
341})
342
343/* Generic code can't deal with the location-relative format that we use for compactness. */
344#define ARCH_HAS_SORT_EXTABLE
345#define ARCH_HAS_SEARCH_EXTABLE
346
347struct exception_table_entry {
348 int addr; /* location-relative address of insn this fixup is for */
349 int cont; /* location-relative continuation addr.; if bit 2 is set, r9 is set to 0 */
350};
351
352extern void ia64_handle_exception (struct pt_regs *regs, const struct exception_table_entry *e);
353extern const struct exception_table_entry *search_exception_tables (unsigned long addr);
354
355static inline int
356ia64_done_with_exception (struct pt_regs *regs)
357{
358 const struct exception_table_entry *e;
359 e = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
360 if (e) {
361 ia64_handle_exception(regs, e);
362 return 1;
363 }
364 return 0;
365}
366
367#define ARCH_HAS_TRANSLATE_MEM_PTR 1
368static __inline__ char *
369xlate_dev_mem_ptr (unsigned long p)
370{
371 struct page *page;
372 char * ptr;
373
374 page = pfn_to_page(p >> PAGE_SHIFT);
375 if (PageUncached(page))
376 ptr = (char *)p + __IA64_UNCACHED_OFFSET;
377 else
378 ptr = __va(p);
379
380 return ptr;
381}
382
383/*
384 * Convert a virtual cached kernel memory pointer to an uncached pointer
385 */
386static __inline__ char *
387xlate_dev_kmem_ptr (char * p)
388{
389 struct page *page;
390 char * ptr;
391
392 page = virt_to_page((unsigned long)p);
393 if (PageUncached(page))
394 ptr = (char *)__pa(p) + __IA64_UNCACHED_OFFSET;
395 else
396 ptr = p;
397
398 return ptr;
399}
400
401#endif /* _ASM_IA64_UACCESS_H */
diff --git a/arch/ia64/include/asm/ucontext.h b/arch/ia64/include/asm/ucontext.h
new file mode 100644
index 000000000000..bf573dc8ca6a
--- /dev/null
+++ b/arch/ia64/include/asm/ucontext.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_IA64_UCONTEXT_H
2#define _ASM_IA64_UCONTEXT_H
3
4struct ucontext {
5 struct sigcontext uc_mcontext;
6};
7
8#define uc_link uc_mcontext.sc_gr[0] /* wrong type; nobody cares */
9#define uc_sigmask uc_mcontext.sc_sigmask
10#define uc_stack uc_mcontext.sc_stack
11
12#endif /* _ASM_IA64_UCONTEXT_H */
diff --git a/arch/ia64/include/asm/unaligned.h b/arch/ia64/include/asm/unaligned.h
new file mode 100644
index 000000000000..7bddc7f58584
--- /dev/null
+++ b/arch/ia64/include/asm/unaligned.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_IA64_UNALIGNED_H
2#define _ASM_IA64_UNALIGNED_H
3
4#include <linux/unaligned/le_struct.h>
5#include <linux/unaligned/be_byteshift.h>
6#include <linux/unaligned/generic.h>
7
8#define get_unaligned __get_unaligned_le
9#define put_unaligned __put_unaligned_le
10
11#endif /* _ASM_IA64_UNALIGNED_H */
diff --git a/arch/ia64/include/asm/uncached.h b/arch/ia64/include/asm/uncached.h
new file mode 100644
index 000000000000..13d7e65ca3cc
--- /dev/null
+++ b/arch/ia64/include/asm/uncached.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright (C) 2001-2008 Silicon Graphics, Inc. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * Prototypes for the uncached page allocator
9 */
10
11extern unsigned long uncached_alloc_page(int starting_nid, int n_pages);
12extern void uncached_free_page(unsigned long uc_addr, int n_pages);
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
new file mode 100644
index 000000000000..d535833aab5e
--- /dev/null
+++ b/arch/ia64/include/asm/unistd.h
@@ -0,0 +1,384 @@
1#ifndef _ASM_IA64_UNISTD_H
2#define _ASM_IA64_UNISTD_H
3
4/*
5 * IA-64 Linux syscall numbers and inline-functions.
6 *
7 * Copyright (C) 1998-2005 Hewlett-Packard Co
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 */
10
11#include <asm/break.h>
12
13#define __BREAK_SYSCALL __IA64_BREAK_SYSCALL
14
15#define __NR_ni_syscall 1024
16#define __NR_exit 1025
17#define __NR_read 1026
18#define __NR_write 1027
19#define __NR_open 1028
20#define __NR_close 1029
21#define __NR_creat 1030
22#define __NR_link 1031
23#define __NR_unlink 1032
24#define __NR_execve 1033
25#define __NR_chdir 1034
26#define __NR_fchdir 1035
27#define __NR_utimes 1036
28#define __NR_mknod 1037
29#define __NR_chmod 1038
30#define __NR_chown 1039
31#define __NR_lseek 1040
32#define __NR_getpid 1041
33#define __NR_getppid 1042
34#define __NR_mount 1043
35#define __NR_umount 1044
36#define __NR_setuid 1045
37#define __NR_getuid 1046
38#define __NR_geteuid 1047
39#define __NR_ptrace 1048
40#define __NR_access 1049
41#define __NR_sync 1050
42#define __NR_fsync 1051
43#define __NR_fdatasync 1052
44#define __NR_kill 1053
45#define __NR_rename 1054
46#define __NR_mkdir 1055
47#define __NR_rmdir 1056
48#define __NR_dup 1057
49#define __NR_pipe 1058
50#define __NR_times 1059
51#define __NR_brk 1060
52#define __NR_setgid 1061
53#define __NR_getgid 1062
54#define __NR_getegid 1063
55#define __NR_acct 1064
56#define __NR_ioctl 1065
57#define __NR_fcntl 1066
58#define __NR_umask 1067
59#define __NR_chroot 1068
60#define __NR_ustat 1069
61#define __NR_dup2 1070
62#define __NR_setreuid 1071
63#define __NR_setregid 1072
64#define __NR_getresuid 1073
65#define __NR_setresuid 1074
66#define __NR_getresgid 1075
67#define __NR_setresgid 1076
68#define __NR_getgroups 1077
69#define __NR_setgroups 1078
70#define __NR_getpgid 1079
71#define __NR_setpgid 1080
72#define __NR_setsid 1081
73#define __NR_getsid 1082
74#define __NR_sethostname 1083
75#define __NR_setrlimit 1084
76#define __NR_getrlimit 1085
77#define __NR_getrusage 1086
78#define __NR_gettimeofday 1087
79#define __NR_settimeofday 1088
80#define __NR_select 1089
81#define __NR_poll 1090
82#define __NR_symlink 1091
83#define __NR_readlink 1092
84#define __NR_uselib 1093
85#define __NR_swapon 1094
86#define __NR_swapoff 1095
87#define __NR_reboot 1096
88#define __NR_truncate 1097
89#define __NR_ftruncate 1098
90#define __NR_fchmod 1099
91#define __NR_fchown 1100
92#define __NR_getpriority 1101
93#define __NR_setpriority 1102
94#define __NR_statfs 1103
95#define __NR_fstatfs 1104
96#define __NR_gettid 1105
97#define __NR_semget 1106
98#define __NR_semop 1107
99#define __NR_semctl 1108
100#define __NR_msgget 1109
101#define __NR_msgsnd 1110
102#define __NR_msgrcv 1111
103#define __NR_msgctl 1112
104#define __NR_shmget 1113
105#define __NR_shmat 1114
106#define __NR_shmdt 1115
107#define __NR_shmctl 1116
108/* also known as klogctl() in GNU libc: */
109#define __NR_syslog 1117
110#define __NR_setitimer 1118
111#define __NR_getitimer 1119
112/* 1120 was __NR_old_stat */
113/* 1121 was __NR_old_lstat */
114/* 1122 was __NR_old_fstat */
115#define __NR_vhangup 1123
116#define __NR_lchown 1124
117#define __NR_remap_file_pages 1125
118#define __NR_wait4 1126
119#define __NR_sysinfo 1127
120#define __NR_clone 1128
121#define __NR_setdomainname 1129
122#define __NR_uname 1130
123#define __NR_adjtimex 1131
124/* 1132 was __NR_create_module */
125#define __NR_init_module 1133
126#define __NR_delete_module 1134
127/* 1135 was __NR_get_kernel_syms */
128/* 1136 was __NR_query_module */
129#define __NR_quotactl 1137
130#define __NR_bdflush 1138
131#define __NR_sysfs 1139
132#define __NR_personality 1140
133#define __NR_afs_syscall 1141
134#define __NR_setfsuid 1142
135#define __NR_setfsgid 1143
136#define __NR_getdents 1144
137#define __NR_flock 1145
138#define __NR_readv 1146
139#define __NR_writev 1147
140#define __NR_pread64 1148
141#define __NR_pwrite64 1149
142#define __NR__sysctl 1150
143#define __NR_mmap 1151
144#define __NR_munmap 1152
145#define __NR_mlock 1153
146#define __NR_mlockall 1154
147#define __NR_mprotect 1155
148#define __NR_mremap 1156
149#define __NR_msync 1157
150#define __NR_munlock 1158
151#define __NR_munlockall 1159
152#define __NR_sched_getparam 1160
153#define __NR_sched_setparam 1161
154#define __NR_sched_getscheduler 1162
155#define __NR_sched_setscheduler 1163
156#define __NR_sched_yield 1164
157#define __NR_sched_get_priority_max 1165
158#define __NR_sched_get_priority_min 1166
159#define __NR_sched_rr_get_interval 1167
160#define __NR_nanosleep 1168
161#define __NR_nfsservctl 1169
162#define __NR_prctl 1170
163/* 1171 is reserved for backwards compatibility with old __NR_getpagesize */
164#define __NR_mmap2 1172
165#define __NR_pciconfig_read 1173
166#define __NR_pciconfig_write 1174
167#define __NR_perfmonctl 1175
168#define __NR_sigaltstack 1176
169#define __NR_rt_sigaction 1177
170#define __NR_rt_sigpending 1178
171#define __NR_rt_sigprocmask 1179
172#define __NR_rt_sigqueueinfo 1180
173#define __NR_rt_sigreturn 1181
174#define __NR_rt_sigsuspend 1182
175#define __NR_rt_sigtimedwait 1183
176#define __NR_getcwd 1184
177#define __NR_capget 1185
178#define __NR_capset 1186
179#define __NR_sendfile 1187
180#define __NR_getpmsg 1188
181#define __NR_putpmsg 1189
182#define __NR_socket 1190
183#define __NR_bind 1191
184#define __NR_connect 1192
185#define __NR_listen 1193
186#define __NR_accept 1194
187#define __NR_getsockname 1195
188#define __NR_getpeername 1196
189#define __NR_socketpair 1197
190#define __NR_send 1198
191#define __NR_sendto 1199
192#define __NR_recv 1200
193#define __NR_recvfrom 1201
194#define __NR_shutdown 1202
195#define __NR_setsockopt 1203
196#define __NR_getsockopt 1204
197#define __NR_sendmsg 1205
198#define __NR_recvmsg 1206
199#define __NR_pivot_root 1207
200#define __NR_mincore 1208
201#define __NR_madvise 1209
202#define __NR_stat 1210
203#define __NR_lstat 1211
204#define __NR_fstat 1212
205#define __NR_clone2 1213
206#define __NR_getdents64 1214
207#define __NR_getunwind 1215
208#define __NR_readahead 1216
209#define __NR_setxattr 1217
210#define __NR_lsetxattr 1218
211#define __NR_fsetxattr 1219
212#define __NR_getxattr 1220
213#define __NR_lgetxattr 1221
214#define __NR_fgetxattr 1222
215#define __NR_listxattr 1223
216#define __NR_llistxattr 1224
217#define __NR_flistxattr 1225
218#define __NR_removexattr 1226
219#define __NR_lremovexattr 1227
220#define __NR_fremovexattr 1228
221#define __NR_tkill 1229
222#define __NR_futex 1230
223#define __NR_sched_setaffinity 1231
224#define __NR_sched_getaffinity 1232
225#define __NR_set_tid_address 1233
226#define __NR_fadvise64 1234
227#define __NR_tgkill 1235
228#define __NR_exit_group 1236
229#define __NR_lookup_dcookie 1237
230#define __NR_io_setup 1238
231#define __NR_io_destroy 1239
232#define __NR_io_getevents 1240
233#define __NR_io_submit 1241
234#define __NR_io_cancel 1242
235#define __NR_epoll_create 1243
236#define __NR_epoll_ctl 1244
237#define __NR_epoll_wait 1245
238#define __NR_restart_syscall 1246
239#define __NR_semtimedop 1247
240#define __NR_timer_create 1248
241#define __NR_timer_settime 1249
242#define __NR_timer_gettime 1250
243#define __NR_timer_getoverrun 1251
244#define __NR_timer_delete 1252
245#define __NR_clock_settime 1253
246#define __NR_clock_gettime 1254
247#define __NR_clock_getres 1255
248#define __NR_clock_nanosleep 1256
249#define __NR_fstatfs64 1257
250#define __NR_statfs64 1258
251#define __NR_mbind 1259
252#define __NR_get_mempolicy 1260
253#define __NR_set_mempolicy 1261
254#define __NR_mq_open 1262
255#define __NR_mq_unlink 1263
256#define __NR_mq_timedsend 1264
257#define __NR_mq_timedreceive 1265
258#define __NR_mq_notify 1266
259#define __NR_mq_getsetattr 1267
260#define __NR_kexec_load 1268
261#define __NR_vserver 1269
262#define __NR_waitid 1270
263#define __NR_add_key 1271
264#define __NR_request_key 1272
265#define __NR_keyctl 1273
266#define __NR_ioprio_set 1274
267#define __NR_ioprio_get 1275
268#define __NR_move_pages 1276
269#define __NR_inotify_init 1277
270#define __NR_inotify_add_watch 1278
271#define __NR_inotify_rm_watch 1279
272#define __NR_migrate_pages 1280
273#define __NR_openat 1281
274#define __NR_mkdirat 1282
275#define __NR_mknodat 1283
276#define __NR_fchownat 1284
277#define __NR_futimesat 1285
278#define __NR_newfstatat 1286
279#define __NR_unlinkat 1287
280#define __NR_renameat 1288
281#define __NR_linkat 1289
282#define __NR_symlinkat 1290
283#define __NR_readlinkat 1291
284#define __NR_fchmodat 1292
285#define __NR_faccessat 1293
286#define __NR_pselect6 1294
287#define __NR_ppoll 1295
288#define __NR_unshare 1296
289#define __NR_splice 1297
290#define __NR_set_robust_list 1298
291#define __NR_get_robust_list 1299
292#define __NR_sync_file_range 1300
293#define __NR_tee 1301
294#define __NR_vmsplice 1302
295#define __NR_fallocate 1303
296#define __NR_getcpu 1304
297#define __NR_epoll_pwait 1305
298#define __NR_utimensat 1306
299#define __NR_signalfd 1307
300#define __NR_timerfd 1308
301#define __NR_eventfd 1309
302#define __NR_timerfd_create 1310
303#define __NR_timerfd_settime 1311
304#define __NR_timerfd_gettime 1312
305#define __NR_signalfd4 1313
306#define __NR_eventfd2 1314
307#define __NR_epoll_create1 1315
308#define __NR_dup3 1316
309#define __NR_pipe2 1317
310#define __NR_inotify_init1 1318
311
312#ifdef __KERNEL__
313
314
315#define NR_syscalls 295 /* length of syscall table */
316
317/*
318 * The following defines stop scripts/checksyscalls.sh from complaining about
319 * unimplemented system calls. Glibc provides for each of these by using
320 * more modern equivalent system calls.
321 */
322#define __IGNORE_fork /* clone() */
323#define __IGNORE_time /* gettimeofday() */
324#define __IGNORE_alarm /* setitimer(ITIMER_REAL, ... */
325#define __IGNORE_pause /* rt_sigprocmask(), rt_sigsuspend() */
326#define __IGNORE_utime /* utimes() */
327#define __IGNORE_getpgrp /* getpgid() */
328#define __IGNORE_vfork /* clone() */
329
330#define __ARCH_WANT_SYS_RT_SIGACTION
331#define __ARCH_WANT_SYS_RT_SIGSUSPEND
332
333#ifdef CONFIG_IA32_SUPPORT
334# define __ARCH_WANT_SYS_FADVISE64
335# define __ARCH_WANT_SYS_GETPGRP
336# define __ARCH_WANT_SYS_LLSEEK
337# define __ARCH_WANT_SYS_NICE
338# define __ARCH_WANT_SYS_OLD_GETRLIMIT
339# define __ARCH_WANT_SYS_OLDUMOUNT
340# define __ARCH_WANT_SYS_SIGPENDING
341# define __ARCH_WANT_SYS_SIGPROCMASK
342# define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
343# define __ARCH_WANT_COMPAT_SYS_TIME
344#endif
345
346#if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
347
348#include <linux/types.h>
349#include <linux/linkage.h>
350#include <linux/compiler.h>
351
352extern long __ia64_syscall (long a0, long a1, long a2, long a3, long a4, long nr);
353
354asmlinkage unsigned long sys_mmap(
355 unsigned long addr, unsigned long len,
356 int prot, int flags,
357 int fd, long off);
358asmlinkage unsigned long sys_mmap2(
359 unsigned long addr, unsigned long len,
360 int prot, int flags,
361 int fd, long pgoff);
362struct pt_regs;
363struct sigaction;
364long sys_execve(char __user *filename, char __user * __user *argv,
365 char __user * __user *envp, struct pt_regs *regs);
366asmlinkage long sys_pipe(void);
367asmlinkage long sys_rt_sigaction(int sig,
368 const struct sigaction __user *act,
369 struct sigaction __user *oact,
370 size_t sigsetsize);
371
372/*
373 * "Conditional" syscalls
374 *
375 * Note, this macro can only be used in the file which defines sys_ni_syscall, i.e., in
376 * kernel/sys_ni.c. This version causes warnings because the declaration isn't a
377 * proper prototype, but we can't use __typeof__ either, because not all cond_syscall()
378 * declarations have prototypes at the moment.
379 */
380#define cond_syscall(x) asmlinkage long x (void) __attribute__((weak,alias("sys_ni_syscall")))
381
382#endif /* !__ASSEMBLY__ */
383#endif /* __KERNEL__ */
384#endif /* _ASM_IA64_UNISTD_H */
diff --git a/arch/ia64/include/asm/unwind.h b/arch/ia64/include/asm/unwind.h
new file mode 100644
index 000000000000..1af3875f1a57
--- /dev/null
+++ b/arch/ia64/include/asm/unwind.h
@@ -0,0 +1,233 @@
1#ifndef _ASM_IA64_UNWIND_H
2#define _ASM_IA64_UNWIND_H
3
4/*
5 * Copyright (C) 1999-2000, 2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * A simple API for unwinding kernel stacks. This is used for
9 * debugging and error reporting purposes. The kernel doesn't need
10 * full-blown stack unwinding with all the bells and whitles, so there
11 * is not much point in implementing the full IA-64 unwind API (though
12 * it would of course be possible to implement the kernel API on top
13 * of it).
14 */
15
16struct task_struct; /* forward declaration */
17struct switch_stack; /* forward declaration */
18
19enum unw_application_register {
20 UNW_AR_BSP,
21 UNW_AR_BSPSTORE,
22 UNW_AR_PFS,
23 UNW_AR_RNAT,
24 UNW_AR_UNAT,
25 UNW_AR_LC,
26 UNW_AR_EC,
27 UNW_AR_FPSR,
28 UNW_AR_RSC,
29 UNW_AR_CCV,
30 UNW_AR_CSD,
31 UNW_AR_SSD
32};
33
34/*
35 * The following declarations are private to the unwind
36 * implementation:
37 */
38
39struct unw_stack {
40 unsigned long limit;
41 unsigned long top;
42};
43
44#define UNW_FLAG_INTERRUPT_FRAME (1UL << 0)
45
46/*
47 * No user of this module should every access this structure directly
48 * as it is subject to change. It is declared here solely so we can
49 * use automatic variables.
50 */
51struct unw_frame_info {
52 struct unw_stack regstk;
53 struct unw_stack memstk;
54 unsigned int flags;
55 short hint;
56 short prev_script;
57
58 /* current frame info: */
59 unsigned long bsp; /* backing store pointer value */
60 unsigned long sp; /* stack pointer value */
61 unsigned long psp; /* previous sp value */
62 unsigned long ip; /* instruction pointer value */
63 unsigned long pr; /* current predicate values */
64 unsigned long *cfm_loc; /* cfm save location (or NULL) */
65 unsigned long pt; /* struct pt_regs location */
66
67 struct task_struct *task;
68 struct switch_stack *sw;
69
70 /* preserved state: */
71 unsigned long *bsp_loc; /* previous bsp save location */
72 unsigned long *bspstore_loc;
73 unsigned long *pfs_loc;
74 unsigned long *rnat_loc;
75 unsigned long *rp_loc;
76 unsigned long *pri_unat_loc;
77 unsigned long *unat_loc;
78 unsigned long *pr_loc;
79 unsigned long *lc_loc;
80 unsigned long *fpsr_loc;
81 struct unw_ireg {
82 unsigned long *loc;
83 struct unw_ireg_nat {
84 unsigned long type : 3; /* enum unw_nat_type */
85 signed long off : 61; /* NaT word is at loc+nat.off */
86 } nat;
87 } r4, r5, r6, r7;
88 unsigned long *b1_loc, *b2_loc, *b3_loc, *b4_loc, *b5_loc;
89 struct ia64_fpreg *f2_loc, *f3_loc, *f4_loc, *f5_loc, *fr_loc[16];
90};
91
92/*
93 * The official API follows below:
94 */
95
96struct unw_table_entry {
97 u64 start_offset;
98 u64 end_offset;
99 u64 info_offset;
100};
101
102/*
103 * Initialize unwind support.
104 */
105extern void unw_init (void);
106
107extern void *unw_add_unwind_table (const char *name, unsigned long segment_base, unsigned long gp,
108 const void *table_start, const void *table_end);
109
110extern void unw_remove_unwind_table (void *handle);
111
112/*
113 * Prepare to unwind blocked task t.
114 */
115extern void unw_init_from_blocked_task (struct unw_frame_info *info, struct task_struct *t);
116
117extern void unw_init_frame_info (struct unw_frame_info *info, struct task_struct *t,
118 struct switch_stack *sw);
119
120/*
121 * Prepare to unwind the currently running thread.
122 */
123extern void unw_init_running (void (*callback)(struct unw_frame_info *info, void *arg), void *arg);
124
125/*
126 * Unwind to previous to frame. Returns 0 if successful, negative
127 * number in case of an error.
128 */
129extern int unw_unwind (struct unw_frame_info *info);
130
131/*
132 * Unwind until the return pointer is in user-land (or until an error
133 * occurs). Returns 0 if successful, negative number in case of
134 * error.
135 */
136extern int unw_unwind_to_user (struct unw_frame_info *info);
137
138#define unw_is_intr_frame(info) (((info)->flags & UNW_FLAG_INTERRUPT_FRAME) != 0)
139
140static inline int
141unw_get_ip (struct unw_frame_info *info, unsigned long *valp)
142{
143 *valp = (info)->ip;
144 return 0;
145}
146
147static inline int
148unw_get_sp (struct unw_frame_info *info, unsigned long *valp)
149{
150 *valp = (info)->sp;
151 return 0;
152}
153
154static inline int
155unw_get_psp (struct unw_frame_info *info, unsigned long *valp)
156{
157 *valp = (info)->psp;
158 return 0;
159}
160
161static inline int
162unw_get_bsp (struct unw_frame_info *info, unsigned long *valp)
163{
164 *valp = (info)->bsp;
165 return 0;
166}
167
168static inline int
169unw_get_cfm (struct unw_frame_info *info, unsigned long *valp)
170{
171 *valp = *(info)->cfm_loc;
172 return 0;
173}
174
175static inline int
176unw_set_cfm (struct unw_frame_info *info, unsigned long val)
177{
178 *(info)->cfm_loc = val;
179 return 0;
180}
181
182static inline int
183unw_get_rp (struct unw_frame_info *info, unsigned long *val)
184{
185 if (!info->rp_loc)
186 return -1;
187 *val = *info->rp_loc;
188 return 0;
189}
190
191extern int unw_access_gr (struct unw_frame_info *, int, unsigned long *, char *, int);
192extern int unw_access_br (struct unw_frame_info *, int, unsigned long *, int);
193extern int unw_access_fr (struct unw_frame_info *, int, struct ia64_fpreg *, int);
194extern int unw_access_ar (struct unw_frame_info *, int, unsigned long *, int);
195extern int unw_access_pr (struct unw_frame_info *, unsigned long *, int);
196
197static inline int
198unw_set_gr (struct unw_frame_info *i, int n, unsigned long v, char nat)
199{
200 return unw_access_gr(i, n, &v, &nat, 1);
201}
202
203static inline int
204unw_set_br (struct unw_frame_info *i, int n, unsigned long v)
205{
206 return unw_access_br(i, n, &v, 1);
207}
208
209static inline int
210unw_set_fr (struct unw_frame_info *i, int n, struct ia64_fpreg v)
211{
212 return unw_access_fr(i, n, &v, 1);
213}
214
215static inline int
216unw_set_ar (struct unw_frame_info *i, int n, unsigned long v)
217{
218 return unw_access_ar(i, n, &v, 1);
219}
220
221static inline int
222unw_set_pr (struct unw_frame_info *i, unsigned long v)
223{
224 return unw_access_pr(i, &v, 1);
225}
226
227#define unw_get_gr(i,n,v,nat) unw_access_gr(i,n,v,nat,0)
228#define unw_get_br(i,n,v) unw_access_br(i,n,v,0)
229#define unw_get_fr(i,n,v) unw_access_fr(i,n,v,0)
230#define unw_get_ar(i,n,v) unw_access_ar(i,n,v,0)
231#define unw_get_pr(i,v) unw_access_pr(i,v,0)
232
233#endif /* _ASM_UNWIND_H */
diff --git a/arch/ia64/include/asm/user.h b/arch/ia64/include/asm/user.h
new file mode 100644
index 000000000000..8b9821110348
--- /dev/null
+++ b/arch/ia64/include/asm/user.h
@@ -0,0 +1,58 @@
1#ifndef _ASM_IA64_USER_H
2#define _ASM_IA64_USER_H
3
4/*
5 * Core file format: The core file is written in such a way that gdb
6 * can understand it and provide useful information to the user (under
7 * linux we use the `trad-core' bfd). The file contents are as
8 * follows:
9 *
10 * upage: 1 page consisting of a user struct that tells gdb
11 * what is present in the file. Directly after this is a
12 * copy of the task_struct, which is currently not used by gdb,
13 * but it may come in handy at some point. All of the registers
14 * are stored as part of the upage. The upage should always be
15 * only one page long.
16 * data: The data segment follows next. We use current->end_text to
17 * current->brk to pick up all of the user variables, plus any memory
18 * that may have been sbrk'ed. No attempt is made to determine if a
19 * page is demand-zero or if a page is totally unused, we just cover
20 * the entire range. All of the addresses are rounded in such a way
21 * that an integral number of pages is written.
22 * stack: We need the stack information in order to get a meaningful
23 * backtrace. We need to write the data from usp to
24 * current->start_stack, so we round each of these in order to be able
25 * to write an integer number of pages.
26 *
27 * Modified 1998, 1999, 2001
28 * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
29 */
30
31#include <linux/ptrace.h>
32#include <linux/types.h>
33
34#include <asm/page.h>
35
36#define EF_SIZE 3072 /* XXX fix me */
37
38struct user {
39 unsigned long regs[EF_SIZE/8+32]; /* integer and fp regs */
40 size_t u_tsize; /* text size (pages) */
41 size_t u_dsize; /* data size (pages) */
42 size_t u_ssize; /* stack size (pages) */
43 unsigned long start_code; /* text starting address */
44 unsigned long start_data; /* data starting address */
45 unsigned long start_stack; /* stack starting address */
46 long int signal; /* signal causing core dump */
47 unsigned long u_ar0; /* help gdb find registers */
48 unsigned long magic; /* identifies a core file */
49 char u_comm[32]; /* user command name */
50};
51
52#define NBPG PAGE_SIZE
53#define UPAGES 1
54#define HOST_TEXT_START_ADDR (u.start_code)
55#define HOST_DATA_START_ADDR (u.start_data)
56#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
57
58#endif /* _ASM_IA64_USER_H */
diff --git a/arch/ia64/include/asm/ustack.h b/arch/ia64/include/asm/ustack.h
new file mode 100644
index 000000000000..504167c35b8b
--- /dev/null
+++ b/arch/ia64/include/asm/ustack.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_IA64_USTACK_H
2#define _ASM_IA64_USTACK_H
3
4/*
5 * Constants for the user stack size
6 */
7
8#ifdef __KERNEL__
9#include <asm/page.h>
10
11/* The absolute hard limit for stack size is 1/2 of the mappable space in the region */
12#define MAX_USER_STACK_SIZE (RGN_MAP_LIMIT/2)
13#define STACK_TOP (0x6000000000000000UL + RGN_MAP_LIMIT)
14#define STACK_TOP_MAX STACK_TOP
15#endif
16
17/* Make a default stack size of 2GiB */
18#define DEFAULT_USER_STACK_SIZE (1UL << 31)
19
20#endif /* _ASM_IA64_USTACK_H */
diff --git a/arch/ia64/include/asm/uv/uv_hub.h b/arch/ia64/include/asm/uv/uv_hub.h
new file mode 100644
index 000000000000..f607018af4a1
--- /dev/null
+++ b/arch/ia64/include/asm/uv/uv_hub.h
@@ -0,0 +1,309 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV architectural definitions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_HUB_H__
12#define __ASM_IA64_UV_HUB_H__
13
14#include <linux/numa.h>
15#include <linux/percpu.h>
16#include <asm/types.h>
17#include <asm/percpu.h>
18
19
20/*
21 * Addressing Terminology
22 *
23 * M - The low M bits of a physical address represent the offset
24 * into the blade local memory. RAM memory on a blade is physically
25 * contiguous (although various IO spaces may punch holes in
26 * it)..
27 *
28 * N - Number of bits in the node portion of a socket physical
29 * address.
30 *
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
36 *
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
38 * of nasids.
39 *
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
42 *
43 *
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
49 *
50 * M - number of node offset bits (35 .. 40)
51 *
52 *
53 * Memory/UV-HUB Processor Socket Address Format:
54 * +----------------+---------------+---------------------+
55 * |00..000000000000| PNODE | NodeOffset |
56 * +----------------+---------------+---------------------+
57 * <--- N bits --->|<--------M bits ----->
58 *
59 * M - number of node offset bits (35 .. 40)
60 * N - number of PNODE bits (0 .. 10)
61 *
62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
63 * The actual values are configuration dependent and are set at
64 * boot time. M & N values are set by the hardware/BIOS at boot.
65 */
66
67
68/*
69 * Maximum number of bricks in all partitions and in all coherency domains.
70 * This is the total number of bricks accessible in the numalink fabric. It
71 * includes all C & M bricks. Routers are NOT included.
72 *
73 * This value is also the value of the maximum number of non-router NASIDs
74 * in the numalink fabric.
75 *
76 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
77 */
78#define UV_MAX_NUMALINK_BLADES 16384
79
80/*
81 * Maximum number of C/Mbricks within a software SSI (hardware may support
82 * more).
83 */
84#define UV_MAX_SSI_BLADES 1
85
86/*
87 * The largest possible NASID of a C or M brick (+ 2)
88 */
89#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
90
91/*
92 * The following defines attributes of the HUB chip. These attributes are
93 * frequently referenced and are kept in the per-cpu data areas of each cpu.
94 * They are kept together in a struct to minimize cache misses.
95 */
96struct uv_hub_info_s {
97 unsigned long global_mmr_base;
98 unsigned long gpa_mask;
99 unsigned long gnode_upper;
100 unsigned long lowmem_remap_top;
101 unsigned long lowmem_remap_base;
102 unsigned short pnode;
103 unsigned short pnode_mask;
104 unsigned short coherency_domain_number;
105 unsigned short numa_blade_id;
106 unsigned char blade_processor_id;
107 unsigned char m_val;
108 unsigned char n_val;
109};
110DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
111#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
112#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
113
114/*
115 * Local & Global MMR space macros.
116 * Note: macros are intended to be used ONLY by inline functions
117 * in this file - not by other kernel code.
118 * n - NASID (full 15-bit global nasid)
119 * g - GNODE (full 15-bit global nasid, right shifted 1)
120 * p - PNODE (local part of nsids, right shifted 1)
121 */
122#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
123#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
124
125#define UV_LOCAL_MMR_BASE 0xf4000000UL
126#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
127#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
128
129#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
130#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
131
132#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
133
134#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
135 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
136
137/*
138 * Macros for converting between kernel virtual addresses, socket local physical
139 * addresses, and UV global physical addresses.
140 * Note: use the standard __pa() & __va() macros for converting
141 * between socket virtual and socket physical addresses.
142 */
143
144/* socket phys RAM --> UV global physical address */
145static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
146{
147 if (paddr < uv_hub_info->lowmem_remap_top)
148 paddr += uv_hub_info->lowmem_remap_base;
149 return paddr | uv_hub_info->gnode_upper;
150}
151
152
153/* socket virtual --> UV global physical address */
154static inline unsigned long uv_gpa(void *v)
155{
156 return __pa(v) | uv_hub_info->gnode_upper;
157}
158
159/* socket virtual --> UV global physical address */
160static inline void *uv_vgpa(void *v)
161{
162 return (void *)uv_gpa(v);
163}
164
165/* UV global physical address --> socket virtual */
166static inline void *uv_va(unsigned long gpa)
167{
168 return __va(gpa & uv_hub_info->gpa_mask);
169}
170
171/* pnode, offset --> socket virtual */
172static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
173{
174 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
175}
176
177
178/*
179 * Access global MMRs using the low memory MMR32 space. This region supports
180 * faster MMR access but not all MMRs are accessible in this space.
181 */
182static inline unsigned long *uv_global_mmr32_address(int pnode,
183 unsigned long offset)
184{
185 return __va(UV_GLOBAL_MMR32_BASE |
186 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
187}
188
189static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
190 unsigned long val)
191{
192 *uv_global_mmr32_address(pnode, offset) = val;
193}
194
195static inline unsigned long uv_read_global_mmr32(int pnode,
196 unsigned long offset)
197{
198 return *uv_global_mmr32_address(pnode, offset);
199}
200
201/*
202 * Access Global MMR space using the MMR space located at the top of physical
203 * memory.
204 */
205static inline unsigned long *uv_global_mmr64_address(int pnode,
206 unsigned long offset)
207{
208 return __va(UV_GLOBAL_MMR64_BASE |
209 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
210}
211
212static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
213 unsigned long val)
214{
215 *uv_global_mmr64_address(pnode, offset) = val;
216}
217
218static inline unsigned long uv_read_global_mmr64(int pnode,
219 unsigned long offset)
220{
221 return *uv_global_mmr64_address(pnode, offset);
222}
223
224/*
225 * Access hub local MMRs. Faster than using global space but only local MMRs
226 * are accessible.
227 */
228static inline unsigned long *uv_local_mmr_address(unsigned long offset)
229{
230 return __va(UV_LOCAL_MMR_BASE | offset);
231}
232
233static inline unsigned long uv_read_local_mmr(unsigned long offset)
234{
235 return *uv_local_mmr_address(offset);
236}
237
238static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
239{
240 *uv_local_mmr_address(offset) = val;
241}
242
243/*
244 * Structures and definitions for converting between cpu, node, pnode, and blade
245 * numbers.
246 */
247
248/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
249static inline int uv_blade_processor_id(void)
250{
251 return smp_processor_id();
252}
253
254/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
255static inline int uv_numa_blade_id(void)
256{
257 return 0;
258}
259
260/* Convert a cpu number to the the UV blade number */
261static inline int uv_cpu_to_blade_id(int cpu)
262{
263 return 0;
264}
265
266/* Convert linux node number to the UV blade number */
267static inline int uv_node_to_blade_id(int nid)
268{
269 return 0;
270}
271
272/* Convert a blade id to the PNODE of the blade */
273static inline int uv_blade_to_pnode(int bid)
274{
275 return 0;
276}
277
278/* Determine the number of possible cpus on a blade */
279static inline int uv_blade_nr_possible_cpus(int bid)
280{
281 return num_possible_cpus();
282}
283
284/* Determine the number of online cpus on a blade */
285static inline int uv_blade_nr_online_cpus(int bid)
286{
287 return num_online_cpus();
288}
289
290/* Convert a cpu id to the PNODE of the blade containing the cpu */
291static inline int uv_cpu_to_pnode(int cpu)
292{
293 return 0;
294}
295
296/* Convert a linux node number to the PNODE of the blade */
297static inline int uv_node_to_pnode(int nid)
298{
299 return 0;
300}
301
302/* Maximum possible number of blades */
303static inline int uv_num_possible_blades(void)
304{
305 return 1;
306}
307
308#endif /* __ASM_IA64_UV_HUB__ */
309
diff --git a/arch/ia64/include/asm/uv/uv_mmrs.h b/arch/ia64/include/asm/uv/uv_mmrs.h
new file mode 100644
index 000000000000..c149ef085437
--- /dev/null
+++ b/arch/ia64/include/asm/uv/uv_mmrs.h
@@ -0,0 +1,673 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV MMR definitions
7 *
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_IA64_UV_MMRS__
12#define __ASM_IA64_UV_MMRS__
13
14#define UV_MMR_ENABLE (1UL << 63)
15
16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0438
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
54
55/* ========================================================================= */
56/* UVH_EVENT_OCCURRED0 */
57/* ========================================================================= */
58#define UVH_EVENT_OCCURRED0 0x70000UL
59#define UVH_EVENT_OCCURRED0_32 0x005e8
60
61#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
62#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
63#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
64#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
65#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
66#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
67#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
68#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
69#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
70#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
71#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
72#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
73#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
74#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
75#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
76#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
77#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
78#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
79#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
80#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
81#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
82#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
83#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
84#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
85#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
86#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
87#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
88#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
89#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
90#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
91#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
92#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
93#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
94#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
95#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
96#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
97#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
98#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
99#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
100#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
101#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
102#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
103#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
104#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
105#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
106#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
107#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
108#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
109#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
110#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
111#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
112#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
113#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
114#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
115#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
116#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
117#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
118#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
119#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
120#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
121#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
122#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
123#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
139#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
140#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
141#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
142#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
143#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
144#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
145#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
146#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
147#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
148#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
149#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
150#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
151#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
152#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
153#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
154#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
155#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
156#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
157#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
158#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
159#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
160#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
161#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
162#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
163#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
164#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
165#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
166#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
167#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
168#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
169#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
170#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
171#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
172#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
173#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
174#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
175union uvh_event_occurred0_u {
176 unsigned long v;
177 struct uvh_event_occurred0_s {
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
183 unsigned long xn_hcerr : 1; /* RW, W1C */
184 unsigned long si_hcerr : 1; /* RW, W1C */
185 unsigned long lb_aoerr0 : 1; /* RW, W1C */
186 unsigned long gr0_aoerr0 : 1; /* RW, W1C */
187 unsigned long gr1_aoerr0 : 1; /* RW, W1C */
188 unsigned long lh_aoerr0 : 1; /* RW, W1C */
189 unsigned long rh_aoerr0 : 1; /* RW, W1C */
190 unsigned long xn_aoerr0 : 1; /* RW, W1C */
191 unsigned long si_aoerr0 : 1; /* RW, W1C */
192 unsigned long lb_aoerr1 : 1; /* RW, W1C */
193 unsigned long gr0_aoerr1 : 1; /* RW, W1C */
194 unsigned long gr1_aoerr1 : 1; /* RW, W1C */
195 unsigned long lh_aoerr1 : 1; /* RW, W1C */
196 unsigned long rh_aoerr1 : 1; /* RW, W1C */
197 unsigned long xn_aoerr1 : 1; /* RW, W1C */
198 unsigned long si_aoerr1 : 1; /* RW, W1C */
199 unsigned long rh_vpi_int : 1; /* RW, W1C */
200 unsigned long system_shutdown_int : 1; /* RW, W1C */
201 unsigned long lb_irq_int_0 : 1; /* RW, W1C */
202 unsigned long lb_irq_int_1 : 1; /* RW, W1C */
203 unsigned long lb_irq_int_2 : 1; /* RW, W1C */
204 unsigned long lb_irq_int_3 : 1; /* RW, W1C */
205 unsigned long lb_irq_int_4 : 1; /* RW, W1C */
206 unsigned long lb_irq_int_5 : 1; /* RW, W1C */
207 unsigned long lb_irq_int_6 : 1; /* RW, W1C */
208 unsigned long lb_irq_int_7 : 1; /* RW, W1C */
209 unsigned long lb_irq_int_8 : 1; /* RW, W1C */
210 unsigned long lb_irq_int_9 : 1; /* RW, W1C */
211 unsigned long lb_irq_int_10 : 1; /* RW, W1C */
212 unsigned long lb_irq_int_11 : 1; /* RW, W1C */
213 unsigned long lb_irq_int_12 : 1; /* RW, W1C */
214 unsigned long lb_irq_int_13 : 1; /* RW, W1C */
215 unsigned long lb_irq_int_14 : 1; /* RW, W1C */
216 unsigned long lb_irq_int_15 : 1; /* RW, W1C */
217 unsigned long l1_nmi_int : 1; /* RW, W1C */
218 unsigned long stop_clock : 1; /* RW, W1C */
219 unsigned long asic_to_l1 : 1; /* RW, W1C */
220 unsigned long l1_to_asic : 1; /* RW, W1C */
221 unsigned long ltc_int : 1; /* RW, W1C */
222 unsigned long la_seq_trigger : 1; /* RW, W1C */
223 unsigned long ipi_int : 1; /* RW, W1C */
224 unsigned long extio_int0 : 1; /* RW, W1C */
225 unsigned long extio_int1 : 1; /* RW, W1C */
226 unsigned long extio_int2 : 1; /* RW, W1C */
227 unsigned long extio_int3 : 1; /* RW, W1C */
228 unsigned long profile_int : 1; /* RW, W1C */
229 unsigned long rtc0 : 1; /* RW, W1C */
230 unsigned long rtc1 : 1; /* RW, W1C */
231 unsigned long rtc2 : 1; /* RW, W1C */
232 unsigned long rtc3 : 1; /* RW, W1C */
233 unsigned long bau_data : 1; /* RW, W1C */
234 unsigned long power_management_req : 1; /* RW, W1C */
235 unsigned long rsvd_57_63 : 7; /* */
236 } s;
237};
238
239/* ========================================================================= */
240/* UVH_EVENT_OCCURRED0_ALIAS */
241/* ========================================================================= */
242#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244
245/* ========================================================================= */
246/* UVH_INT_CMPB */
247/* ========================================================================= */
248#define UVH_INT_CMPB 0x22080UL
249
250#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
251#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
252
253union uvh_int_cmpb_u {
254 unsigned long v;
255 struct uvh_int_cmpb_s {
256 unsigned long real_time_cmpb : 56; /* RW */
257 unsigned long rsvd_56_63 : 8; /* */
258 } s;
259};
260
261/* ========================================================================= */
262/* UVH_INT_CMPC */
263/* ========================================================================= */
264#define UVH_INT_CMPC 0x22100UL
265
266#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
267#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
268
269union uvh_int_cmpc_u {
270 unsigned long v;
271 struct uvh_int_cmpc_s {
272 unsigned long real_time_cmpc : 56; /* RW */
273 unsigned long rsvd_56_63 : 8; /* */
274 } s;
275};
276
277/* ========================================================================= */
278/* UVH_INT_CMPD */
279/* ========================================================================= */
280#define UVH_INT_CMPD 0x22180UL
281
282#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
283#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
284
285union uvh_int_cmpd_u {
286 unsigned long v;
287 struct uvh_int_cmpd_s {
288 unsigned long real_time_cmpd : 56; /* RW */
289 unsigned long rsvd_56_63 : 8; /* */
290 } s;
291};
292
293/* ========================================================================= */
294/* UVH_NODE_ID */
295/* ========================================================================= */
296#define UVH_NODE_ID 0x0UL
297
298#define UVH_NODE_ID_FORCE1_SHFT 0
299#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
300#define UVH_NODE_ID_MANUFACTURER_SHFT 1
301#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
302#define UVH_NODE_ID_PART_NUMBER_SHFT 12
303#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
304#define UVH_NODE_ID_REVISION_SHFT 28
305#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
306#define UVH_NODE_ID_NODE_ID_SHFT 32
307#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
308#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
309#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
310#define UVH_NODE_ID_NI_PORT_SHFT 56
311#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
312
313union uvh_node_id_u {
314 unsigned long v;
315 struct uvh_node_id_s {
316 unsigned long force1 : 1; /* RO */
317 unsigned long manufacturer : 11; /* RO */
318 unsigned long part_number : 16; /* RO */
319 unsigned long revision : 4; /* RO */
320 unsigned long node_id : 15; /* RW */
321 unsigned long rsvd_47 : 1; /* */
322 unsigned long nodes_per_bit : 7; /* RW */
323 unsigned long rsvd_55 : 1; /* */
324 unsigned long ni_port : 4; /* RO */
325 unsigned long rsvd_60_63 : 4; /* */
326 } s;
327};
328
329/* ========================================================================= */
330/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
331/* ========================================================================= */
332#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
333
334#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
335#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
336
337union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
338 unsigned long v;
339 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
340 unsigned long rsvd_0_23 : 24; /* */
341 unsigned long dest_base : 22; /* RW */
342 unsigned long rsvd_46_63: 18; /* */
343 } s;
344};
345
346/* ========================================================================= */
347/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
348/* ========================================================================= */
349#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
350
351#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
352#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
353
354union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
355 unsigned long v;
356 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
357 unsigned long rsvd_0_23 : 24; /* */
358 unsigned long dest_base : 22; /* RW */
359 unsigned long rsvd_46_63: 18; /* */
360 } s;
361};
362
363/* ========================================================================= */
364/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
365/* ========================================================================= */
366#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
367
368#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
369#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
370
371union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
372 unsigned long v;
373 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
374 unsigned long rsvd_0_23 : 24; /* */
375 unsigned long dest_base : 22; /* RW */
376 unsigned long rsvd_46_63: 18; /* */
377 } s;
378};
379
380/* ========================================================================= */
381/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
382/* ========================================================================= */
383#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
384
385#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
386#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
387#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
388#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
389#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
390#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
391#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
392#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
393
394union uvh_rh_gam_gru_overlay_config_mmr_u {
395 unsigned long v;
396 struct uvh_rh_gam_gru_overlay_config_mmr_s {
397 unsigned long rsvd_0_27: 28; /* */
398 unsigned long base : 18; /* RW */
399 unsigned long rsvd_46_47: 2; /* */
400 unsigned long gr4 : 1; /* RW */
401 unsigned long rsvd_49_51: 3; /* */
402 unsigned long n_gru : 4; /* RW */
403 unsigned long rsvd_56_62: 7; /* */
404 unsigned long enable : 1; /* RW */
405 } s;
406};
407
408/* ========================================================================= */
409/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
410/* ========================================================================= */
411#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
412
413#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
414#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
415#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
416#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
417#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
418#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
419
420union uvh_rh_gam_mmr_overlay_config_mmr_u {
421 unsigned long v;
422 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
423 unsigned long rsvd_0_25: 26; /* */
424 unsigned long base : 20; /* RW */
425 unsigned long dual_hub : 1; /* RW */
426 unsigned long rsvd_47_62: 16; /* */
427 unsigned long enable : 1; /* RW */
428 } s;
429};
430
431/* ========================================================================= */
432/* UVH_RTC */
433/* ========================================================================= */
434#define UVH_RTC 0x340000UL
435
436#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
437#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
438
439union uvh_rtc_u {
440 unsigned long v;
441 struct uvh_rtc_s {
442 unsigned long real_time_clock : 56; /* RW */
443 unsigned long rsvd_56_63 : 8; /* */
444 } s;
445};
446
447/* ========================================================================= */
448/* UVH_RTC1_INT_CONFIG */
449/* ========================================================================= */
450#define UVH_RTC1_INT_CONFIG 0x615c0UL
451
452#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
453#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
454#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
455#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
456#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
457#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
458#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
459#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
460#define UVH_RTC1_INT_CONFIG_P_SHFT 13
461#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
462#define UVH_RTC1_INT_CONFIG_T_SHFT 15
463#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
464#define UVH_RTC1_INT_CONFIG_M_SHFT 16
465#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
466#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
467#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
468
469union uvh_rtc1_int_config_u {
470 unsigned long v;
471 struct uvh_rtc1_int_config_s {
472 unsigned long vector_ : 8; /* RW */
473 unsigned long dm : 3; /* RW */
474 unsigned long destmode : 1; /* RW */
475 unsigned long status : 1; /* RO */
476 unsigned long p : 1; /* RO */
477 unsigned long rsvd_14 : 1; /* */
478 unsigned long t : 1; /* RO */
479 unsigned long m : 1; /* RW */
480 unsigned long rsvd_17_31: 15; /* */
481 unsigned long apic_id : 32; /* RW */
482 } s;
483};
484
485/* ========================================================================= */
486/* UVH_RTC2_INT_CONFIG */
487/* ========================================================================= */
488#define UVH_RTC2_INT_CONFIG 0x61600UL
489
490#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
491#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
492#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
493#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
494#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
495#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
496#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
497#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
498#define UVH_RTC2_INT_CONFIG_P_SHFT 13
499#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
500#define UVH_RTC2_INT_CONFIG_T_SHFT 15
501#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
502#define UVH_RTC2_INT_CONFIG_M_SHFT 16
503#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
504#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
505#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
506
507union uvh_rtc2_int_config_u {
508 unsigned long v;
509 struct uvh_rtc2_int_config_s {
510 unsigned long vector_ : 8; /* RW */
511 unsigned long dm : 3; /* RW */
512 unsigned long destmode : 1; /* RW */
513 unsigned long status : 1; /* RO */
514 unsigned long p : 1; /* RO */
515 unsigned long rsvd_14 : 1; /* */
516 unsigned long t : 1; /* RO */
517 unsigned long m : 1; /* RW */
518 unsigned long rsvd_17_31: 15; /* */
519 unsigned long apic_id : 32; /* RW */
520 } s;
521};
522
523/* ========================================================================= */
524/* UVH_RTC3_INT_CONFIG */
525/* ========================================================================= */
526#define UVH_RTC3_INT_CONFIG 0x61640UL
527
528#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
529#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
530#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
531#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
532#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
533#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
534#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
535#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
536#define UVH_RTC3_INT_CONFIG_P_SHFT 13
537#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
538#define UVH_RTC3_INT_CONFIG_T_SHFT 15
539#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
540#define UVH_RTC3_INT_CONFIG_M_SHFT 16
541#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
542#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
543#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
544
545union uvh_rtc3_int_config_u {
546 unsigned long v;
547 struct uvh_rtc3_int_config_s {
548 unsigned long vector_ : 8; /* RW */
549 unsigned long dm : 3; /* RW */
550 unsigned long destmode : 1; /* RW */
551 unsigned long status : 1; /* RO */
552 unsigned long p : 1; /* RO */
553 unsigned long rsvd_14 : 1; /* */
554 unsigned long t : 1; /* RO */
555 unsigned long m : 1; /* RW */
556 unsigned long rsvd_17_31: 15; /* */
557 unsigned long apic_id : 32; /* RW */
558 } s;
559};
560
561/* ========================================================================= */
562/* UVH_RTC_INC_RATIO */
563/* ========================================================================= */
564#define UVH_RTC_INC_RATIO 0x350000UL
565
566#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
567#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
568#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
569#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
570
571union uvh_rtc_inc_ratio_u {
572 unsigned long v;
573 struct uvh_rtc_inc_ratio_s {
574 unsigned long fraction : 20; /* RW */
575 unsigned long ratio : 3; /* RW */
576 unsigned long rsvd_23_63: 41; /* */
577 } s;
578};
579
580/* ========================================================================= */
581/* UVH_SI_ADDR_MAP_CONFIG */
582/* ========================================================================= */
583#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
584
585#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
586#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
587#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
588#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
589
590union uvh_si_addr_map_config_u {
591 unsigned long v;
592 struct uvh_si_addr_map_config_s {
593 unsigned long m_skt : 6; /* RW */
594 unsigned long rsvd_6_7: 2; /* */
595 unsigned long n_skt : 4; /* RW */
596 unsigned long rsvd_12_63: 52; /* */
597 } s;
598};
599
600/* ========================================================================= */
601/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
602/* ========================================================================= */
603#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
604
605#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
606#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
607#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
608#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
609#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
610#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
611
612union uvh_si_alias0_overlay_config_u {
613 unsigned long v;
614 struct uvh_si_alias0_overlay_config_s {
615 unsigned long rsvd_0_23: 24; /* */
616 unsigned long base : 8; /* RW */
617 unsigned long rsvd_32_47: 16; /* */
618 unsigned long m_alias : 5; /* RW */
619 unsigned long rsvd_53_62: 10; /* */
620 unsigned long enable : 1; /* RW */
621 } s;
622};
623
624/* ========================================================================= */
625/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
626/* ========================================================================= */
627#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
628
629#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
630#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
631#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
632#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
633#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
634#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
635
636union uvh_si_alias1_overlay_config_u {
637 unsigned long v;
638 struct uvh_si_alias1_overlay_config_s {
639 unsigned long rsvd_0_23: 24; /* */
640 unsigned long base : 8; /* RW */
641 unsigned long rsvd_32_47: 16; /* */
642 unsigned long m_alias : 5; /* RW */
643 unsigned long rsvd_53_62: 10; /* */
644 unsigned long enable : 1; /* RW */
645 } s;
646};
647
648/* ========================================================================= */
649/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
650/* ========================================================================= */
651#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
652
653#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
654#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
655#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
656#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
657#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
658#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
659
660union uvh_si_alias2_overlay_config_u {
661 unsigned long v;
662 struct uvh_si_alias2_overlay_config_s {
663 unsigned long rsvd_0_23: 24; /* */
664 unsigned long base : 8; /* RW */
665 unsigned long rsvd_32_47: 16; /* */
666 unsigned long m_alias : 5; /* RW */
667 unsigned long rsvd_53_62: 10; /* */
668 unsigned long enable : 1; /* RW */
669 } s;
670};
671
672
673#endif /* __ASM_IA64_UV_MMRS__ */
diff --git a/arch/ia64/include/asm/vga.h b/arch/ia64/include/asm/vga.h
new file mode 100644
index 000000000000..02184ecd8208
--- /dev/null
+++ b/arch/ia64/include/asm/vga.h
@@ -0,0 +1,25 @@
1/*
2 * Access to VGA videoram
3 *
4 * (c) 1998 Martin Mares <mj@ucw.cz>
5 * (c) 1999 Asit Mallick <asit.k.mallick@intel.com>
6 * (c) 1999 Don Dugger <don.dugger@intel.com>
7 */
8
9#ifndef __ASM_IA64_VGA_H_
10#define __ASM_IA64_VGA_H_
11
12/*
13 * On the PC, we can just recalculate addresses and then access the
14 * videoram directly without any black magic.
15 */
16
17extern unsigned long vga_console_iobase;
18extern unsigned long vga_console_membase;
19
20#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap_nocache(vga_console_membase + (x), s))
21
22#define vga_readb(x) (*(x))
23#define vga_writeb(x,y) (*(y) = (x))
24
25#endif /* __ASM_IA64_VGA_H_ */
diff --git a/arch/ia64/include/asm/xor.h b/arch/ia64/include/asm/xor.h
new file mode 100644
index 000000000000..a349e23dea15
--- /dev/null
+++ b/arch/ia64/include/asm/xor.h
@@ -0,0 +1,31 @@
1/*
2 * Optimized RAID-5 checksumming functions for IA-64.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2, or (at your option)
7 * any later version.
8 *
9 * You should have received a copy of the GNU General Public License
10 * (for example /usr/src/linux/COPYING); if not, write to the Free
11 * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
12 */
13
14
15extern void xor_ia64_2(unsigned long, unsigned long *, unsigned long *);
16extern void xor_ia64_3(unsigned long, unsigned long *, unsigned long *,
17 unsigned long *);
18extern void xor_ia64_4(unsigned long, unsigned long *, unsigned long *,
19 unsigned long *, unsigned long *);
20extern void xor_ia64_5(unsigned long, unsigned long *, unsigned long *,
21 unsigned long *, unsigned long *, unsigned long *);
22
23static struct xor_block_template xor_block_ia64 = {
24 .name = "ia64",
25 .do_2 = xor_ia64_2,
26 .do_3 = xor_ia64_3,
27 .do_4 = xor_ia64_4,
28 .do_5 = xor_ia64_5,
29};
30
31#define XOR_TRY_TEMPLATES xor_speed(&xor_block_ia64)