[IA64] 4-level page tables

This patch introduces 4-level page tables to ia64.  I have run
some benchmarks and found nothing interesting.  Performance has
consistently fallen within the noise range.

It also introduces a config option (setting the default to 3
levels).  The config option prevents having 4 level page
tables with 64k base page size.

Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index d4de8a4814be..8796e12c56f3 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -164,6 +164,19 @@ config IA64_PAGE_SIZE_64KB
 
 endchoice
 
+choice
+        prompt "Page Table Levels"
+        default PGTABLE_3
+
+config PGTABLE_3
+        bool "3 Levels"
+
+config PGTABLE_4
+        depends on !IA64_PAGE_SIZE_64KB
+        bool "4 Levels"
+
+endchoice
+
 source kernel/Kconfig.hz
 
 config IA64_BRL_EMU