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authordean gaudet <dean@arctic.org>2007-08-10 16:30:59 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-11 18:58:12 -0400
commit3320ad994afb2c44ad34b3b34c3c5cf0da297331 (patch)
tree7eb9c73a0513f96a7af3c598cd3103cbf4da5043 /arch/i386
parent9535239f6bc99f68e0cfae44505ad402b53ed24c (diff)
x86: Work around mmio config space quirk on AMD Fam10h
Some broken devices have been discovered to require %al/%ax/%eax registers for MMIO config space accesses. Modify mmconfig.c to use these registers explicitly (rather than modify the global readb/writeb/etc inlines). AK: also changed i386 to always use eax AK: moved change to extended space probing to different patch AK: reworked with inlines according to Linus' requirements. AK: improve comments. Signed-off-by: dean gaudet <dean@arctic.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/i386')
-rw-r--r--arch/i386/pci/mmconfig.c14
-rw-r--r--arch/i386/pci/pci.h43
2 files changed, 49 insertions, 8 deletions
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index bb1afd9e589d..0d46b7a88b3b 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -82,16 +82,15 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
82 82
83 switch (len) { 83 switch (len) {
84 case 1: 84 case 1:
85 *value = readb(mmcfg_virt_addr + reg); 85 *value = mmio_config_readb(mmcfg_virt_addr + reg);
86 break; 86 break;
87 case 2: 87 case 2:
88 *value = readw(mmcfg_virt_addr + reg); 88 *value = mmio_config_readw(mmcfg_virt_addr + reg);
89 break; 89 break;
90 case 4: 90 case 4:
91 *value = readl(mmcfg_virt_addr + reg); 91 *value = mmio_config_readl(mmcfg_virt_addr + reg);
92 break; 92 break;
93 } 93 }
94
95 spin_unlock_irqrestore(&pci_config_lock, flags); 94 spin_unlock_irqrestore(&pci_config_lock, flags);
96 95
97 return 0; 96 return 0;
@@ -116,16 +115,15 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
116 115
117 switch (len) { 116 switch (len) {
118 case 1: 117 case 1:
119 writeb(value, mmcfg_virt_addr + reg); 118 mmio_config_writeb(mmcfg_virt_addr, value);
120 break; 119 break;
121 case 2: 120 case 2:
122 writew(value, mmcfg_virt_addr + reg); 121 mmio_config_writew(mmcfg_virt_addr, value);
123 break; 122 break;
124 case 4: 123 case 4:
125 writel(value, mmcfg_virt_addr + reg); 124 mmio_config_writel(mmcfg_virt_addr, value);
126 break; 125 break;
127 } 126 }
128
129 spin_unlock_irqrestore(&pci_config_lock, flags); 127 spin_unlock_irqrestore(&pci_config_lock, flags);
130 128
131 return 0; 129 return 0;
diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h
index e58bae2076ad..8c66f275756f 100644
--- a/arch/i386/pci/pci.h
+++ b/arch/i386/pci/pci.h
@@ -104,3 +104,46 @@ extern DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
104extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus, 104extern int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
105 unsigned int devfn); 105 unsigned int devfn);
106extern int __init pci_mmcfg_arch_init(void); 106extern int __init pci_mmcfg_arch_init(void);
107
108/*
109 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
110 * on their northbrige except through the * %eax register. As such, you MUST
111 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
112 * accessor functions.
113 * In fact just use pci_config_*, nothing else please.
114 */
115static inline unsigned char mmio_config_readb(void __iomem *pos)
116{
117 u8 val;
118 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
119 return val;
120}
121
122static inline unsigned short mmio_config_readw(void __iomem *pos)
123{
124 u16 val;
125 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
126 return val;
127}
128
129static inline unsigned int mmio_config_readl(void __iomem *pos)
130{
131 u32 val;
132 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
133 return val;
134}
135
136static inline void mmio_config_writeb(void __iomem *pos, u8 val)
137{
138 asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
139}
140
141static inline void mmio_config_writew(void __iomem *pos, u16 val)
142{
143 asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
144}
145
146static inline void mmio_config_writel(void __iomem *pos, u32 val)
147{
148 asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
149}