diff options
author | Brian Gerst <bgerst@didntduck.org> | 2007-05-21 08:31:53 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-21 12:56:57 -0400 |
commit | 17304383ebc1ce68a88030ac4d18ea549d9578c7 (patch) | |
tree | ddeebffef6841cc421e9fc9bf5429b4a97057363 /arch/i386 | |
parent | d0aff6e6f4e54f79f9c89d147d371bad384454e9 (diff) |
i386: fix PGE mask
cr4 is a 32-bit register, so casting the mask to an unsigned char is wrong,
as it clears more than the PGE bit.
Signed-off-by: Brian Gerst <bgerst@didntduck.org>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/i386')
-rw-r--r-- | arch/i386/kernel/cpu/mtrr/cyrix.c | 2 | ||||
-rw-r--r-- | arch/i386/kernel/cpu/mtrr/state.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/i386/kernel/cpu/mtrr/cyrix.c b/arch/i386/kernel/cpu/mtrr/cyrix.c index 0737a596db43..9edf5625584f 100644 --- a/arch/i386/kernel/cpu/mtrr/cyrix.c +++ b/arch/i386/kernel/cpu/mtrr/cyrix.c | |||
@@ -136,7 +136,7 @@ static void prepare_set(void) | |||
136 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ | 136 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ |
137 | if ( cpu_has_pge ) { | 137 | if ( cpu_has_pge ) { |
138 | cr4 = read_cr4(); | 138 | cr4 = read_cr4(); |
139 | write_cr4(cr4 & (unsigned char) ~(1 << 7)); | 139 | write_cr4(cr4 & ~X86_CR4_PGE); |
140 | } | 140 | } |
141 | 141 | ||
142 | /* Disable and flush caches. Note that wbinvd flushes the TLBs as | 142 | /* Disable and flush caches. Note that wbinvd flushes the TLBs as |
diff --git a/arch/i386/kernel/cpu/mtrr/state.c b/arch/i386/kernel/cpu/mtrr/state.c index f62ecd15811a..7b39a2f954d9 100644 --- a/arch/i386/kernel/cpu/mtrr/state.c +++ b/arch/i386/kernel/cpu/mtrr/state.c | |||
@@ -19,7 +19,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) | |||
19 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ | 19 | /* Save value of CR4 and clear Page Global Enable (bit 7) */ |
20 | if ( cpu_has_pge ) { | 20 | if ( cpu_has_pge ) { |
21 | ctxt->cr4val = read_cr4(); | 21 | ctxt->cr4val = read_cr4(); |
22 | write_cr4(ctxt->cr4val & (unsigned char) ~(1 << 7)); | 22 | write_cr4(ctxt->cr4val & ~X86_CR4_PGE); |
23 | } | 23 | } |
24 | 24 | ||
25 | /* Disable and flush caches. Note that wbinvd flushes the TLBs as | 25 | /* Disable and flush caches. Note that wbinvd flushes the TLBs as |