[PATCH] fix subarchitecture breakage with CONFIG_SCHED_SMT

Commit 1e9f28fa1eb9773bf65bae08288c6a0a38eef4a7 ("[PATCH] sched: new
sched domain for representing multi-core") incorrectly made SCHED_SMT
and some of the structures it uses dependent on SMP.

However, this is wrong, the structures are only defined if X86_HT, so
SCHED_SMT has to depend on that as well.

The patch broke voyager, since it doesn't provide any of the multi-core
or hyperthreading structures.

Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

3 files changed, 6 insertions, 6 deletions

diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig
index 47c08bcd9b24..6662f8c44798 100644
--- a/arch/i386/Kconfig
+++ b/arch/i386/Kconfig
@@ -233,7 +233,7 @@ config NR_CPUS
 
 config SCHED_SMT
         bool "SMT (Hyperthreading) scheduler support"
-        depends on SMP
+        depends on X86_HT
         help
           SMT scheduler support improves the CPU scheduler's decision making
           when dealing with Intel Pentium 4 chips with HyperThreading at a
@@ -242,7 +242,7 @@ config SCHED_SMT
 
 config SCHED_MC
         bool "Multi-core scheduler support"
-        depends on SMP
+        depends on X86_HT
         default y
         help
           Multi-core scheduler support improves the CPU scheduler's decision
diff --git a/arch/i386/kernel/cpu/common.c b/arch/i386/kernel/cpu/common.c
index 2fa401f19f37..70c87de582c7 100644
--- a/arch/i386/kernel/cpu/common.c
+++ b/arch/i386/kernel/cpu/common.c
@@ -294,7 +294,7 @@ void __cpuinit generic_identify(struct cpuinfo_x86 * c)
                         if (c->x86 >= 0x6)
                                 c->x86_model += ((tfms >> 16) & 0xF) << 4;
                         c->x86_mask = tfms & 15;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                         c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
 #else
                         c->apicid = (ebx >> 24) & 0xFF;
diff --git a/arch/i386/kernel/cpu/intel_cacheinfo.c b/arch/i386/kernel/cpu/intel_cacheinfo.c
index f24a0145024c..8a92642ea590 100644
--- a/arch/i386/kernel/cpu/intel_cacheinfo.c
+++ b/arch/i386/kernel/cpu/intel_cacheinfo.c
@@ -261,7 +261,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
         unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
         unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
         unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
         unsigned int cpu = (c == &boot_cpu_data) ? 0 : (c - cpu_data);
 #endif
 
@@ -383,14 +383,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
         if (new_l2) {
                 l2 = new_l2;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                 cpu_llc_id[cpu] = l2_id;
 #endif
         }
 
         if (new_l3) {
                 l3 = new_l3;
-#ifdef CONFIG_SMP
+#ifdef CONFIG_X86_HT
                 cpu_llc_id[cpu] = l3_id;
 #endif
         }