aboutsummaryrefslogtreecommitdiffstats
path: root/arch/i386
diff options
context:
space:
mode:
authorRafaƂ Bilski <rafalbilski@interia.pl>2007-06-07 16:31:24 -0400
committerDave Jones <davej@redhat.com>2007-06-21 12:57:53 -0400
commit689eba77cbd0cfaaa3687cbe23e8b534f8ae0ebb (patch)
treee9790923a4a84137e17e288cc427221f58daf162 /arch/i386
parente8666b2718fdb5bf0ea7c3126f7e292bbbf2946b (diff)
[CPUFREQ] Longhaul - Proper register access
In previous commit I used u32 for u16 register. This code will work only when ACPI block address is set. For now it is only for VT8235 and VT8237. Signed-off-by: Rafal Bilski <rafalbilski@interia.pl> Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'arch/i386')
-rw-r--r--arch/i386/kernel/cpu/cpufreq/longhaul.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/i386/kernel/cpu/cpufreq/longhaul.c b/arch/i386/kernel/cpu/cpufreq/longhaul.c
index 2841735e3feb..8eca59d4c8f4 100644
--- a/arch/i386/kernel/cpu/cpufreq/longhaul.c
+++ b/arch/i386/kernel/cpu/cpufreq/longhaul.c
@@ -247,7 +247,7 @@ static void longhaul_setstate(unsigned int table_index)
247 struct cpufreq_freqs freqs; 247 struct cpufreq_freqs freqs;
248 unsigned long flags; 248 unsigned long flags;
249 unsigned int pic1_mask, pic2_mask; 249 unsigned int pic1_mask, pic2_mask;
250 u32 bm_status = 0; 250 u16 bm_status = 0;
251 u32 bm_timeout = 1000; 251 u32 bm_timeout = 1000;
252 unsigned int dir = 0; 252 unsigned int dir = 0;
253 253
@@ -281,14 +281,14 @@ static void longhaul_setstate(unsigned int table_index)
281 outb(0xFE,0x21); /* TMR0 only */ 281 outb(0xFE,0x21); /* TMR0 only */
282 282
283 /* Wait while PCI bus is busy. */ 283 /* Wait while PCI bus is busy. */
284 if (longhaul_flags & USE_NORTHBRIDGE 284 if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
285 || ((pr != NULL) && pr->flags.bm_control)) { 285 || ((pr != NULL) && pr->flags.bm_control))) {
286 bm_status = inl(acpi_regs_addr); 286 bm_status = inw(acpi_regs_addr);
287 bm_status &= 1 << 4; 287 bm_status &= 1 << 4;
288 while (bm_status && bm_timeout) { 288 while (bm_status && bm_timeout) {
289 outl(1 << 4, acpi_regs_addr); 289 outw(1 << 4, acpi_regs_addr);
290 bm_timeout--; 290 bm_timeout--;
291 bm_status = inl(acpi_regs_addr); 291 bm_status = inw(acpi_regs_addr);
292 bm_status &= 1 << 4; 292 bm_status &= 1 << 4;
293 } 293 }
294 } 294 }