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authorClemens Ladisch <clemens@ladisch.de>2005-10-30 18:03:36 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-30 20:37:29 -0500
commit5f819949ee4e5a06c2e0054cbb42f3f0d170d779 (patch)
tree85dfb0366a13b3e0ae073b5838ec8d457fd89518 /arch/i386
parentf00c96f313b07d2eb2845305b9a3395e14385767 (diff)
[PATCH] hpet-RTC: fix timer config register accesses
Make sure that the RTC timer is in non-periodic mode; some stupid BIOS might have initialized it to periodic mode. Furthermore, don't set the SETVAL bit in the config register. This wouldn't have any effect unless the timer was in period mode (which it isn't), and then the actual timer frequency would be half that of the desired one because incrementing the comparator in the interrupt handler would be done after the hardware has already incremented it itself. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Acked-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/i386')
-rw-r--r--arch/i386/kernel/time_hpet.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/i386/kernel/time_hpet.c b/arch/i386/kernel/time_hpet.c
index 23e81fcbeaea..cb1f313858e3 100644
--- a/arch/i386/kernel/time_hpet.c
+++ b/arch/i386/kernel/time_hpet.c
@@ -309,7 +309,8 @@ int hpet_rtc_timer_init(void)
309 local_irq_restore(flags); 309 local_irq_restore(flags);
310 310
311 cfg = hpet_readl(HPET_T1_CFG); 311 cfg = hpet_readl(HPET_T1_CFG);
312 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT; 312 cfg &= ~HPET_TN_PERIODIC;
313 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
313 hpet_writel(cfg, HPET_T1_CFG); 314 hpet_writel(cfg, HPET_T1_CFG);
314 315
315 return 1; 316 return 1;
@@ -335,12 +336,6 @@ static void hpet_rtc_timer_reinit(void)
335 cnt = hpet_readl(HPET_T1_CMP); 336 cnt = hpet_readl(HPET_T1_CMP);
336 cnt += hpet_tick*HZ/hpet_rtc_int_freq; 337 cnt += hpet_tick*HZ/hpet_rtc_int_freq;
337 hpet_writel(cnt, HPET_T1_CMP); 338 hpet_writel(cnt, HPET_T1_CMP);
338
339 cfg = hpet_readl(HPET_T1_CFG);
340 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT;
341 hpet_writel(cfg, HPET_T1_CFG);
342
343 return;
344} 339}
345 340
346/* 341/*