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authorGreg Kroah-Hartman <gregkh@suse.de>2005-06-23 20:35:56 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2005-06-28 00:52:47 -0400
commitd57e26ceb7dbf44cd08128cb6146116d4281b58b (patch)
tree3fd0f4ff6ec93f3b8f4342649a4b717beb97c903 /arch/i386/pci
parent545493917dc90298e1c38f018ad893f5518928e7 (diff)
[PATCH] PCI: use the MCFG table to properly access pci devices (i386)
Now that we have access to the whole MCFG table, let's properly use it for all pci device accesses (as that's what it is there for, some boxes don't put all the busses into one entry.) If, for some reason, the table is incorrect, we fallback to the "old style" of mmconfig accesses, namely, we just assume the first entry in the table is the one for us, and blindly use it. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/i386/pci')
-rw-r--r--arch/i386/pci/mmconfig.c29
1 files changed, 25 insertions, 4 deletions
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index 5fbaa9132258..60f0e7a1162a 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -22,10 +22,31 @@ static u32 mmcfg_last_accessed_device;
22/* 22/*
23 * Functions for accessing PCI configuration space with MMCONFIG accesses 23 * Functions for accessing PCI configuration space with MMCONFIG accesses
24 */ 24 */
25static u32 get_base_addr(unsigned int seg, int bus)
26{
27 int cfg_num = -1;
28 struct acpi_table_mcfg_config *cfg;
29
30 while (1) {
31 ++cfg_num;
32 if (cfg_num >= pci_mmcfg_config_num) {
33 /* something bad is going on, no cfg table is found. */
34 /* so we fall back to the old way we used to do this */
35 /* and just rely on the first entry to be correct. */
36 return pci_mmcfg_config[0].base_address;
37 }
38 cfg = &pci_mmcfg_config[cfg_num];
39 if (cfg->pci_segment_group_number != seg)
40 continue;
41 if ((cfg->start_bus_number <= bus) &&
42 (cfg->end_bus_number >= bus))
43 return cfg->base_address;
44 }
45}
25 46
26static inline void pci_exp_set_dev_base(int bus, int devfn) 47static inline void pci_exp_set_dev_base(unsigned int seg, int bus, int devfn)
27{ 48{
28 u32 dev_base = pci_mmcfg_config[0].base_address | (bus << 20) | (devfn << 12); 49 u32 dev_base = get_base_addr(seg, bus) | (bus << 20) | (devfn << 12);
29 if (dev_base != mmcfg_last_accessed_device) { 50 if (dev_base != mmcfg_last_accessed_device) {
30 mmcfg_last_accessed_device = dev_base; 51 mmcfg_last_accessed_device = dev_base;
31 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); 52 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
@@ -42,7 +63,7 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
42 63
43 spin_lock_irqsave(&pci_config_lock, flags); 64 spin_lock_irqsave(&pci_config_lock, flags);
44 65
45 pci_exp_set_dev_base(bus, devfn); 66 pci_exp_set_dev_base(seg, bus, devfn);
46 67
47 switch (len) { 68 switch (len) {
48 case 1: 69 case 1:
@@ -71,7 +92,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
71 92
72 spin_lock_irqsave(&pci_config_lock, flags); 93 spin_lock_irqsave(&pci_config_lock, flags);
73 94
74 pci_exp_set_dev_base(bus, devfn); 95 pci_exp_set_dev_base(seg, bus, devfn);
75 96
76 switch (len) { 97 switch (len) {
77 case 1: 98 case 1: