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authorJeff Garzik <jeff@garzik.org>2006-04-12 16:54:43 -0400
committerJeff Garzik <jeff@garzik.org>2006-04-12 16:54:43 -0400
commita890b15c0990cc8d686edcc85f5fccde71ad5ce9 (patch)
tree73162355b58283a2531f13fbbf663809f95c1483 /arch/i386/pci/mmconfig.c
parent79fa1b677be3a985cc66b9218a4dd09818f1051b (diff)
parent26ec634c31a11a003040e10b4d650495158632fd (diff)
Merge branch 'upstream'
Diffstat (limited to 'arch/i386/pci/mmconfig.c')
-rw-r--r--arch/i386/pci/mmconfig.c67
1 files changed, 44 insertions, 23 deletions
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index 613789071f30..6b1ea0c9a570 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -12,14 +12,20 @@
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/acpi.h> 14#include <linux/acpi.h>
15#include <asm/e820.h>
15#include "pci.h" 16#include "pci.h"
16 17
18#define MMCONFIG_APER_SIZE (256*1024*1024)
19
20/* Assume systems with more busses have correct MCFG */
21#define MAX_CHECK_BUS 16
22
17#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG)) 23#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
18 24
19/* The base address of the last MMCONFIG device accessed */ 25/* The base address of the last MMCONFIG device accessed */
20static u32 mmcfg_last_accessed_device; 26static u32 mmcfg_last_accessed_device;
21 27
22static DECLARE_BITMAP(fallback_slots, 32); 28static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
23 29
24/* 30/*
25 * Functions for accessing PCI configuration space with MMCONFIG accesses 31 * Functions for accessing PCI configuration space with MMCONFIG accesses
@@ -29,8 +35,8 @@ static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
29 int cfg_num = -1; 35 int cfg_num = -1;
30 struct acpi_table_mcfg_config *cfg; 36 struct acpi_table_mcfg_config *cfg;
31 37
32 if (seg == 0 && bus == 0 && 38 if (seg == 0 && bus < MAX_CHECK_BUS &&
33 test_bit(PCI_SLOT(devfn), fallback_slots)) 39 test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
34 return 0; 40 return 0;
35 41
36 while (1) { 42 while (1) {
@@ -74,8 +80,10 @@ static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
74 unsigned long flags; 80 unsigned long flags;
75 u32 base; 81 u32 base;
76 82
77 if (!value || (bus > 255) || (devfn > 255) || (reg > 4095)) 83 if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
84 *value = -1;
78 return -EINVAL; 85 return -EINVAL;
86 }
79 87
80 base = get_base_addr(seg, bus, devfn); 88 base = get_base_addr(seg, bus, devfn);
81 if (!base) 89 if (!base)
@@ -146,29 +154,34 @@ static struct pci_raw_ops pci_mmcfg = {
146 Normally this can be expressed in the MCFG by not listing them 154 Normally this can be expressed in the MCFG by not listing them
147 and assigning suitable _SEGs, but this isn't implemented in some BIOS. 155 and assigning suitable _SEGs, but this isn't implemented in some BIOS.
148 Instead try to discover all devices on bus 0 that are unreachable using MM 156 Instead try to discover all devices on bus 0 that are unreachable using MM
149 and fallback for them. 157 and fallback for them. */
150 We only do this for bus 0/seg 0 */
151static __init void unreachable_devices(void) 158static __init void unreachable_devices(void)
152{ 159{
153 int i; 160 int i, k;
154 unsigned long flags; 161 unsigned long flags;
155 162
156 for (i = 0; i < 32; i++) { 163 for (k = 0; k < MAX_CHECK_BUS; k++) {
157 u32 val1; 164 for (i = 0; i < 32; i++) {
158 u32 addr; 165 u32 val1;
159 166 u32 addr;
160 pci_conf1_read(0, 0, PCI_DEVFN(i, 0), 0, 4, &val1); 167
161 if (val1 == 0xffffffff) 168 pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
162 continue; 169 if (val1 == 0xffffffff)
163 170 continue;
164 /* Locking probably not needed, but safer */ 171
165 spin_lock_irqsave(&pci_config_lock, flags); 172 /* Locking probably not needed, but safer */
166 addr = get_base_addr(0, 0, PCI_DEVFN(i, 0)); 173 spin_lock_irqsave(&pci_config_lock, flags);
167 if (addr != 0) 174 addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
168 pci_exp_set_dev_base(addr, 0, PCI_DEVFN(i, 0)); 175 if (addr != 0)
169 if (addr == 0 || readl((u32 __iomem *)mmcfg_virt_addr) != val1) 176 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
170 set_bit(i, fallback_slots); 177 if (addr == 0 ||
171 spin_unlock_irqrestore(&pci_config_lock, flags); 178 readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
179 set_bit(i, fallback_slots);
180 printk(KERN_NOTICE
181 "PCI: No mmconfig possible on %x:%x\n", k, i);
182 }
183 spin_unlock_irqrestore(&pci_config_lock, flags);
184 }
172 } 185 }
173} 186}
174 187
@@ -183,6 +196,14 @@ void __init pci_mmcfg_init(void)
183 (pci_mmcfg_config[0].base_address == 0)) 196 (pci_mmcfg_config[0].base_address == 0))
184 return; 197 return;
185 198
199 if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
200 pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
201 E820_RESERVED)) {
202 printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
203 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
204 return;
205 }
206
186 printk(KERN_INFO "PCI: Using MMCONFIG\n"); 207 printk(KERN_INFO "PCI: Using MMCONFIG\n");
187 raw_pci_ops = &pci_mmcfg; 208 raw_pci_ops = &pci_mmcfg;
188 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 209 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;