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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/i386/mach-voyager
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/i386/mach-voyager')
-rw-r--r--arch/i386/mach-voyager/Makefile8
-rw-r--r--arch/i386/mach-voyager/setup.c48
-rw-r--r--arch/i386/mach-voyager/voyager_basic.c325
-rw-r--r--arch/i386/mach-voyager/voyager_cat.c1178
-rw-r--r--arch/i386/mach-voyager/voyager_smp.c1931
-rw-r--r--arch/i386/mach-voyager/voyager_thread.c167
6 files changed, 3657 insertions, 0 deletions
diff --git a/arch/i386/mach-voyager/Makefile b/arch/i386/mach-voyager/Makefile
new file mode 100644
index 000000000000..f24d29651318
--- /dev/null
+++ b/arch/i386/mach-voyager/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the linux kernel.
3#
4
5EXTRA_CFLAGS += -I../kernel
6obj-y := setup.o voyager_basic.o voyager_thread.o
7
8obj-$(CONFIG_SMP) += voyager_smp.o voyager_cat.o
diff --git a/arch/i386/mach-voyager/setup.c b/arch/i386/mach-voyager/setup.c
new file mode 100644
index 000000000000..df123fc487bb
--- /dev/null
+++ b/arch/i386/mach-voyager/setup.c
@@ -0,0 +1,48 @@
1/*
2 * Machine specific setup for generic
3 */
4
5#include <linux/config.h>
6#include <linux/init.h>
7#include <linux/irq.h>
8#include <linux/interrupt.h>
9#include <asm/acpi.h>
10#include <asm/arch_hooks.h>
11
12void __init pre_intr_init_hook(void)
13{
14 init_ISA_irqs();
15}
16
17/*
18 * IRQ2 is cascade interrupt to second interrupt controller
19 */
20static struct irqaction irq2 = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL};
21
22void __init intr_init_hook(void)
23{
24#ifdef CONFIG_SMP
25 smp_intr_init();
26#endif
27
28 if (!acpi_ioapic)
29 setup_irq(2, &irq2);
30}
31
32void __init pre_setup_arch_hook(void)
33{
34 /* Voyagers run their CPUs from independent clocks, so disable
35 * the TSC code because we can't sync them */
36 tsc_disable = 1;
37}
38
39void __init trap_init_hook(void)
40{
41}
42
43static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
44
45void __init time_init_hook(void)
46{
47 setup_irq(0, &irq0);
48}
diff --git a/arch/i386/mach-voyager/voyager_basic.c b/arch/i386/mach-voyager/voyager_basic.c
new file mode 100644
index 000000000000..602aea240e9b
--- /dev/null
+++ b/arch/i386/mach-voyager/voyager_basic.c
@@ -0,0 +1,325 @@
1/* Copyright (C) 1999,2001
2 *
3 * Author: J.E.J.Bottomley@HansenPartnership.com
4 *
5 * linux/arch/i386/kernel/voyager.c
6 *
7 * This file contains all the voyager specific routines for getting
8 * initialisation of the architecture to function. For additional
9 * features see:
10 *
11 * voyager_cat.c - Voyager CAT bus interface
12 * voyager_smp.c - Voyager SMP hal (emulates linux smp.c)
13 */
14
15#include <linux/config.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/sched.h>
19#include <linux/ptrace.h>
20#include <linux/ioport.h>
21#include <linux/interrupt.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/reboot.h>
25#include <linux/sysrq.h>
26#include <asm/io.h>
27#include <asm/voyager.h>
28#include <asm/vic.h>
29#include <linux/pm.h>
30#include <linux/irq.h>
31#include <asm/tlbflush.h>
32#include <asm/arch_hooks.h>
33
34/*
35 * Power off function, if any
36 */
37void (*pm_power_off)(void);
38
39int voyager_level = 0;
40
41struct voyager_SUS *voyager_SUS = NULL;
42
43#ifdef CONFIG_SMP
44static void
45voyager_dump(int dummy1, struct pt_regs *dummy2, struct tty_struct *dummy3)
46{
47 /* get here via a sysrq */
48 voyager_smp_dump();
49}
50
51static struct sysrq_key_op sysrq_voyager_dump_op = {
52 .handler = voyager_dump,
53 .help_msg = "Voyager",
54 .action_msg = "Dump Voyager Status",
55};
56#endif
57
58void
59voyager_detect(struct voyager_bios_info *bios)
60{
61 if(bios->len != 0xff) {
62 int class = (bios->class_1 << 8)
63 | (bios->class_2 & 0xff);
64
65 printk("Voyager System detected.\n"
66 " Class %x, Revision %d.%d\n",
67 class, bios->major, bios->minor);
68 if(class == VOYAGER_LEVEL4)
69 voyager_level = 4;
70 else if(class < VOYAGER_LEVEL5_AND_ABOVE)
71 voyager_level = 3;
72 else
73 voyager_level = 5;
74 printk(" Architecture Level %d\n", voyager_level);
75 if(voyager_level < 4)
76 printk("\n**WARNING**: Voyager HAL only supports Levels 4 and 5 Architectures at the moment\n\n");
77 /* install the power off handler */
78 pm_power_off = voyager_power_off;
79#ifdef CONFIG_SMP
80 register_sysrq_key('v', &sysrq_voyager_dump_op);
81#endif
82 } else {
83 printk("\n\n**WARNING**: No Voyager Subsystem Found\n");
84 }
85}
86
87void
88voyager_system_interrupt(int cpl, void *dev_id, struct pt_regs *regs)
89{
90 printk("Voyager: detected system interrupt\n");
91}
92
93/* Routine to read information from the extended CMOS area */
94__u8
95voyager_extended_cmos_read(__u16 addr)
96{
97 outb(addr & 0xff, 0x74);
98 outb((addr >> 8) & 0xff, 0x75);
99 return inb(0x76);
100}
101
102/* internal definitions for the SUS Click Map of memory */
103
104#define CLICK_ENTRIES 16
105#define CLICK_SIZE 4096 /* click to byte conversion for Length */
106
107typedef struct ClickMap {
108 struct Entry {
109 __u32 Address;
110 __u32 Length;
111 } Entry[CLICK_ENTRIES];
112} ClickMap_t;
113
114
115/* This routine is pretty much an awful hack to read the bios clickmap by
116 * mapping it into page 0. There are usually three regions in the map:
117 * Base Memory
118 * Extended Memory
119 * zero length marker for end of map
120 *
121 * Returns are 0 for failure and 1 for success on extracting region.
122 */
123int __init
124voyager_memory_detect(int region, __u32 *start, __u32 *length)
125{
126 int i;
127 int retval = 0;
128 __u8 cmos[4];
129 ClickMap_t *map;
130 unsigned long map_addr;
131 unsigned long old;
132
133 if(region >= CLICK_ENTRIES) {
134 printk("Voyager: Illegal ClickMap region %d\n", region);
135 return 0;
136 }
137
138 for(i = 0; i < sizeof(cmos); i++)
139 cmos[i] = voyager_extended_cmos_read(VOYAGER_MEMORY_CLICKMAP + i);
140
141 map_addr = *(unsigned long *)cmos;
142
143 /* steal page 0 for this */
144 old = pg0[0];
145 pg0[0] = ((map_addr & PAGE_MASK) | _PAGE_RW | _PAGE_PRESENT);
146 local_flush_tlb();
147 /* now clear everything out but page 0 */
148 map = (ClickMap_t *)(map_addr & (~PAGE_MASK));
149
150 /* zero length is the end of the clickmap */
151 if(map->Entry[region].Length != 0) {
152 *length = map->Entry[region].Length * CLICK_SIZE;
153 *start = map->Entry[region].Address;
154 retval = 1;
155 }
156
157 /* replace the mapping */
158 pg0[0] = old;
159 local_flush_tlb();
160 return retval;
161}
162
163/* voyager specific handling code for timer interrupts. Used to hand
164 * off the timer tick to the SMP code, since the VIC doesn't have an
165 * internal timer (The QIC does, but that's another story). */
166void
167voyager_timer_interrupt(struct pt_regs *regs)
168{
169 if((jiffies & 0x3ff) == 0) {
170
171 /* There seems to be something flaky in either
172 * hardware or software that is resetting the timer 0
173 * count to something much higher than it should be
174 * This seems to occur in the boot sequence, just
175 * before root is mounted. Therefore, every 10
176 * seconds or so, we sanity check the timer zero count
177 * and kick it back to where it should be.
178 *
179 * FIXME: This is the most awful hack yet seen. I
180 * should work out exactly what is interfering with
181 * the timer count settings early in the boot sequence
182 * and swiftly introduce it to something sharp and
183 * pointy. */
184 __u16 val;
185 extern spinlock_t i8253_lock;
186
187 spin_lock(&i8253_lock);
188
189 outb_p(0x00, 0x43);
190 val = inb_p(0x40);
191 val |= inb(0x40) << 8;
192 spin_unlock(&i8253_lock);
193
194 if(val > LATCH) {
195 printk("\nVOYAGER: countdown timer value too high (%d), resetting\n\n", val);
196 spin_lock(&i8253_lock);
197 outb(0x34,0x43);
198 outb_p(LATCH & 0xff , 0x40); /* LSB */
199 outb(LATCH >> 8 , 0x40); /* MSB */
200 spin_unlock(&i8253_lock);
201 }
202 }
203#ifdef CONFIG_SMP
204 smp_vic_timer_interrupt(regs);
205#endif
206}
207
208void
209voyager_power_off(void)
210{
211 printk("VOYAGER Power Off\n");
212
213 if(voyager_level == 5) {
214 voyager_cat_power_off();
215 } else if(voyager_level == 4) {
216 /* This doesn't apparently work on most L4 machines,
217 * but the specs say to do this to get automatic power
218 * off. Unfortunately, if it doesn't power off the
219 * machine, it ends up doing a cold restart, which
220 * isn't really intended, so comment out the code */
221#if 0
222 int port;
223
224
225 /* enable the voyager Configuration Space */
226 outb((inb(VOYAGER_MC_SETUP) & 0xf0) | 0x8,
227 VOYAGER_MC_SETUP);
228 /* the port for the power off flag is an offset from the
229 floating base */
230 port = (inb(VOYAGER_SSPB_RELOCATION_PORT) << 8) + 0x21;
231 /* set the power off flag */
232 outb(inb(port) | 0x1, port);
233#endif
234 }
235 /* and wait for it to happen */
236 for(;;) {
237 __asm("cli");
238 __asm("hlt");
239 }
240}
241
242/* copied from process.c */
243static inline void
244kb_wait(void)
245{
246 int i;
247
248 for (i=0; i<0x10000; i++)
249 if ((inb_p(0x64) & 0x02) == 0)
250 break;
251}
252
253void
254machine_restart(char *cmd)
255{
256 printk("Voyager Warm Restart\n");
257 kb_wait();
258
259 if(voyager_level == 5) {
260 /* write magic values to the RTC to inform system that
261 * shutdown is beginning */
262 outb(0x8f, 0x70);
263 outb(0x5 , 0x71);
264
265 udelay(50);
266 outb(0xfe,0x64); /* pull reset low */
267 } else if(voyager_level == 4) {
268 __u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8;
269 __u8 basebd = inb(VOYAGER_MC_SETUP);
270
271 outb(basebd | 0x08, VOYAGER_MC_SETUP);
272 outb(0x02, catbase + 0x21);
273 }
274 for(;;) {
275 asm("cli");
276 asm("hlt");
277 }
278}
279
280EXPORT_SYMBOL(machine_restart);
281
282void
283mca_nmi_hook(void)
284{
285 __u8 dumpval __attribute__((unused)) = inb(0xf823);
286 __u8 swnmi __attribute__((unused)) = inb(0xf813);
287
288 /* FIXME: assume dump switch pressed */
289 /* check to see if the dump switch was pressed */
290 VDEBUG(("VOYAGER: dumpval = 0x%x, swnmi = 0x%x\n", dumpval, swnmi));
291 /* clear swnmi */
292 outb(0xff, 0xf813);
293 /* tell SUS to ignore dump */
294 if(voyager_level == 5 && voyager_SUS != NULL) {
295 if(voyager_SUS->SUS_mbox == VOYAGER_DUMP_BUTTON_NMI) {
296 voyager_SUS->kernel_mbox = VOYAGER_NO_COMMAND;
297 voyager_SUS->kernel_flags |= VOYAGER_OS_IN_PROGRESS;
298 udelay(1000);
299 voyager_SUS->kernel_mbox = VOYAGER_IGNORE_DUMP;
300 voyager_SUS->kernel_flags &= ~VOYAGER_OS_IN_PROGRESS;
301 }
302 }
303 printk(KERN_ERR "VOYAGER: Dump switch pressed, printing CPU%d tracebacks\n", smp_processor_id());
304 show_stack(NULL, NULL);
305 show_state();
306}
307
308
309
310void
311machine_halt(void)
312{
313 /* treat a halt like a power off */
314 machine_power_off();
315}
316
317EXPORT_SYMBOL(machine_halt);
318
319void machine_power_off(void)
320{
321 if (pm_power_off)
322 pm_power_off();
323}
324
325EXPORT_SYMBOL(machine_power_off);
diff --git a/arch/i386/mach-voyager/voyager_cat.c b/arch/i386/mach-voyager/voyager_cat.c
new file mode 100644
index 000000000000..23967fe658d3
--- /dev/null
+++ b/arch/i386/mach-voyager/voyager_cat.c
@@ -0,0 +1,1178 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_cat.c
8 *
9 * This file contains all the logic for manipulating the CAT bus
10 * in a level 5 machine.
11 *
12 * The CAT bus is a serial configuration and test bus. Its primary
13 * uses are to probe the initial configuration of the system and to
14 * diagnose error conditions when a system interrupt occurs. The low
15 * level interface is fairly primitive, so most of this file consists
16 * of bit shift manipulations to send and receive packets on the
17 * serial bus */
18
19#include <linux/config.h>
20#include <linux/types.h>
21#include <linux/completion.h>
22#include <linux/sched.h>
23#include <asm/voyager.h>
24#include <asm/vic.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29#include <asm/io.h>
30
31#ifdef VOYAGER_CAT_DEBUG
32#define CDEBUG(x) printk x
33#else
34#define CDEBUG(x)
35#endif
36
37/* the CAT command port */
38#define CAT_CMD (sspb + 0xe)
39/* the CAT data port */
40#define CAT_DATA (sspb + 0xd)
41
42/* the internal cat functions */
43static void cat_pack(__u8 *msg, __u16 start_bit, __u8 *data,
44 __u16 num_bits);
45static void cat_unpack(__u8 *msg, __u16 start_bit, __u8 *data,
46 __u16 num_bits);
47static void cat_build_header(__u8 *header, const __u16 len,
48 const __u16 smallest_reg_bits,
49 const __u16 longest_reg_bits);
50static int cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp,
51 __u8 reg, __u8 op);
52static int cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp,
53 __u8 reg, __u8 *value);
54static int cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes,
55 __u8 pad_bits);
56static int cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
57 __u8 value);
58static int cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
59 __u8 *value);
60static int cat_subread(voyager_module_t *modp, voyager_asic_t *asicp,
61 __u16 offset, __u16 len, void *buf);
62static int cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp,
63 __u8 reg, __u8 value);
64static int cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp);
65static int cat_connect(voyager_module_t *modp, voyager_asic_t *asicp);
66
67static inline const char *
68cat_module_name(int module_id)
69{
70 switch(module_id) {
71 case 0x10:
72 return "Processor Slot 0";
73 case 0x11:
74 return "Processor Slot 1";
75 case 0x12:
76 return "Processor Slot 2";
77 case 0x13:
78 return "Processor Slot 4";
79 case 0x14:
80 return "Memory Slot 0";
81 case 0x15:
82 return "Memory Slot 1";
83 case 0x18:
84 return "Primary Microchannel";
85 case 0x19:
86 return "Secondary Microchannel";
87 case 0x1a:
88 return "Power Supply Interface";
89 case 0x1c:
90 return "Processor Slot 5";
91 case 0x1d:
92 return "Processor Slot 6";
93 case 0x1e:
94 return "Processor Slot 7";
95 case 0x1f:
96 return "Processor Slot 8";
97 default:
98 return "Unknown Module";
99 }
100}
101
102static int sspb = 0; /* stores the super port location */
103int voyager_8slot = 0; /* set to true if a 51xx monster */
104
105voyager_module_t *voyager_cat_list;
106
107/* the I/O port assignments for the VIC and QIC */
108static struct resource vic_res = {
109 "Voyager Interrupt Controller", 0xFC00, 0xFC6F };
110static struct resource qic_res = {
111 "Quad Interrupt Controller", 0xFC70, 0xFCFF };
112
113/* This function is used to pack a data bit stream inside a message.
114 * It writes num_bits of the data buffer in msg starting at start_bit.
115 * Note: This function assumes that any unused bit in the data stream
116 * is set to zero so that the ors will work correctly */
117#define BITS_PER_BYTE 8
118static void
119cat_pack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits)
120{
121 /* compute initial shift needed */
122 const __u16 offset = start_bit % BITS_PER_BYTE;
123 __u16 len = num_bits / BITS_PER_BYTE;
124 __u16 byte = start_bit / BITS_PER_BYTE;
125 __u16 residue = (num_bits % BITS_PER_BYTE) + offset;
126 int i;
127
128 /* adjust if we have more than a byte of residue */
129 if(residue >= BITS_PER_BYTE) {
130 residue -= BITS_PER_BYTE;
131 len++;
132 }
133
134 /* clear out the bits. We assume here that if len==0 then
135 * residue >= offset. This is always true for the catbus
136 * operations */
137 msg[byte] &= 0xff << (BITS_PER_BYTE - offset);
138 msg[byte++] |= data[0] >> offset;
139 if(len == 0)
140 return;
141 for(i = 1; i < len; i++)
142 msg[byte++] = (data[i-1] << (BITS_PER_BYTE - offset))
143 | (data[i] >> offset);
144 if(residue != 0) {
145 __u8 mask = 0xff >> residue;
146 __u8 last_byte = data[i-1] << (BITS_PER_BYTE - offset)
147 | (data[i] >> offset);
148
149 last_byte &= ~mask;
150 msg[byte] &= mask;
151 msg[byte] |= last_byte;
152 }
153 return;
154}
155/* unpack the data again (same arguments as cat_pack()). data buffer
156 * must be zero populated.
157 *
158 * Function: given a message string move to start_bit and copy num_bits into
159 * data (starting at bit 0 in data).
160 */
161static void
162cat_unpack(__u8 *msg, const __u16 start_bit, __u8 *data, const __u16 num_bits)
163{
164 /* compute initial shift needed */
165 const __u16 offset = start_bit % BITS_PER_BYTE;
166 __u16 len = num_bits / BITS_PER_BYTE;
167 const __u8 last_bits = num_bits % BITS_PER_BYTE;
168 __u16 byte = start_bit / BITS_PER_BYTE;
169 int i;
170
171 if(last_bits != 0)
172 len++;
173
174 /* special case: want < 8 bits from msg and we can get it from
175 * a single byte of the msg */
176 if(len == 0 && BITS_PER_BYTE - offset >= num_bits) {
177 data[0] = msg[byte] << offset;
178 data[0] &= 0xff >> (BITS_PER_BYTE - num_bits);
179 return;
180 }
181 for(i = 0; i < len; i++) {
182 /* this annoying if has to be done just in case a read of
183 * msg one beyond the array causes a panic */
184 if(offset != 0) {
185 data[i] = msg[byte++] << offset;
186 data[i] |= msg[byte] >> (BITS_PER_BYTE - offset);
187 }
188 else {
189 data[i] = msg[byte++];
190 }
191 }
192 /* do we need to truncate the final byte */
193 if(last_bits != 0) {
194 data[i-1] &= 0xff << (BITS_PER_BYTE - last_bits);
195 }
196 return;
197}
198
199static void
200cat_build_header(__u8 *header, const __u16 len, const __u16 smallest_reg_bits,
201 const __u16 longest_reg_bits)
202{
203 int i;
204 __u16 start_bit = (smallest_reg_bits - 1) % BITS_PER_BYTE;
205 __u8 *last_byte = &header[len - 1];
206
207 if(start_bit == 0)
208 start_bit = 1; /* must have at least one bit in the hdr */
209
210 for(i=0; i < len; i++)
211 header[i] = 0;
212
213 for(i = start_bit; i > 0; i--)
214 *last_byte = ((*last_byte) << 1) + 1;
215
216}
217
218static int
219cat_sendinst(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg, __u8 op)
220{
221 __u8 parity, inst, inst_buf[4] = { 0 };
222 __u8 iseq[VOYAGER_MAX_SCAN_PATH], hseq[VOYAGER_MAX_REG_SIZE];
223 __u16 ibytes, hbytes, padbits;
224 int i;
225
226 /*
227 * Parity is the parity of the register number + 1 (READ_REGISTER
228 * and WRITE_REGISTER always add '1' to the number of bits == 1)
229 */
230 parity = (__u8)(1 + (reg & 0x01) +
231 ((__u8)(reg & 0x02) >> 1) +
232 ((__u8)(reg & 0x04) >> 2) +
233 ((__u8)(reg & 0x08) >> 3)) % 2;
234
235 inst = ((parity << 7) | (reg << 2) | op);
236
237 outb(VOYAGER_CAT_IRCYC, CAT_CMD);
238 if(!modp->scan_path_connected) {
239 if(asicp->asic_id != VOYAGER_CAT_ID) {
240 printk("**WARNING***: cat_sendinst has disconnected scan path not to CAT asic\n");
241 return 1;
242 }
243 outb(VOYAGER_CAT_HEADER, CAT_DATA);
244 outb(inst, CAT_DATA);
245 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
246 CDEBUG(("VOYAGER CAT: cat_sendinst failed to get CAT_HEADER\n"));
247 return 1;
248 }
249 return 0;
250 }
251 ibytes = modp->inst_bits / BITS_PER_BYTE;
252 if((padbits = modp->inst_bits % BITS_PER_BYTE) != 0) {
253 padbits = BITS_PER_BYTE - padbits;
254 ibytes++;
255 }
256 hbytes = modp->largest_reg / BITS_PER_BYTE;
257 if(modp->largest_reg % BITS_PER_BYTE)
258 hbytes++;
259 CDEBUG(("cat_sendinst: ibytes=%d, hbytes=%d\n", ibytes, hbytes));
260 /* initialise the instruction sequence to 0xff */
261 for(i=0; i < ibytes + hbytes; i++)
262 iseq[i] = 0xff;
263 cat_build_header(hseq, hbytes, modp->smallest_reg, modp->largest_reg);
264 cat_pack(iseq, modp->inst_bits, hseq, hbytes * BITS_PER_BYTE);
265 inst_buf[0] = inst;
266 inst_buf[1] = 0xFF >> (modp->largest_reg % BITS_PER_BYTE);
267 cat_pack(iseq, asicp->bit_location, inst_buf, asicp->ireg_length);
268#ifdef VOYAGER_CAT_DEBUG
269 printk("ins = 0x%x, iseq: ", inst);
270 for(i=0; i< ibytes + hbytes; i++)
271 printk("0x%x ", iseq[i]);
272 printk("\n");
273#endif
274 if(cat_shiftout(iseq, ibytes, hbytes, padbits)) {
275 CDEBUG(("VOYAGER CAT: cat_sendinst: cat_shiftout failed\n"));
276 return 1;
277 }
278 CDEBUG(("CAT SHIFTOUT DONE\n"));
279 return 0;
280}
281
282static int
283cat_getdata(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
284 __u8 *value)
285{
286 if(!modp->scan_path_connected) {
287 if(asicp->asic_id != VOYAGER_CAT_ID) {
288 CDEBUG(("VOYAGER CAT: ERROR: cat_getdata to CAT asic with scan path connected\n"));
289 return 1;
290 }
291 if(reg > VOYAGER_SUBADDRHI)
292 outb(VOYAGER_CAT_RUN, CAT_CMD);
293 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
294 outb(VOYAGER_CAT_HEADER, CAT_DATA);
295 *value = inb(CAT_DATA);
296 outb(0xAA, CAT_DATA);
297 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
298 CDEBUG(("cat_getdata: failed to get VOYAGER_CAT_HEADER\n"));
299 return 1;
300 }
301 return 0;
302 }
303 else {
304 __u16 sbits = modp->num_asics -1 + asicp->ireg_length;
305 __u16 sbytes = sbits / BITS_PER_BYTE;
306 __u16 tbytes;
307 __u8 string[VOYAGER_MAX_SCAN_PATH], trailer[VOYAGER_MAX_REG_SIZE];
308 __u8 padbits;
309 int i;
310
311 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
312
313 if((padbits = sbits % BITS_PER_BYTE) != 0) {
314 padbits = BITS_PER_BYTE - padbits;
315 sbytes++;
316 }
317 tbytes = asicp->ireg_length / BITS_PER_BYTE;
318 if(asicp->ireg_length % BITS_PER_BYTE)
319 tbytes++;
320 CDEBUG(("cat_getdata: tbytes = %d, sbytes = %d, padbits = %d\n",
321 tbytes, sbytes, padbits));
322 cat_build_header(trailer, tbytes, 1, asicp->ireg_length);
323
324
325 for(i = tbytes - 1; i >= 0; i--) {
326 outb(trailer[i], CAT_DATA);
327 string[sbytes + i] = inb(CAT_DATA);
328 }
329
330 for(i = sbytes - 1; i >= 0; i--) {
331 outb(0xaa, CAT_DATA);
332 string[i] = inb(CAT_DATA);
333 }
334 *value = 0;
335 cat_unpack(string, padbits + (tbytes * BITS_PER_BYTE) + asicp->asic_location, value, asicp->ireg_length);
336#ifdef VOYAGER_CAT_DEBUG
337 printk("value=0x%x, string: ", *value);
338 for(i=0; i< tbytes+sbytes; i++)
339 printk("0x%x ", string[i]);
340 printk("\n");
341#endif
342
343 /* sanity check the rest of the return */
344 for(i=0; i < tbytes; i++) {
345 __u8 input = 0;
346
347 cat_unpack(string, padbits + (i * BITS_PER_BYTE), &input, BITS_PER_BYTE);
348 if(trailer[i] != input) {
349 CDEBUG(("cat_getdata: failed to sanity check rest of ret(%d) 0x%x != 0x%x\n", i, input, trailer[i]));
350 return 1;
351 }
352 }
353 CDEBUG(("cat_getdata DONE\n"));
354 return 0;
355 }
356}
357
358static int
359cat_shiftout(__u8 *data, __u16 data_bytes, __u16 header_bytes, __u8 pad_bits)
360{
361 int i;
362
363 for(i = data_bytes + header_bytes - 1; i >= header_bytes; i--)
364 outb(data[i], CAT_DATA);
365
366 for(i = header_bytes - 1; i >= 0; i--) {
367 __u8 header = 0;
368 __u8 input;
369
370 outb(data[i], CAT_DATA);
371 input = inb(CAT_DATA);
372 CDEBUG(("cat_shiftout: returned 0x%x\n", input));
373 cat_unpack(data, ((data_bytes + i) * BITS_PER_BYTE) - pad_bits,
374 &header, BITS_PER_BYTE);
375 if(input != header) {
376 CDEBUG(("VOYAGER CAT: cat_shiftout failed to return header 0x%x != 0x%x\n", input, header));
377 return 1;
378 }
379 }
380 return 0;
381}
382
383static int
384cat_senddata(voyager_module_t *modp, voyager_asic_t *asicp,
385 __u8 reg, __u8 value)
386{
387 outb(VOYAGER_CAT_DRCYC, CAT_CMD);
388 if(!modp->scan_path_connected) {
389 if(asicp->asic_id != VOYAGER_CAT_ID) {
390 CDEBUG(("VOYAGER CAT: ERROR: scan path disconnected when asic != CAT\n"));
391 return 1;
392 }
393 outb(VOYAGER_CAT_HEADER, CAT_DATA);
394 outb(value, CAT_DATA);
395 if(inb(CAT_DATA) != VOYAGER_CAT_HEADER) {
396 CDEBUG(("cat_senddata: failed to get correct header response to sent data\n"));
397 return 1;
398 }
399 if(reg > VOYAGER_SUBADDRHI) {
400 outb(VOYAGER_CAT_RUN, CAT_CMD);
401 outb(VOYAGER_CAT_END, CAT_CMD);
402 outb(VOYAGER_CAT_RUN, CAT_CMD);
403 }
404
405 return 0;
406 }
407 else {
408 __u16 hbytes = asicp->ireg_length / BITS_PER_BYTE;
409 __u16 dbytes = (modp->num_asics - 1 + asicp->ireg_length)/BITS_PER_BYTE;
410 __u8 padbits, dseq[VOYAGER_MAX_SCAN_PATH],
411 hseq[VOYAGER_MAX_REG_SIZE];
412 int i;
413
414 if((padbits = (modp->num_asics - 1
415 + asicp->ireg_length) % BITS_PER_BYTE) != 0) {
416 padbits = BITS_PER_BYTE - padbits;
417 dbytes++;
418 }
419 if(asicp->ireg_length % BITS_PER_BYTE)
420 hbytes++;
421
422 cat_build_header(hseq, hbytes, 1, asicp->ireg_length);
423
424 for(i = 0; i < dbytes + hbytes; i++)
425 dseq[i] = 0xff;
426 CDEBUG(("cat_senddata: dbytes=%d, hbytes=%d, padbits=%d\n",
427 dbytes, hbytes, padbits));
428 cat_pack(dseq, modp->num_asics - 1 + asicp->ireg_length,
429 hseq, hbytes * BITS_PER_BYTE);
430 cat_pack(dseq, asicp->asic_location, &value,
431 asicp->ireg_length);
432#ifdef VOYAGER_CAT_DEBUG
433 printk("dseq ");
434 for(i=0; i<hbytes+dbytes; i++) {
435 printk("0x%x ", dseq[i]);
436 }
437 printk("\n");
438#endif
439 return cat_shiftout(dseq, dbytes, hbytes, padbits);
440 }
441}
442
443static int
444cat_write(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
445 __u8 value)
446{
447 if(cat_sendinst(modp, asicp, reg, VOYAGER_WRITE_CONFIG))
448 return 1;
449 return cat_senddata(modp, asicp, reg, value);
450}
451
452static int
453cat_read(voyager_module_t *modp, voyager_asic_t *asicp, __u8 reg,
454 __u8 *value)
455{
456 if(cat_sendinst(modp, asicp, reg, VOYAGER_READ_CONFIG))
457 return 1;
458 return cat_getdata(modp, asicp, reg, value);
459}
460
461static int
462cat_subaddrsetup(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
463 __u16 len)
464{
465 __u8 val;
466
467 if(len > 1) {
468 /* set auto increment */
469 __u8 newval;
470
471 if(cat_read(modp, asicp, VOYAGER_AUTO_INC_REG, &val)) {
472 CDEBUG(("cat_subaddrsetup: read of VOYAGER_AUTO_INC_REG failed\n"));
473 return 1;
474 }
475 CDEBUG(("cat_subaddrsetup: VOYAGER_AUTO_INC_REG = 0x%x\n", val));
476 newval = val | VOYAGER_AUTO_INC;
477 if(newval != val) {
478 if(cat_write(modp, asicp, VOYAGER_AUTO_INC_REG, val)) {
479 CDEBUG(("cat_subaddrsetup: write to VOYAGER_AUTO_INC_REG failed\n"));
480 return 1;
481 }
482 }
483 }
484 if(cat_write(modp, asicp, VOYAGER_SUBADDRLO, (__u8)(offset &0xff))) {
485 CDEBUG(("cat_subaddrsetup: write to SUBADDRLO failed\n"));
486 return 1;
487 }
488 if(asicp->subaddr > VOYAGER_SUBADDR_LO) {
489 if(cat_write(modp, asicp, VOYAGER_SUBADDRHI, (__u8)(offset >> 8))) {
490 CDEBUG(("cat_subaddrsetup: write to SUBADDRHI failed\n"));
491 return 1;
492 }
493 cat_read(modp, asicp, VOYAGER_SUBADDRHI, &val);
494 CDEBUG(("cat_subaddrsetup: offset = %d, hi = %d\n", offset, val));
495 }
496 cat_read(modp, asicp, VOYAGER_SUBADDRLO, &val);
497 CDEBUG(("cat_subaddrsetup: offset = %d, lo = %d\n", offset, val));
498 return 0;
499}
500
501static int
502cat_subwrite(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
503 __u16 len, void *buf)
504{
505 int i, retval;
506
507 /* FIXME: need special actions for VOYAGER_CAT_ID here */
508 if(asicp->asic_id == VOYAGER_CAT_ID) {
509 CDEBUG(("cat_subwrite: ATTEMPT TO WRITE TO CAT ASIC\n"));
510 /* FIXME -- This is supposed to be handled better
511 * There is a problem writing to the cat asic in the
512 * PSI. The 30us delay seems to work, though */
513 udelay(30);
514 }
515
516 if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) {
517 printk("cat_subwrite: cat_subaddrsetup FAILED\n");
518 return retval;
519 }
520
521 if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_WRITE_CONFIG)) {
522 printk("cat_subwrite: cat_sendinst FAILED\n");
523 return 1;
524 }
525 for(i = 0; i < len; i++) {
526 if(cat_senddata(modp, asicp, 0xFF, ((__u8 *)buf)[i])) {
527 printk("cat_subwrite: cat_sendata element at %d FAILED\n", i);
528 return 1;
529 }
530 }
531 return 0;
532}
533static int
534cat_subread(voyager_module_t *modp, voyager_asic_t *asicp, __u16 offset,
535 __u16 len, void *buf)
536{
537 int i, retval;
538
539 if((retval = cat_subaddrsetup(modp, asicp, offset, len)) != 0) {
540 CDEBUG(("cat_subread: cat_subaddrsetup FAILED\n"));
541 return retval;
542 }
543
544 if(cat_sendinst(modp, asicp, VOYAGER_SUBADDRDATA, VOYAGER_READ_CONFIG)) {
545 CDEBUG(("cat_subread: cat_sendinst failed\n"));
546 return 1;
547 }
548 for(i = 0; i < len; i++) {
549 if(cat_getdata(modp, asicp, 0xFF,
550 &((__u8 *)buf)[i])) {
551 CDEBUG(("cat_subread: cat_getdata element %d failed\n", i));
552 return 1;
553 }
554 }
555 return 0;
556}
557
558
559/* buffer for storing EPROM data read in during initialisation */
560static __initdata __u8 eprom_buf[0xFFFF];
561static voyager_module_t *voyager_initial_module;
562
563/* Initialise the cat bus components. We assume this is called by the
564 * boot cpu *after* all memory initialisation has been done (so we can
565 * use kmalloc) but before smp initialisation, so we can probe the SMP
566 * configuration and pick up necessary information. */
567void
568voyager_cat_init(void)
569{
570 voyager_module_t **modpp = &voyager_initial_module;
571 voyager_asic_t **asicpp;
572 voyager_asic_t *qabc_asic = NULL;
573 int i, j;
574 unsigned long qic_addr = 0;
575 __u8 qabc_data[0x20];
576 __u8 num_submodules, val;
577 voyager_eprom_hdr_t *eprom_hdr = (voyager_eprom_hdr_t *)&eprom_buf[0];
578
579 __u8 cmos[4];
580 unsigned long addr;
581
582 /* initiallise the SUS mailbox */
583 for(i=0; i<sizeof(cmos); i++)
584 cmos[i] = voyager_extended_cmos_read(VOYAGER_DUMP_LOCATION + i);
585 addr = *(unsigned long *)cmos;
586 if((addr & 0xff000000) != 0xff000000) {
587 printk(KERN_ERR "Voyager failed to get SUS mailbox (addr = 0x%lx\n", addr);
588 } else {
589 static struct resource res;
590
591 res.name = "voyager SUS";
592 res.start = addr;
593 res.end = addr+0x3ff;
594
595 request_resource(&iomem_resource, &res);
596 voyager_SUS = (struct voyager_SUS *)
597 ioremap(addr, 0x400);
598 printk(KERN_NOTICE "Voyager SUS mailbox version 0x%x\n",
599 voyager_SUS->SUS_version);
600 voyager_SUS->kernel_version = VOYAGER_MAILBOX_VERSION;
601 voyager_SUS->kernel_flags = VOYAGER_OS_HAS_SYSINT;
602 }
603
604 /* clear the processor counts */
605 voyager_extended_vic_processors = 0;
606 voyager_quad_processors = 0;
607
608
609
610 printk("VOYAGER: beginning CAT bus probe\n");
611 /* set up the SuperSet Port Block which tells us where the
612 * CAT communication port is */
613 sspb = inb(VOYAGER_SSPB_RELOCATION_PORT) * 0x100;
614 VDEBUG(("VOYAGER DEBUG: sspb = 0x%x\n", sspb));
615
616 /* now find out if were 8 slot or normal */
617 if((inb(VIC_PROC_WHO_AM_I) & EIGHT_SLOT_IDENTIFIER)
618 == EIGHT_SLOT_IDENTIFIER) {
619 voyager_8slot = 1;
620 printk(KERN_NOTICE "Voyager: Eight slot 51xx configuration detected\n");
621 }
622
623 for(i = VOYAGER_MIN_MODULE;
624 i <= VOYAGER_MAX_MODULE; i++) {
625 __u8 input;
626 int asic;
627 __u16 eprom_size;
628 __u16 sp_offset;
629
630 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
631 outb(i, VOYAGER_CAT_CONFIG_PORT);
632
633 /* check the presence of the module */
634 outb(VOYAGER_CAT_RUN, CAT_CMD);
635 outb(VOYAGER_CAT_IRCYC, CAT_CMD);
636 outb(VOYAGER_CAT_HEADER, CAT_DATA);
637 /* stream series of alternating 1's and 0's to stimulate
638 * response */
639 outb(0xAA, CAT_DATA);
640 input = inb(CAT_DATA);
641 outb(VOYAGER_CAT_END, CAT_CMD);
642 if(input != VOYAGER_CAT_HEADER) {
643 continue;
644 }
645 CDEBUG(("VOYAGER DEBUG: found module id 0x%x, %s\n", i,
646 cat_module_name(i)));
647 *modpp = kmalloc(sizeof(voyager_module_t), GFP_KERNEL); /*&voyager_module_storage[cat_count++];*/
648 if(*modpp == NULL) {
649 printk("**WARNING** kmalloc failure in cat_init\n");
650 continue;
651 }
652 memset(*modpp, 0, sizeof(voyager_module_t));
653 /* need temporary asic for cat_subread. It will be
654 * filled in correctly later */
655 (*modpp)->asic = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count];*/
656 if((*modpp)->asic == NULL) {
657 printk("**WARNING** kmalloc failure in cat_init\n");
658 continue;
659 }
660 memset((*modpp)->asic, 0, sizeof(voyager_asic_t));
661 (*modpp)->asic->asic_id = VOYAGER_CAT_ID;
662 (*modpp)->asic->subaddr = VOYAGER_SUBADDR_HI;
663 (*modpp)->module_addr = i;
664 (*modpp)->scan_path_connected = 0;
665 if(i == VOYAGER_PSI) {
666 /* Exception leg for modules with no EEPROM */
667 printk("Module \"%s\"\n", cat_module_name(i));
668 continue;
669 }
670
671 CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET));
672 outb(VOYAGER_CAT_RUN, CAT_CMD);
673 cat_disconnect(*modpp, (*modpp)->asic);
674 if(cat_subread(*modpp, (*modpp)->asic,
675 VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size),
676 &eprom_size)) {
677 printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i);
678 outb(VOYAGER_CAT_END, CAT_CMD);
679 continue;
680 }
681 if(eprom_size > sizeof(eprom_buf)) {
682 printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size);
683 outb(VOYAGER_CAT_END, CAT_CMD);
684 continue;
685 }
686 outb(VOYAGER_CAT_END, CAT_CMD);
687 outb(VOYAGER_CAT_RUN, CAT_CMD);
688 CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size));
689 if(cat_subread(*modpp, (*modpp)->asic, 0,
690 eprom_size, eprom_buf)) {
691 outb(VOYAGER_CAT_END, CAT_CMD);
692 continue;
693 }
694 outb(VOYAGER_CAT_END, CAT_CMD);
695 printk("Module \"%s\", version 0x%x, tracer 0x%x, asics %d\n",
696 cat_module_name(i), eprom_hdr->version_id,
697 *((__u32 *)eprom_hdr->tracer), eprom_hdr->num_asics);
698 (*modpp)->ee_size = eprom_hdr->ee_size;
699 (*modpp)->num_asics = eprom_hdr->num_asics;
700 asicpp = &((*modpp)->asic);
701 sp_offset = eprom_hdr->scan_path_offset;
702 /* All we really care about are the Quad cards. We
703 * identify them because they are in a processor slot
704 * and have only four asics */
705 if((i < 0x10 || (i>=0x14 && i < 0x1c) || i>0x1f)) {
706 modpp = &((*modpp)->next);
707 continue;
708 }
709 /* Now we know it's in a processor slot, does it have
710 * a quad baseboard submodule */
711 outb(VOYAGER_CAT_RUN, CAT_CMD);
712 cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODPRESENT,
713 &num_submodules);
714 /* lowest two bits, active low */
715 num_submodules = ~(0xfc | num_submodules);
716 CDEBUG(("VOYAGER CAT: %d submodules present\n", num_submodules));
717 if(num_submodules == 0) {
718 /* fill in the dyadic extended processors */
719 __u8 cpu = i & 0x07;
720
721 printk("Module \"%s\": Dyadic Processor Card\n",
722 cat_module_name(i));
723 voyager_extended_vic_processors |= (1<<cpu);
724 cpu += 4;
725 voyager_extended_vic_processors |= (1<<cpu);
726 outb(VOYAGER_CAT_END, CAT_CMD);
727 continue;
728 }
729
730 /* now we want to read the asics on the first submodule,
731 * which should be the quad base board */
732
733 cat_read(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, &val);
734 CDEBUG(("cat_init: SUBMODSELECT value = 0x%x\n", val));
735 val = (val & 0x7c) | VOYAGER_QUAD_BASEBOARD;
736 cat_write(*modpp, (*modpp)->asic, VOYAGER_SUBMODSELECT, val);
737
738 outb(VOYAGER_CAT_END, CAT_CMD);
739
740
741 CDEBUG(("cat_init: Reading eeprom for module 0x%x at offset %d\n", i, VOYAGER_XSUM_END_OFFSET));
742 outb(VOYAGER_CAT_RUN, CAT_CMD);
743 cat_disconnect(*modpp, (*modpp)->asic);
744 if(cat_subread(*modpp, (*modpp)->asic,
745 VOYAGER_XSUM_END_OFFSET, sizeof(eprom_size),
746 &eprom_size)) {
747 printk("**WARNING**: Voyager couldn't read EPROM size for module 0x%x\n", i);
748 outb(VOYAGER_CAT_END, CAT_CMD);
749 continue;
750 }
751 if(eprom_size > sizeof(eprom_buf)) {
752 printk("**WARNING**: Voyager insufficient size to read EPROM data, module 0x%x. Need %d\n", i, eprom_size);
753 outb(VOYAGER_CAT_END, CAT_CMD);
754 continue;
755 }
756 outb(VOYAGER_CAT_END, CAT_CMD);
757 outb(VOYAGER_CAT_RUN, CAT_CMD);
758 CDEBUG(("cat_init: module 0x%x, eeprom_size %d\n", i, eprom_size));
759 if(cat_subread(*modpp, (*modpp)->asic, 0,
760 eprom_size, eprom_buf)) {
761 outb(VOYAGER_CAT_END, CAT_CMD);
762 continue;
763 }
764 outb(VOYAGER_CAT_END, CAT_CMD);
765 /* Now do everything for the QBB submodule 1 */
766 (*modpp)->ee_size = eprom_hdr->ee_size;
767 (*modpp)->num_asics = eprom_hdr->num_asics;
768 asicpp = &((*modpp)->asic);
769 sp_offset = eprom_hdr->scan_path_offset;
770 /* get rid of the dummy CAT asic and read the real one */
771 kfree((*modpp)->asic);
772 for(asic=0; asic < (*modpp)->num_asics; asic++) {
773 int j;
774 voyager_asic_t *asicp = *asicpp
775 = kmalloc(sizeof(voyager_asic_t), GFP_KERNEL); /*&voyager_asic_storage[asic_count++];*/
776 voyager_sp_table_t *sp_table;
777 voyager_at_t *asic_table;
778 voyager_jtt_t *jtag_table;
779
780 if(asicp == NULL) {
781 printk("**WARNING** kmalloc failure in cat_init\n");
782 continue;
783 }
784 memset(asicp, 0, sizeof(voyager_asic_t));
785 asicpp = &(asicp->next);
786 asicp->asic_location = asic;
787 sp_table = (voyager_sp_table_t *)(eprom_buf + sp_offset);
788 asicp->asic_id = sp_table->asic_id;
789 asic_table = (voyager_at_t *)(eprom_buf + sp_table->asic_data_offset);
790 for(j=0; j<4; j++)
791 asicp->jtag_id[j] = asic_table->jtag_id[j];
792 jtag_table = (voyager_jtt_t *)(eprom_buf + asic_table->jtag_offset);
793 asicp->ireg_length = jtag_table->ireg_len;
794 asicp->bit_location = (*modpp)->inst_bits;
795 (*modpp)->inst_bits += asicp->ireg_length;
796 if(asicp->ireg_length > (*modpp)->largest_reg)
797 (*modpp)->largest_reg = asicp->ireg_length;
798 if (asicp->ireg_length < (*modpp)->smallest_reg ||
799 (*modpp)->smallest_reg == 0)
800 (*modpp)->smallest_reg = asicp->ireg_length;
801 CDEBUG(("asic 0x%x, ireg_length=%d, bit_location=%d\n",
802 asicp->asic_id, asicp->ireg_length,
803 asicp->bit_location));
804 if(asicp->asic_id == VOYAGER_QUAD_QABC) {
805 CDEBUG(("VOYAGER CAT: QABC ASIC found\n"));
806 qabc_asic = asicp;
807 }
808 sp_offset += sizeof(voyager_sp_table_t);
809 }
810 CDEBUG(("Module inst_bits = %d, largest_reg = %d, smallest_reg=%d\n",
811 (*modpp)->inst_bits, (*modpp)->largest_reg,
812 (*modpp)->smallest_reg));
813 /* OK, now we have the QUAD ASICs set up, use them.
814 * we need to:
815 *
816 * 1. Find the Memory area for the Quad CPIs.
817 * 2. Find the Extended VIC processor
818 * 3. Configure a second extended VIC processor (This
819 * cannot be done for the 51xx.
820 * */
821 outb(VOYAGER_CAT_RUN, CAT_CMD);
822 cat_connect(*modpp, (*modpp)->asic);
823 CDEBUG(("CAT CONNECTED!!\n"));
824 cat_subread(*modpp, qabc_asic, 0, sizeof(qabc_data), qabc_data);
825 qic_addr = qabc_data[5] << 8;
826 qic_addr = (qic_addr | qabc_data[6]) << 8;
827 qic_addr = (qic_addr | qabc_data[7]) << 8;
828 printk("Module \"%s\": Quad Processor Card; CPI 0x%lx, SET=0x%x\n",
829 cat_module_name(i), qic_addr, qabc_data[8]);
830#if 0 /* plumbing fails---FIXME */
831 if((qabc_data[8] & 0xf0) == 0) {
832 /* FIXME: 32 way 8 CPU slot monster cannot be
833 * plumbed this way---need to check for it */
834
835 printk("Plumbing second Extended Quad Processor\n");
836 /* second VIC line hardwired to Quad CPU 1 */
837 qabc_data[8] |= 0x20;
838 cat_subwrite(*modpp, qabc_asic, 8, 1, &qabc_data[8]);
839#ifdef VOYAGER_CAT_DEBUG
840 /* verify plumbing */
841 cat_subread(*modpp, qabc_asic, 8, 1, &qabc_data[8]);
842 if((qabc_data[8] & 0xf0) == 0) {
843 CDEBUG(("PLUMBING FAILED: 0x%x\n", qabc_data[8]));
844 }
845#endif
846 }
847#endif
848
849 {
850 struct resource *res = kmalloc(sizeof(struct resource),GFP_KERNEL);
851 memset(res, 0, sizeof(struct resource));
852 res->name = kmalloc(128, GFP_KERNEL);
853 sprintf((char *)res->name, "Voyager %s Quad CPI", cat_module_name(i));
854 res->start = qic_addr;
855 res->end = qic_addr + 0x3ff;
856 request_resource(&iomem_resource, res);
857 }
858
859 qic_addr = (unsigned long)ioremap(qic_addr, 0x400);
860
861 for(j = 0; j < 4; j++) {
862 __u8 cpu;
863
864 if(voyager_8slot) {
865 /* 8 slot has a different mapping,
866 * each slot has only one vic line, so
867 * 1 cpu in each slot must be < 8 */
868 cpu = (i & 0x07) + j*8;
869 } else {
870 cpu = (i & 0x03) + j*4;
871 }
872 if( (qabc_data[8] & (1<<j))) {
873 voyager_extended_vic_processors |= (1<<cpu);
874 }
875 if(qabc_data[8] & (1<<(j+4)) ) {
876 /* Second SET register plumbed: Quad
877 * card has two VIC connected CPUs.
878 * Secondary cannot be booted as a VIC
879 * CPU */
880 voyager_extended_vic_processors |= (1<<cpu);
881 voyager_allowed_boot_processors &= (~(1<<cpu));
882 }
883
884 voyager_quad_processors |= (1<<cpu);
885 voyager_quad_cpi_addr[cpu] = (struct voyager_qic_cpi *)
886 (qic_addr+(j<<8));
887 CDEBUG(("CPU%d: CPI address 0x%lx\n", cpu,
888 (unsigned long)voyager_quad_cpi_addr[cpu]));
889 }
890 outb(VOYAGER_CAT_END, CAT_CMD);
891
892
893
894 *asicpp = NULL;
895 modpp = &((*modpp)->next);
896 }
897 *modpp = NULL;
898 printk("CAT Bus Initialisation finished: extended procs 0x%x, quad procs 0x%x, allowed vic boot = 0x%x\n", voyager_extended_vic_processors, voyager_quad_processors, voyager_allowed_boot_processors);
899 request_resource(&ioport_resource, &vic_res);
900 if(voyager_quad_processors)
901 request_resource(&ioport_resource, &qic_res);
902 /* set up the front power switch */
903}
904
905int
906voyager_cat_readb(__u8 module, __u8 asic, int reg)
907{
908 return 0;
909}
910
911static int
912cat_disconnect(voyager_module_t *modp, voyager_asic_t *asicp)
913{
914 __u8 val;
915 int err = 0;
916
917 if(!modp->scan_path_connected)
918 return 0;
919 if(asicp->asic_id != VOYAGER_CAT_ID) {
920 CDEBUG(("cat_disconnect: ASIC is not CAT\n"));
921 return 1;
922 }
923 err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val);
924 if(err) {
925 CDEBUG(("cat_disconnect: failed to read SCANPATH\n"));
926 return err;
927 }
928 val &= VOYAGER_DISCONNECT_ASIC;
929 err = cat_write(modp, asicp, VOYAGER_SCANPATH, val);
930 if(err) {
931 CDEBUG(("cat_disconnect: failed to write SCANPATH\n"));
932 return err;
933 }
934 outb(VOYAGER_CAT_END, CAT_CMD);
935 outb(VOYAGER_CAT_RUN, CAT_CMD);
936 modp->scan_path_connected = 0;
937
938 return 0;
939}
940
941static int
942cat_connect(voyager_module_t *modp, voyager_asic_t *asicp)
943{
944 __u8 val;
945 int err = 0;
946
947 if(modp->scan_path_connected)
948 return 0;
949 if(asicp->asic_id != VOYAGER_CAT_ID) {
950 CDEBUG(("cat_connect: ASIC is not CAT\n"));
951 return 1;
952 }
953
954 err = cat_read(modp, asicp, VOYAGER_SCANPATH, &val);
955 if(err) {
956 CDEBUG(("cat_connect: failed to read SCANPATH\n"));
957 return err;
958 }
959 val |= VOYAGER_CONNECT_ASIC;
960 err = cat_write(modp, asicp, VOYAGER_SCANPATH, val);
961 if(err) {
962 CDEBUG(("cat_connect: failed to write SCANPATH\n"));
963 return err;
964 }
965 outb(VOYAGER_CAT_END, CAT_CMD);
966 outb(VOYAGER_CAT_RUN, CAT_CMD);
967 modp->scan_path_connected = 1;
968
969 return 0;
970}
971
972void
973voyager_cat_power_off(void)
974{
975 /* Power the machine off by writing to the PSI over the CAT
976 * bus */
977 __u8 data;
978 voyager_module_t psi = { 0 };
979 voyager_asic_t psi_asic = { 0 };
980
981 psi.asic = &psi_asic;
982 psi.asic->asic_id = VOYAGER_CAT_ID;
983 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
984 psi.module_addr = VOYAGER_PSI;
985 psi.scan_path_connected = 0;
986
987 outb(VOYAGER_CAT_END, CAT_CMD);
988 /* Connect the PSI to the CAT Bus */
989 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
990 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
991 outb(VOYAGER_CAT_RUN, CAT_CMD);
992 cat_disconnect(&psi, &psi_asic);
993 /* Read the status */
994 cat_subread(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
995 outb(VOYAGER_CAT_END, CAT_CMD);
996 CDEBUG(("PSI STATUS 0x%x\n", data));
997 /* These two writes are power off prep and perform */
998 data = PSI_CLEAR;
999 outb(VOYAGER_CAT_RUN, CAT_CMD);
1000 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
1001 outb(VOYAGER_CAT_END, CAT_CMD);
1002 data = PSI_POWER_DOWN;
1003 outb(VOYAGER_CAT_RUN, CAT_CMD);
1004 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG, 1, &data);
1005 outb(VOYAGER_CAT_END, CAT_CMD);
1006}
1007
1008struct voyager_status voyager_status = { 0 };
1009
1010void
1011voyager_cat_psi(__u8 cmd, __u16 reg, __u8 *data)
1012{
1013 voyager_module_t psi = { 0 };
1014 voyager_asic_t psi_asic = { 0 };
1015
1016 psi.asic = &psi_asic;
1017 psi.asic->asic_id = VOYAGER_CAT_ID;
1018 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
1019 psi.module_addr = VOYAGER_PSI;
1020 psi.scan_path_connected = 0;
1021
1022 outb(VOYAGER_CAT_END, CAT_CMD);
1023 /* Connect the PSI to the CAT Bus */
1024 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
1025 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
1026 outb(VOYAGER_CAT_RUN, CAT_CMD);
1027 cat_disconnect(&psi, &psi_asic);
1028 switch(cmd) {
1029 case VOYAGER_PSI_READ:
1030 cat_read(&psi, &psi_asic, reg, data);
1031 break;
1032 case VOYAGER_PSI_WRITE:
1033 cat_write(&psi, &psi_asic, reg, *data);
1034 break;
1035 case VOYAGER_PSI_SUBREAD:
1036 cat_subread(&psi, &psi_asic, reg, 1, data);
1037 break;
1038 case VOYAGER_PSI_SUBWRITE:
1039 cat_subwrite(&psi, &psi_asic, reg, 1, data);
1040 break;
1041 default:
1042 printk(KERN_ERR "Voyager PSI, unrecognised command %d\n", cmd);
1043 break;
1044 }
1045 outb(VOYAGER_CAT_END, CAT_CMD);
1046}
1047
1048void
1049voyager_cat_do_common_interrupt(void)
1050{
1051 /* This is caused either by a memory parity error or something
1052 * in the PSI */
1053 __u8 data;
1054 voyager_module_t psi = { 0 };
1055 voyager_asic_t psi_asic = { 0 };
1056 struct voyager_psi psi_reg;
1057 int i;
1058 re_read:
1059 psi.asic = &psi_asic;
1060 psi.asic->asic_id = VOYAGER_CAT_ID;
1061 psi.asic->subaddr = VOYAGER_SUBADDR_HI;
1062 psi.module_addr = VOYAGER_PSI;
1063 psi.scan_path_connected = 0;
1064
1065 outb(VOYAGER_CAT_END, CAT_CMD);
1066 /* Connect the PSI to the CAT Bus */
1067 outb(VOYAGER_CAT_DESELECT, VOYAGER_CAT_CONFIG_PORT);
1068 outb(VOYAGER_PSI, VOYAGER_CAT_CONFIG_PORT);
1069 outb(VOYAGER_CAT_RUN, CAT_CMD);
1070 cat_disconnect(&psi, &psi_asic);
1071 /* Read the status. NOTE: Need to read *all* the PSI regs here
1072 * otherwise the cmn int will be reasserted */
1073 for(i = 0; i < sizeof(psi_reg.regs); i++) {
1074 cat_read(&psi, &psi_asic, i, &((__u8 *)&psi_reg.regs)[i]);
1075 }
1076 outb(VOYAGER_CAT_END, CAT_CMD);
1077 if((psi_reg.regs.checkbit & 0x02) == 0) {
1078 psi_reg.regs.checkbit |= 0x02;
1079 cat_write(&psi, &psi_asic, 5, psi_reg.regs.checkbit);
1080 printk("VOYAGER RE-READ PSI\n");
1081 goto re_read;
1082 }
1083 outb(VOYAGER_CAT_RUN, CAT_CMD);
1084 for(i = 0; i < sizeof(psi_reg.subregs); i++) {
1085 /* This looks strange, but the PSI doesn't do auto increment
1086 * correctly */
1087 cat_subread(&psi, &psi_asic, VOYAGER_PSI_SUPPLY_REG + i,
1088 1, &((__u8 *)&psi_reg.subregs)[i]);
1089 }
1090 outb(VOYAGER_CAT_END, CAT_CMD);
1091#ifdef VOYAGER_CAT_DEBUG
1092 printk("VOYAGER PSI: ");
1093 for(i=0; i<sizeof(psi_reg.regs); i++)
1094 printk("%02x ", ((__u8 *)&psi_reg.regs)[i]);
1095 printk("\n ");
1096 for(i=0; i<sizeof(psi_reg.subregs); i++)
1097 printk("%02x ", ((__u8 *)&psi_reg.subregs)[i]);
1098 printk("\n");
1099#endif
1100 if(psi_reg.regs.intstatus & PSI_MON) {
1101 /* switch off or power fail */
1102
1103 if(psi_reg.subregs.supply & PSI_SWITCH_OFF) {
1104 if(voyager_status.switch_off) {
1105 printk(KERN_ERR "Voyager front panel switch turned off again---Immediate power off!\n");
1106 voyager_cat_power_off();
1107 /* not reached */
1108 } else {
1109 printk(KERN_ERR "Voyager front panel switch turned off\n");
1110 voyager_status.switch_off = 1;
1111 voyager_status.request_from_kernel = 1;
1112 up(&kvoyagerd_sem);
1113 }
1114 /* Tell the hardware we're taking care of the
1115 * shutdown, otherwise it will power the box off
1116 * within 3 seconds of the switch being pressed and,
1117 * which is much more important to us, continue to
1118 * assert the common interrupt */
1119 data = PSI_CLR_SWITCH_OFF;
1120 outb(VOYAGER_CAT_RUN, CAT_CMD);
1121 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_SUPPLY_REG,
1122 1, &data);
1123 outb(VOYAGER_CAT_END, CAT_CMD);
1124 } else {
1125
1126 VDEBUG(("Voyager ac fail reg 0x%x\n",
1127 psi_reg.subregs.ACfail));
1128 if((psi_reg.subregs.ACfail & AC_FAIL_STAT_CHANGE) == 0) {
1129 /* No further update */
1130 return;
1131 }
1132#if 0
1133 /* Don't bother trying to find out who failed.
1134 * FIXME: This probably makes the code incorrect on
1135 * anything other than a 345x */
1136 for(i=0; i< 5; i++) {
1137 if( psi_reg.subregs.ACfail &(1<<i)) {
1138 break;
1139 }
1140 }
1141 printk(KERN_NOTICE "AC FAIL IN SUPPLY %d\n", i);
1142#endif
1143 /* DON'T do this: it shuts down the AC PSI
1144 outb(VOYAGER_CAT_RUN, CAT_CMD);
1145 data = PSI_MASK_MASK | i;
1146 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_MASK,
1147 1, &data);
1148 outb(VOYAGER_CAT_END, CAT_CMD);
1149 */
1150 printk(KERN_ERR "Voyager AC power failure\n");
1151 outb(VOYAGER_CAT_RUN, CAT_CMD);
1152 data = PSI_COLD_START;
1153 cat_subwrite(&psi, &psi_asic, VOYAGER_PSI_GENERAL_REG,
1154 1, &data);
1155 outb(VOYAGER_CAT_END, CAT_CMD);
1156 voyager_status.power_fail = 1;
1157 voyager_status.request_from_kernel = 1;
1158 up(&kvoyagerd_sem);
1159 }
1160
1161
1162 } else if(psi_reg.regs.intstatus & PSI_FAULT) {
1163 /* Major fault! */
1164 printk(KERN_ERR "Voyager PSI Detected major fault, immediate power off!\n");
1165 voyager_cat_power_off();
1166 /* not reached */
1167 } else if(psi_reg.regs.intstatus & (PSI_DC_FAIL | PSI_ALARM
1168 | PSI_CURRENT | PSI_DVM
1169 | PSI_PSCFAULT | PSI_STAT_CHG)) {
1170 /* other psi fault */
1171
1172 printk(KERN_WARNING "Voyager PSI status 0x%x\n", data);
1173 /* clear the PSI fault */
1174 outb(VOYAGER_CAT_RUN, CAT_CMD);
1175 cat_write(&psi, &psi_asic, VOYAGER_PSI_STATUS_REG, 0);
1176 outb(VOYAGER_CAT_END, CAT_CMD);
1177 }
1178}
diff --git a/arch/i386/mach-voyager/voyager_smp.c b/arch/i386/mach-voyager/voyager_smp.c
new file mode 100644
index 000000000000..903d739ca74a
--- /dev/null
+++ b/arch/i386/mach-voyager/voyager_smp.c
@@ -0,0 +1,1931 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_smp.c
8 *
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
11 */
12#include <linux/config.h>
13#include <linux/mm.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/mc146818rtc.h>
17#include <linux/cache.h>
18#include <linux/interrupt.h>
19#include <linux/smp_lock.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/bootmem.h>
23#include <linux/completion.h>
24#include <asm/desc.h>
25#include <asm/voyager.h>
26#include <asm/vic.h>
27#include <asm/mtrr.h>
28#include <asm/pgalloc.h>
29#include <asm/tlbflush.h>
30#include <asm/arch_hooks.h>
31
32#include <linux/irq.h>
33
34/* TLB state -- visible externally, indexed physically */
35DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
36
37/* CPU IRQ affinity -- set to all ones initially */
38static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
39
40/* per CPU data structure (for /proc/cpuinfo et al), visible externally
41 * indexed physically */
42struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
43
44/* physical ID of the CPU used to boot the system */
45unsigned char boot_cpu_id;
46
47/* The memory line addresses for the Quad CPIs */
48struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49
50/* The masks for the Extended VIC processors, filled in by cat_init */
51__u32 voyager_extended_vic_processors = 0;
52
53/* Masks for the extended Quad processors which cannot be VIC booted */
54__u32 voyager_allowed_boot_processors = 0;
55
56/* The mask for the Quad Processors (both extended and non-extended) */
57__u32 voyager_quad_processors = 0;
58
59/* Total count of live CPUs, used in process.c to display
60 * the CPU information and in irq.c for the per CPU irq
61 * activity count. Finally exported by i386_ksyms.c */
62static int voyager_extended_cpus = 1;
63
64/* Have we found an SMP box - used by time.c to do the profiling
65 interrupt for timeslicing; do not set to 1 until the per CPU timer
66 interrupt is active */
67int smp_found_config = 0;
68
69/* Used for the invalidate map that's also checked in the spinlock */
70static volatile unsigned long smp_invalidate_needed;
71
72/* Bitmask of currently online CPUs - used by setup.c for
73 /proc/cpuinfo, visible externally but still physical */
74cpumask_t cpu_online_map = CPU_MASK_NONE;
75
76/* Bitmask of CPUs present in the system - exported by i386_syms.c, used
77 * by scheduler but indexed physically */
78cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
79
80
81/* The internal functions */
82static void send_CPI(__u32 cpuset, __u8 cpi);
83static void ack_CPI(__u8 cpi);
84static int ack_QIC_CPI(__u8 cpi);
85static void ack_special_QIC_CPI(__u8 cpi);
86static void ack_VIC_CPI(__u8 cpi);
87static void send_CPI_allbutself(__u8 cpi);
88static void enable_vic_irq(unsigned int irq);
89static void disable_vic_irq(unsigned int irq);
90static unsigned int startup_vic_irq(unsigned int irq);
91static void enable_local_vic_irq(unsigned int irq);
92static void disable_local_vic_irq(unsigned int irq);
93static void before_handle_vic_irq(unsigned int irq);
94static void after_handle_vic_irq(unsigned int irq);
95static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
96static void ack_vic_irq(unsigned int irq);
97static void vic_enable_cpi(void);
98static void do_boot_cpu(__u8 cpuid);
99static void do_quad_bootstrap(void);
100static inline void wrapper_smp_local_timer_interrupt(struct pt_regs *);
101
102int hard_smp_processor_id(void);
103
104/* Inline functions */
105static inline void
106send_one_QIC_CPI(__u8 cpu, __u8 cpi)
107{
108 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
109 (smp_processor_id() << 16) + cpi;
110}
111
112static inline void
113send_QIC_CPI(__u32 cpuset, __u8 cpi)
114{
115 int cpu;
116
117 for_each_online_cpu(cpu) {
118 if(cpuset & (1<<cpu)) {
119#ifdef VOYAGER_DEBUG
120 if(!cpu_isset(cpu, cpu_online_map))
121 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
122#endif
123 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
124 }
125 }
126}
127
128static inline void
129send_one_CPI(__u8 cpu, __u8 cpi)
130{
131 if(voyager_quad_processors & (1<<cpu))
132 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
133 else
134 send_CPI(1<<cpu, cpi);
135}
136
137static inline void
138send_CPI_allbutself(__u8 cpi)
139{
140 __u8 cpu = smp_processor_id();
141 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
142 send_CPI(mask, cpi);
143}
144
145static inline int
146is_cpu_quad(void)
147{
148 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
149 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
150}
151
152static inline int
153is_cpu_extended(void)
154{
155 __u8 cpu = hard_smp_processor_id();
156
157 return(voyager_extended_vic_processors & (1<<cpu));
158}
159
160static inline int
161is_cpu_vic_boot(void)
162{
163 __u8 cpu = hard_smp_processor_id();
164
165 return(voyager_extended_vic_processors
166 & voyager_allowed_boot_processors & (1<<cpu));
167}
168
169
170static inline void
171ack_CPI(__u8 cpi)
172{
173 switch(cpi) {
174 case VIC_CPU_BOOT_CPI:
175 if(is_cpu_quad() && !is_cpu_vic_boot())
176 ack_QIC_CPI(cpi);
177 else
178 ack_VIC_CPI(cpi);
179 break;
180 case VIC_SYS_INT:
181 case VIC_CMN_INT:
182 /* These are slightly strange. Even on the Quad card,
183 * They are vectored as VIC CPIs */
184 if(is_cpu_quad())
185 ack_special_QIC_CPI(cpi);
186 else
187 ack_VIC_CPI(cpi);
188 break;
189 default:
190 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
191 break;
192 }
193}
194
195/* local variables */
196
197/* The VIC IRQ descriptors -- these look almost identical to the
198 * 8259 IRQs except that masks and things must be kept per processor
199 */
200static struct hw_interrupt_type vic_irq_type = {
201 .typename = "VIC-level",
202 .startup = startup_vic_irq,
203 .shutdown = disable_vic_irq,
204 .enable = enable_vic_irq,
205 .disable = disable_vic_irq,
206 .ack = before_handle_vic_irq,
207 .end = after_handle_vic_irq,
208 .set_affinity = set_vic_irq_affinity,
209};
210
211/* used to count up as CPUs are brought on line (starts at 0) */
212static int cpucount = 0;
213
214/* steal a page from the bottom of memory for the trampoline and
215 * squirrel its address away here. This will be in kernel virtual
216 * space */
217static __u32 trampoline_base;
218
219/* The per cpu profile stuff - used in smp_local_timer_interrupt */
220static DEFINE_PER_CPU(int, prof_multiplier) = 1;
221static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
222static DEFINE_PER_CPU(int, prof_counter) = 1;
223
224/* the map used to check if a CPU has booted */
225static __u32 cpu_booted_map;
226
227/* the synchronize flag used to hold all secondary CPUs spinning in
228 * a tight loop until the boot sequence is ready for them */
229static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
230
231/* This is for the new dynamic CPU boot code */
232cpumask_t cpu_callin_map = CPU_MASK_NONE;
233cpumask_t cpu_callout_map = CPU_MASK_NONE;
234
235/* The per processor IRQ masks (these are usually kept in sync) */
236static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
237
238/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
239static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
240
241/* Lock for enable/disable of VIC interrupts */
242static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
243
244/* The boot processor is correctly set up in PC mode when it
245 * comes up, but the secondaries need their master/slave 8259
246 * pairs initializing correctly */
247
248/* Interrupt counters (per cpu) and total - used to try to
249 * even up the interrupt handling routines */
250static long vic_intr_total = 0;
251static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
252static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
253
254/* Since we can only use CPI0, we fake all the other CPIs */
255static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
256
257/* debugging routine to read the isr of the cpu's pic */
258static inline __u16
259vic_read_isr(void)
260{
261 __u16 isr;
262
263 outb(0x0b, 0xa0);
264 isr = inb(0xa0) << 8;
265 outb(0x0b, 0x20);
266 isr |= inb(0x20);
267
268 return isr;
269}
270
271static __init void
272qic_setup(void)
273{
274 if(!is_cpu_quad()) {
275 /* not a quad, no setup */
276 return;
277 }
278 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
279 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
280
281 if(is_cpu_extended()) {
282 /* the QIC duplicate of the VIC base register */
283 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
284 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
285
286 /* FIXME: should set up the QIC timer and memory parity
287 * error vectors here */
288 }
289}
290
291static __init void
292vic_setup_pic(void)
293{
294 outb(1, VIC_REDIRECT_REGISTER_1);
295 /* clear the claim registers for dynamic routing */
296 outb(0, VIC_CLAIM_REGISTER_0);
297 outb(0, VIC_CLAIM_REGISTER_1);
298
299 outb(0, VIC_PRIORITY_REGISTER);
300 /* Set the Primary and Secondary Microchannel vector
301 * bases to be the same as the ordinary interrupts
302 *
303 * FIXME: This would be more efficient using separate
304 * vectors. */
305 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
306 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
307 /* Now initiallise the master PIC belonging to this CPU by
308 * sending the four ICWs */
309
310 /* ICW1: level triggered, ICW4 needed */
311 outb(0x19, 0x20);
312
313 /* ICW2: vector base */
314 outb(FIRST_EXTERNAL_VECTOR, 0x21);
315
316 /* ICW3: slave at line 2 */
317 outb(0x04, 0x21);
318
319 /* ICW4: 8086 mode */
320 outb(0x01, 0x21);
321
322 /* now the same for the slave PIC */
323
324 /* ICW1: level trigger, ICW4 needed */
325 outb(0x19, 0xA0);
326
327 /* ICW2: slave vector base */
328 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
329
330 /* ICW3: slave ID */
331 outb(0x02, 0xA1);
332
333 /* ICW4: 8086 mode */
334 outb(0x01, 0xA1);
335}
336
337static void
338do_quad_bootstrap(void)
339{
340 if(is_cpu_quad() && is_cpu_vic_boot()) {
341 int i;
342 unsigned long flags;
343 __u8 cpuid = hard_smp_processor_id();
344
345 local_irq_save(flags);
346
347 for(i = 0; i<4; i++) {
348 /* FIXME: this would be >>3 &0x7 on the 32 way */
349 if(((cpuid >> 2) & 0x03) == i)
350 /* don't lower our own mask! */
351 continue;
352
353 /* masquerade as local Quad CPU */
354 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
355 /* enable the startup CPI */
356 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
357 /* restore cpu id */
358 outb(0, QIC_PROCESSOR_ID);
359 }
360 local_irq_restore(flags);
361 }
362}
363
364
365/* Set up all the basic stuff: read the SMP config and make all the
366 * SMP information reflect only the boot cpu. All others will be
367 * brought on-line later. */
368void __init
369find_smp_config(void)
370{
371 int i;
372
373 boot_cpu_id = hard_smp_processor_id();
374
375 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
376
377 /* initialize the CPU structures (moved from smp_boot_cpus) */
378 for(i=0; i<NR_CPUS; i++) {
379 cpu_irq_affinity[i] = ~0;
380 }
381 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
382
383 /* The boot CPU must be extended */
384 voyager_extended_vic_processors = 1<<boot_cpu_id;
385 /* initially, all of the first 8 cpu's can boot */
386 voyager_allowed_boot_processors = 0xff;
387 /* set up everything for just this CPU, we can alter
388 * this as we start the other CPUs later */
389 /* now get the CPU disposition from the extended CMOS */
390 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
391 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
392 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
393 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
394 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
395 /* Here we set up the VIC to enable SMP */
396 /* enable the CPIs by writing the base vector to their register */
397 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
398 outb(1, VIC_REDIRECT_REGISTER_1);
399 /* set the claim registers for static routing --- Boot CPU gets
400 * all interrupts untill all other CPUs started */
401 outb(0xff, VIC_CLAIM_REGISTER_0);
402 outb(0xff, VIC_CLAIM_REGISTER_1);
403 /* Set the Primary and Secondary Microchannel vector
404 * bases to be the same as the ordinary interrupts
405 *
406 * FIXME: This would be more efficient using separate
407 * vectors. */
408 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
409 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
410
411 /* Finally tell the firmware that we're driving */
412 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
413 VOYAGER_SUS_IN_CONTROL_PORT);
414
415 current_thread_info()->cpu = boot_cpu_id;
416}
417
418/*
419 * The bootstrap kernel entry code has set these up. Save them
420 * for a given CPU, id is physical */
421void __init
422smp_store_cpu_info(int id)
423{
424 struct cpuinfo_x86 *c=&cpu_data[id];
425
426 *c = boot_cpu_data;
427
428 identify_cpu(c);
429}
430
431/* set up the trampoline and return the physical address of the code */
432static __u32 __init
433setup_trampoline(void)
434{
435 /* these two are global symbols in trampoline.S */
436 extern __u8 trampoline_end[];
437 extern __u8 trampoline_data[];
438
439 memcpy((__u8 *)trampoline_base, trampoline_data,
440 trampoline_end - trampoline_data);
441 return virt_to_phys((__u8 *)trampoline_base);
442}
443
444/* Routine initially called when a non-boot CPU is brought online */
445static void __init
446start_secondary(void *unused)
447{
448 __u8 cpuid = hard_smp_processor_id();
449 /* external functions not defined in the headers */
450 extern void calibrate_delay(void);
451
452 cpu_init();
453
454 /* OK, we're in the routine */
455 ack_CPI(VIC_CPU_BOOT_CPI);
456
457 /* setup the 8259 master slave pair belonging to this CPU ---
458 * we won't actually receive any until the boot CPU
459 * relinquishes it's static routing mask */
460 vic_setup_pic();
461
462 qic_setup();
463
464 if(is_cpu_quad() && !is_cpu_vic_boot()) {
465 /* clear the boot CPI */
466 __u8 dummy;
467
468 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
469 printk("read dummy %d\n", dummy);
470 }
471
472 /* lower the mask to receive CPIs */
473 vic_enable_cpi();
474
475 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
476
477 /* enable interrupts */
478 local_irq_enable();
479
480 /* get our bogomips */
481 calibrate_delay();
482
483 /* save our processor parameters */
484 smp_store_cpu_info(cpuid);
485
486 /* if we're a quad, we may need to bootstrap other CPUs */
487 do_quad_bootstrap();
488
489 /* FIXME: this is rather a poor hack to prevent the CPU
490 * activating softirqs while it's supposed to be waiting for
491 * permission to proceed. Without this, the new per CPU stuff
492 * in the softirqs will fail */
493 local_irq_disable();
494 cpu_set(cpuid, cpu_callin_map);
495
496 /* signal that we're done */
497 cpu_booted_map = 1;
498
499 while (!cpu_isset(cpuid, smp_commenced_mask))
500 rep_nop();
501 local_irq_enable();
502
503 local_flush_tlb();
504
505 cpu_set(cpuid, cpu_online_map);
506 wmb();
507 cpu_idle();
508}
509
510
511/* Routine to kick start the given CPU and wait for it to report ready
512 * (or timeout in startup). When this routine returns, the requested
513 * CPU is either fully running and configured or known to be dead.
514 *
515 * We call this routine sequentially 1 CPU at a time, so no need for
516 * locking */
517
518static void __init
519do_boot_cpu(__u8 cpu)
520{
521 struct task_struct *idle;
522 int timeout;
523 unsigned long flags;
524 int quad_boot = (1<<cpu) & voyager_quad_processors
525 & ~( voyager_extended_vic_processors
526 & voyager_allowed_boot_processors);
527
528 /* For the 486, we can't use the 4Mb page table trick, so
529 * must map a region of memory */
530#ifdef CONFIG_M486
531 int i;
532 unsigned long *page_table_copies = (unsigned long *)
533 __get_free_page(GFP_KERNEL);
534#endif
535 pgd_t orig_swapper_pg_dir0;
536
537 /* This is an area in head.S which was used to set up the
538 * initial kernel stack. We need to alter this to give the
539 * booting CPU a new stack (taken from its idle process) */
540 extern struct {
541 __u8 *esp;
542 unsigned short ss;
543 } stack_start;
544 /* This is the format of the CPI IDT gate (in real mode) which
545 * we're hijacking to boot the CPU */
546 union IDTFormat {
547 struct seg {
548 __u16 Offset;
549 __u16 Segment;
550 } idt;
551 __u32 val;
552 } hijack_source;
553
554 __u32 *hijack_vector;
555 __u32 start_phys_address = setup_trampoline();
556
557 /* There's a clever trick to this: The linux trampoline is
558 * compiled to begin at absolute location zero, so make the
559 * address zero but have the data segment selector compensate
560 * for the actual address */
561 hijack_source.idt.Offset = start_phys_address & 0x000F;
562 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
563
564 cpucount++;
565 idle = fork_idle(cpu);
566 if(IS_ERR(idle))
567 panic("failed fork for CPU%d", cpu);
568 idle->thread.eip = (unsigned long) start_secondary;
569 /* init_tasks (in sched.c) is indexed logically */
570 stack_start.esp = (void *) idle->thread.esp;
571
572 irq_ctx_init(cpu);
573
574 /* Note: Don't modify initial ss override */
575 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
576 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
577 hijack_source.idt.Offset, stack_start.esp));
578 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
579 * (so that the booting CPU can find start_32 */
580 orig_swapper_pg_dir0 = swapper_pg_dir[0];
581#ifdef CONFIG_M486
582 if(page_table_copies == NULL)
583 panic("No free memory for 486 page tables\n");
584 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
585 page_table_copies[i] = (i * PAGE_SIZE)
586 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
587
588 ((unsigned long *)swapper_pg_dir)[0] =
589 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
590 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
591#else
592 ((unsigned long *)swapper_pg_dir)[0] =
593 (virt_to_phys(pg0) & PAGE_MASK)
594 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
595#endif
596
597 if(quad_boot) {
598 printk("CPU %d: non extended Quad boot\n", cpu);
599 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
600 *hijack_vector = hijack_source.val;
601 } else {
602 printk("CPU%d: extended VIC boot\n", cpu);
603 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
604 *hijack_vector = hijack_source.val;
605 /* VIC errata, may also receive interrupt at this address */
606 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
607 *hijack_vector = hijack_source.val;
608 }
609 /* All non-boot CPUs start with interrupts fully masked. Need
610 * to lower the mask of the CPI we're about to send. We do
611 * this in the VIC by masquerading as the processor we're
612 * about to boot and lowering its interrupt mask */
613 local_irq_save(flags);
614 if(quad_boot) {
615 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
616 } else {
617 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
618 /* here we're altering registers belonging to `cpu' */
619
620 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
621 /* now go back to our original identity */
622 outb(boot_cpu_id, VIC_PROCESSOR_ID);
623
624 /* and boot the CPU */
625
626 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
627 }
628 cpu_booted_map = 0;
629 local_irq_restore(flags);
630
631 /* now wait for it to become ready (or timeout) */
632 for(timeout = 0; timeout < 50000; timeout++) {
633 if(cpu_booted_map)
634 break;
635 udelay(100);
636 }
637 /* reset the page table */
638 swapper_pg_dir[0] = orig_swapper_pg_dir0;
639 local_flush_tlb();
640#ifdef CONFIG_M486
641 free_page((unsigned long)page_table_copies);
642#endif
643
644 if (cpu_booted_map) {
645 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
646 cpu, smp_processor_id()));
647
648 printk("CPU%d: ", cpu);
649 print_cpu_info(&cpu_data[cpu]);
650 wmb();
651 cpu_set(cpu, cpu_callout_map);
652 }
653 else {
654 printk("CPU%d FAILED TO BOOT: ", cpu);
655 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
656 printk("Stuck.\n");
657 else
658 printk("Not responding.\n");
659
660 cpucount--;
661 }
662}
663
664void __init
665smp_boot_cpus(void)
666{
667 int i;
668
669 /* CAT BUS initialisation must be done after the memory */
670 /* FIXME: The L4 has a catbus too, it just needs to be
671 * accessed in a totally different way */
672 if(voyager_level == 5) {
673 voyager_cat_init();
674
675 /* now that the cat has probed the Voyager System Bus, sanity
676 * check the cpu map */
677 if( ((voyager_quad_processors | voyager_extended_vic_processors)
678 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
679 /* should panic */
680 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
681 }
682 } else if(voyager_level == 4)
683 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
684
685 /* this sets up the idle task to run on the current cpu */
686 voyager_extended_cpus = 1;
687 /* Remove the global_irq_holder setting, it triggers a BUG() on
688 * schedule at the moment */
689 //global_irq_holder = boot_cpu_id;
690
691 /* FIXME: Need to do something about this but currently only works
692 * on CPUs with a tsc which none of mine have.
693 smp_tune_scheduling();
694 */
695 smp_store_cpu_info(boot_cpu_id);
696 printk("CPU%d: ", boot_cpu_id);
697 print_cpu_info(&cpu_data[boot_cpu_id]);
698
699 if(is_cpu_quad()) {
700 /* booting on a Quad CPU */
701 printk("VOYAGER SMP: Boot CPU is Quad\n");
702 qic_setup();
703 do_quad_bootstrap();
704 }
705
706 /* enable our own CPIs */
707 vic_enable_cpi();
708
709 cpu_set(boot_cpu_id, cpu_online_map);
710 cpu_set(boot_cpu_id, cpu_callout_map);
711
712 /* loop over all the extended VIC CPUs and boot them. The
713 * Quad CPUs must be bootstrapped by their extended VIC cpu */
714 for(i = 0; i < NR_CPUS; i++) {
715 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
716 continue;
717 do_boot_cpu(i);
718 /* This udelay seems to be needed for the Quad boots
719 * don't remove unless you know what you're doing */
720 udelay(1000);
721 }
722 /* we could compute the total bogomips here, but why bother?,
723 * Code added from smpboot.c */
724 {
725 unsigned long bogosum = 0;
726 for (i = 0; i < NR_CPUS; i++)
727 if (cpu_isset(i, cpu_online_map))
728 bogosum += cpu_data[i].loops_per_jiffy;
729 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
730 cpucount+1,
731 bogosum/(500000/HZ),
732 (bogosum/(5000/HZ))%100);
733 }
734 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
735 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
736 /* that's it, switch to symmetric mode */
737 outb(0, VIC_PRIORITY_REGISTER);
738 outb(0, VIC_CLAIM_REGISTER_0);
739 outb(0, VIC_CLAIM_REGISTER_1);
740
741 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
742}
743
744/* Reload the secondary CPUs task structure (this function does not
745 * return ) */
746void __init
747initialize_secondary(void)
748{
749#if 0
750 // AC kernels only
751 set_current(hard_get_current());
752#endif
753
754 /*
755 * We don't actually need to load the full TSS,
756 * basically just the stack pointer and the eip.
757 */
758
759 asm volatile(
760 "movl %0,%%esp\n\t"
761 "jmp *%1"
762 :
763 :"r" (current->thread.esp),"r" (current->thread.eip));
764}
765
766/* handle a Voyager SYS_INT -- If we don't, the base board will
767 * panic the system.
768 *
769 * System interrupts occur because some problem was detected on the
770 * various busses. To find out what you have to probe all the
771 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
772fastcall void
773smp_vic_sys_interrupt(struct pt_regs *regs)
774{
775 ack_CPI(VIC_SYS_INT);
776 printk("Voyager SYSTEM INTERRUPT\n");
777}
778
779/* Handle a voyager CMN_INT; These interrupts occur either because of
780 * a system status change or because a single bit memory error
781 * occurred. FIXME: At the moment, ignore all this. */
782fastcall void
783smp_vic_cmn_interrupt(struct pt_regs *regs)
784{
785 static __u8 in_cmn_int = 0;
786 static DEFINE_SPINLOCK(cmn_int_lock);
787
788 /* common ints are broadcast, so make sure we only do this once */
789 _raw_spin_lock(&cmn_int_lock);
790 if(in_cmn_int)
791 goto unlock_end;
792
793 in_cmn_int++;
794 _raw_spin_unlock(&cmn_int_lock);
795
796 VDEBUG(("Voyager COMMON INTERRUPT\n"));
797
798 if(voyager_level == 5)
799 voyager_cat_do_common_interrupt();
800
801 _raw_spin_lock(&cmn_int_lock);
802 in_cmn_int = 0;
803 unlock_end:
804 _raw_spin_unlock(&cmn_int_lock);
805 ack_CPI(VIC_CMN_INT);
806}
807
808/*
809 * Reschedule call back. Nothing to do, all the work is done
810 * automatically when we return from the interrupt. */
811static void
812smp_reschedule_interrupt(void)
813{
814 /* do nothing */
815}
816
817static struct mm_struct * flush_mm;
818static unsigned long flush_va;
819static DEFINE_SPINLOCK(tlbstate_lock);
820#define FLUSH_ALL 0xffffffff
821
822/*
823 * We cannot call mmdrop() because we are in interrupt context,
824 * instead update mm->cpu_vm_mask.
825 *
826 * We need to reload %cr3 since the page tables may be going
827 * away from under us..
828 */
829static inline void
830leave_mm (unsigned long cpu)
831{
832 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
833 BUG();
834 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
835 load_cr3(swapper_pg_dir);
836}
837
838
839/*
840 * Invalidate call-back
841 */
842static void
843smp_invalidate_interrupt(void)
844{
845 __u8 cpu = smp_processor_id();
846
847 if (!test_bit(cpu, &smp_invalidate_needed))
848 return;
849 /* This will flood messages. Don't uncomment unless you see
850 * Problems with cross cpu invalidation
851 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
852 smp_processor_id()));
853 */
854
855 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
856 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
857 if (flush_va == FLUSH_ALL)
858 local_flush_tlb();
859 else
860 __flush_tlb_one(flush_va);
861 } else
862 leave_mm(cpu);
863 }
864 smp_mb__before_clear_bit();
865 clear_bit(cpu, &smp_invalidate_needed);
866 smp_mb__after_clear_bit();
867}
868
869/* All the new flush operations for 2.4 */
870
871
872/* This routine is called with a physical cpu mask */
873static void
874flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
875 unsigned long va)
876{
877 int stuck = 50000;
878
879 if (!cpumask)
880 BUG();
881 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
882 BUG();
883 if (cpumask & (1 << smp_processor_id()))
884 BUG();
885 if (!mm)
886 BUG();
887
888 spin_lock(&tlbstate_lock);
889
890 flush_mm = mm;
891 flush_va = va;
892 atomic_set_mask(cpumask, &smp_invalidate_needed);
893 /*
894 * We have to send the CPI only to
895 * CPUs affected.
896 */
897 send_CPI(cpumask, VIC_INVALIDATE_CPI);
898
899 while (smp_invalidate_needed) {
900 mb();
901 if(--stuck == 0) {
902 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
903 break;
904 }
905 }
906
907 /* Uncomment only to debug invalidation problems
908 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
909 */
910
911 flush_mm = NULL;
912 flush_va = 0;
913 spin_unlock(&tlbstate_lock);
914}
915
916void
917flush_tlb_current_task(void)
918{
919 struct mm_struct *mm = current->mm;
920 unsigned long cpu_mask;
921
922 preempt_disable();
923
924 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
925 local_flush_tlb();
926 if (cpu_mask)
927 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
928
929 preempt_enable();
930}
931
932
933void
934flush_tlb_mm (struct mm_struct * mm)
935{
936 unsigned long cpu_mask;
937
938 preempt_disable();
939
940 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
941
942 if (current->active_mm == mm) {
943 if (current->mm)
944 local_flush_tlb();
945 else
946 leave_mm(smp_processor_id());
947 }
948 if (cpu_mask)
949 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
950
951 preempt_enable();
952}
953
954void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
955{
956 struct mm_struct *mm = vma->vm_mm;
957 unsigned long cpu_mask;
958
959 preempt_disable();
960
961 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
962 if (current->active_mm == mm) {
963 if(current->mm)
964 __flush_tlb_one(va);
965 else
966 leave_mm(smp_processor_id());
967 }
968
969 if (cpu_mask)
970 flush_tlb_others(cpu_mask, mm, va);
971
972 preempt_enable();
973}
974
975/* enable the requested IRQs */
976static void
977smp_enable_irq_interrupt(void)
978{
979 __u8 irq;
980 __u8 cpu = get_cpu();
981
982 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
983 vic_irq_enable_mask[cpu]));
984
985 spin_lock(&vic_irq_lock);
986 for(irq = 0; irq < 16; irq++) {
987 if(vic_irq_enable_mask[cpu] & (1<<irq))
988 enable_local_vic_irq(irq);
989 }
990 vic_irq_enable_mask[cpu] = 0;
991 spin_unlock(&vic_irq_lock);
992
993 put_cpu_no_resched();
994}
995
996/*
997 * CPU halt call-back
998 */
999static void
1000smp_stop_cpu_function(void *dummy)
1001{
1002 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1003 cpu_clear(smp_processor_id(), cpu_online_map);
1004 local_irq_disable();
1005 for(;;)
1006 __asm__("hlt");
1007}
1008
1009static DEFINE_SPINLOCK(call_lock);
1010
1011struct call_data_struct {
1012 void (*func) (void *info);
1013 void *info;
1014 volatile unsigned long started;
1015 volatile unsigned long finished;
1016 int wait;
1017};
1018
1019static struct call_data_struct * call_data;
1020
1021/* execute a thread on a new CPU. The function to be called must be
1022 * previously set up. This is used to schedule a function for
1023 * execution on all CPU's - set up the function then broadcast a
1024 * function_interrupt CPI to come here on each CPU */
1025static void
1026smp_call_function_interrupt(void)
1027{
1028 void (*func) (void *info) = call_data->func;
1029 void *info = call_data->info;
1030 /* must take copy of wait because call_data may be replaced
1031 * unless the function is waiting for us to finish */
1032 int wait = call_data->wait;
1033 __u8 cpu = smp_processor_id();
1034
1035 /*
1036 * Notify initiating CPU that I've grabbed the data and am
1037 * about to execute the function
1038 */
1039 mb();
1040 if(!test_and_clear_bit(cpu, &call_data->started)) {
1041 /* If the bit wasn't set, this could be a replay */
1042 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1043 return;
1044 }
1045 /*
1046 * At this point the info structure may be out of scope unless wait==1
1047 */
1048 irq_enter();
1049 (*func)(info);
1050 irq_exit();
1051 if (wait) {
1052 mb();
1053 clear_bit(cpu, &call_data->finished);
1054 }
1055}
1056
1057/* Call this function on all CPUs using the function_interrupt above
1058 <func> The function to run. This must be fast and non-blocking.
1059 <info> An arbitrary pointer to pass to the function.
1060 <retry> If true, keep retrying until ready.
1061 <wait> If true, wait until function has completed on other CPUs.
1062 [RETURNS] 0 on success, else a negative status code. Does not return until
1063 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1064*/
1065int
1066smp_call_function (void (*func) (void *info), void *info, int retry,
1067 int wait)
1068{
1069 struct call_data_struct data;
1070 __u32 mask = cpus_addr(cpu_online_map)[0];
1071
1072 mask &= ~(1<<smp_processor_id());
1073
1074 if (!mask)
1075 return 0;
1076
1077 /* Can deadlock when called with interrupts disabled */
1078 WARN_ON(irqs_disabled());
1079
1080 data.func = func;
1081 data.info = info;
1082 data.started = mask;
1083 data.wait = wait;
1084 if (wait)
1085 data.finished = mask;
1086
1087 spin_lock(&call_lock);
1088 call_data = &data;
1089 wmb();
1090 /* Send a message to all other CPUs and wait for them to respond */
1091 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI);
1092
1093 /* Wait for response */
1094 while (data.started)
1095 barrier();
1096
1097 if (wait)
1098 while (data.finished)
1099 barrier();
1100
1101 spin_unlock(&call_lock);
1102
1103 return 0;
1104}
1105
1106/* Sorry about the name. In an APIC based system, the APICs
1107 * themselves are programmed to send a timer interrupt. This is used
1108 * by linux to reschedule the processor. Voyager doesn't have this,
1109 * so we use the system clock to interrupt one processor, which in
1110 * turn, broadcasts a timer CPI to all the others --- we receive that
1111 * CPI here. We don't use this actually for counting so losing
1112 * ticks doesn't matter
1113 *
1114 * FIXME: For those CPU's which actually have a local APIC, we could
1115 * try to use it to trigger this interrupt instead of having to
1116 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1117 * no local APIC, so I can't do this
1118 *
1119 * This function is currently a placeholder and is unused in the code */
1120fastcall void
1121smp_apic_timer_interrupt(struct pt_regs *regs)
1122{
1123 wrapper_smp_local_timer_interrupt(regs);
1124}
1125
1126/* All of the QUAD interrupt GATES */
1127fastcall void
1128smp_qic_timer_interrupt(struct pt_regs *regs)
1129{
1130 ack_QIC_CPI(QIC_TIMER_CPI);
1131 wrapper_smp_local_timer_interrupt(regs);
1132}
1133
1134fastcall void
1135smp_qic_invalidate_interrupt(struct pt_regs *regs)
1136{
1137 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1138 smp_invalidate_interrupt();
1139}
1140
1141fastcall void
1142smp_qic_reschedule_interrupt(struct pt_regs *regs)
1143{
1144 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1145 smp_reschedule_interrupt();
1146}
1147
1148fastcall void
1149smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1150{
1151 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1152 smp_enable_irq_interrupt();
1153}
1154
1155fastcall void
1156smp_qic_call_function_interrupt(struct pt_regs *regs)
1157{
1158 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1159 smp_call_function_interrupt();
1160}
1161
1162fastcall void
1163smp_vic_cpi_interrupt(struct pt_regs *regs)
1164{
1165 __u8 cpu = smp_processor_id();
1166
1167 if(is_cpu_quad())
1168 ack_QIC_CPI(VIC_CPI_LEVEL0);
1169 else
1170 ack_VIC_CPI(VIC_CPI_LEVEL0);
1171
1172 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
1173 wrapper_smp_local_timer_interrupt(regs);
1174 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1175 smp_invalidate_interrupt();
1176 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1177 smp_reschedule_interrupt();
1178 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1179 smp_enable_irq_interrupt();
1180 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1181 smp_call_function_interrupt();
1182}
1183
1184static void
1185do_flush_tlb_all(void* info)
1186{
1187 unsigned long cpu = smp_processor_id();
1188
1189 __flush_tlb_all();
1190 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1191 leave_mm(cpu);
1192}
1193
1194
1195/* flush the TLB of every active CPU in the system */
1196void
1197flush_tlb_all(void)
1198{
1199 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1200}
1201
1202/* used to set up the trampoline for other CPUs when the memory manager
1203 * is sorted out */
1204void __init
1205smp_alloc_memory(void)
1206{
1207 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1208 if(__pa(trampoline_base) >= 0x93000)
1209 BUG();
1210}
1211
1212/* send a reschedule CPI to one CPU by physical CPU number*/
1213void
1214smp_send_reschedule(int cpu)
1215{
1216 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1217}
1218
1219
1220int
1221hard_smp_processor_id(void)
1222{
1223 __u8 i;
1224 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1225 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1226 return cpumask & 0x1F;
1227
1228 for(i = 0; i < 8; i++) {
1229 if(cpumask & (1<<i))
1230 return i;
1231 }
1232 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1233 return 0;
1234}
1235
1236/* broadcast a halt to all other CPUs */
1237void
1238smp_send_stop(void)
1239{
1240 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1241}
1242
1243/* this function is triggered in time.c when a clock tick fires
1244 * we need to re-broadcast the tick to all CPUs */
1245void
1246smp_vic_timer_interrupt(struct pt_regs *regs)
1247{
1248 send_CPI_allbutself(VIC_TIMER_CPI);
1249 smp_local_timer_interrupt(regs);
1250}
1251
1252static inline void
1253wrapper_smp_local_timer_interrupt(struct pt_regs *regs)
1254{
1255 irq_enter();
1256 smp_local_timer_interrupt(regs);
1257 irq_exit();
1258}
1259
1260/* local (per CPU) timer interrupt. It does both profiling and
1261 * process statistics/rescheduling.
1262 *
1263 * We do profiling in every local tick, statistics/rescheduling
1264 * happen only every 'profiling multiplier' ticks. The default
1265 * multiplier is 1 and it can be changed by writing the new multiplier
1266 * value into /proc/profile.
1267 */
1268void
1269smp_local_timer_interrupt(struct pt_regs * regs)
1270{
1271 int cpu = smp_processor_id();
1272 long weight;
1273
1274 profile_tick(CPU_PROFILING, regs);
1275 if (--per_cpu(prof_counter, cpu) <= 0) {
1276 /*
1277 * The multiplier may have changed since the last time we got
1278 * to this point as a result of the user writing to
1279 * /proc/profile. In this case we need to adjust the APIC
1280 * timer accordingly.
1281 *
1282 * Interrupts are already masked off at this point.
1283 */
1284 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1285 if (per_cpu(prof_counter, cpu) !=
1286 per_cpu(prof_old_multiplier, cpu)) {
1287 /* FIXME: need to update the vic timer tick here */
1288 per_cpu(prof_old_multiplier, cpu) =
1289 per_cpu(prof_counter, cpu);
1290 }
1291
1292 update_process_times(user_mode(regs));
1293 }
1294
1295 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1296 /* only extended VIC processors participate in
1297 * interrupt distribution */
1298 return;
1299
1300 /*
1301 * We take the 'long' return path, and there every subsystem
1302 * grabs the apropriate locks (kernel lock/ irq lock).
1303 *
1304 * we might want to decouple profiling from the 'long path',
1305 * and do the profiling totally in assembly.
1306 *
1307 * Currently this isn't too much of an issue (performance wise),
1308 * we can take more than 100K local irqs per second on a 100 MHz P5.
1309 */
1310
1311 if((++vic_tick[cpu] & 0x7) != 0)
1312 return;
1313 /* get here every 16 ticks (about every 1/6 of a second) */
1314
1315 /* Change our priority to give someone else a chance at getting
1316 * the IRQ. The algorithm goes like this:
1317 *
1318 * In the VIC, the dynamically routed interrupt is always
1319 * handled by the lowest priority eligible (i.e. receiving
1320 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1321 * lowest processor number gets it.
1322 *
1323 * The priority of a CPU is controlled by a special per-CPU
1324 * VIC priority register which is 3 bits wide 0 being lowest
1325 * and 7 highest priority..
1326 *
1327 * Therefore we subtract the average number of interrupts from
1328 * the number we've fielded. If this number is negative, we
1329 * lower the activity count and if it is positive, we raise
1330 * it.
1331 *
1332 * I'm afraid this still leads to odd looking interrupt counts:
1333 * the totals are all roughly equal, but the individual ones
1334 * look rather skewed.
1335 *
1336 * FIXME: This algorithm is total crap when mixed with SMP
1337 * affinity code since we now try to even up the interrupt
1338 * counts when an affinity binding is keeping them on a
1339 * particular CPU*/
1340 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1341 - vic_intr_total) >> 4;
1342 weight += 4;
1343 if(weight > 7)
1344 weight = 7;
1345 if(weight < 0)
1346 weight = 0;
1347
1348 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1349
1350#ifdef VOYAGER_DEBUG
1351 if((vic_tick[cpu] & 0xFFF) == 0) {
1352 /* print this message roughly every 25 secs */
1353 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1354 cpu, vic_tick[cpu], weight);
1355 }
1356#endif
1357}
1358
1359/* setup the profiling timer */
1360int
1361setup_profiling_timer(unsigned int multiplier)
1362{
1363 int i;
1364
1365 if ( (!multiplier))
1366 return -EINVAL;
1367
1368 /*
1369 * Set the new multiplier for each CPU. CPUs don't start using the
1370 * new values until the next timer interrupt in which they do process
1371 * accounting.
1372 */
1373 for (i = 0; i < NR_CPUS; ++i)
1374 per_cpu(prof_multiplier, i) = multiplier;
1375
1376 return 0;
1377}
1378
1379
1380/* The CPIs are handled in the per cpu 8259s, so they must be
1381 * enabled to be received: FIX: enabling the CPIs in the early
1382 * boot sequence interferes with bug checking; enable them later
1383 * on in smp_init */
1384#define VIC_SET_GATE(cpi, vector) \
1385 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1386#define QIC_SET_GATE(cpi, vector) \
1387 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1388
1389void __init
1390smp_intr_init(void)
1391{
1392 int i;
1393
1394 /* initialize the per cpu irq mask to all disabled */
1395 for(i = 0; i < NR_CPUS; i++)
1396 vic_irq_mask[i] = 0xFFFF;
1397
1398 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1399
1400 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1401 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1402
1403 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1404 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1405 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1406 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1407 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1408
1409
1410 /* now put the VIC descriptor into the first 48 IRQs
1411 *
1412 * This is for later: first 16 correspond to PC IRQs; next 16
1413 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1414 for(i = 0; i < 48; i++)
1415 irq_desc[i].handler = &vic_irq_type;
1416}
1417
1418/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1419 * processor to receive CPI */
1420static void
1421send_CPI(__u32 cpuset, __u8 cpi)
1422{
1423 int cpu;
1424 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1425
1426 if(cpi < VIC_START_FAKE_CPI) {
1427 /* fake CPI are only used for booting, so send to the
1428 * extended quads as well---Quads must be VIC booted */
1429 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1430 return;
1431 }
1432 if(quad_cpuset)
1433 send_QIC_CPI(quad_cpuset, cpi);
1434 cpuset &= ~quad_cpuset;
1435 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1436 if(cpuset == 0)
1437 return;
1438 for_each_online_cpu(cpu) {
1439 if(cpuset & (1<<cpu))
1440 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1441 }
1442 if(cpuset)
1443 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1444}
1445
1446/* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1447 * set the cache line to shared by reading it.
1448 *
1449 * DON'T make this inline otherwise the cache line read will be
1450 * optimised away
1451 * */
1452static int
1453ack_QIC_CPI(__u8 cpi) {
1454 __u8 cpu = hard_smp_processor_id();
1455
1456 cpi &= 7;
1457
1458 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1459 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1460}
1461
1462static void
1463ack_special_QIC_CPI(__u8 cpi)
1464{
1465 switch(cpi) {
1466 case VIC_CMN_INT:
1467 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1468 break;
1469 case VIC_SYS_INT:
1470 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1471 break;
1472 }
1473 /* also clear at the VIC, just in case (nop for non-extended proc) */
1474 ack_VIC_CPI(cpi);
1475}
1476
1477/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1478static void
1479ack_VIC_CPI(__u8 cpi)
1480{
1481#ifdef VOYAGER_DEBUG
1482 unsigned long flags;
1483 __u16 isr;
1484 __u8 cpu = smp_processor_id();
1485
1486 local_irq_save(flags);
1487 isr = vic_read_isr();
1488 if((isr & (1<<(cpi &7))) == 0) {
1489 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1490 }
1491#endif
1492 /* send specific EOI; the two system interrupts have
1493 * bit 4 set for a separate vector but behave as the
1494 * corresponding 3 bit intr */
1495 outb_p(0x60|(cpi & 7),0x20);
1496
1497#ifdef VOYAGER_DEBUG
1498 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1499 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1500 }
1501 local_irq_restore(flags);
1502#endif
1503}
1504
1505/* cribbed with thanks from irq.c */
1506#define __byte(x,y) (((unsigned char *)&(y))[x])
1507#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1508#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1509
1510static unsigned int
1511startup_vic_irq(unsigned int irq)
1512{
1513 enable_vic_irq(irq);
1514
1515 return 0;
1516}
1517
1518/* The enable and disable routines. This is where we run into
1519 * conflicting architectural philosophy. Fundamentally, the voyager
1520 * architecture does not expect to have to disable interrupts globally
1521 * (the IRQ controllers belong to each CPU). The processor masquerade
1522 * which is used to start the system shouldn't be used in a running OS
1523 * since it will cause great confusion if two separate CPUs drive to
1524 * the same IRQ controller (I know, I've tried it).
1525 *
1526 * The solution is a variant on the NCR lazy SPL design:
1527 *
1528 * 1) To disable an interrupt, do nothing (other than set the
1529 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1530 *
1531 * 2) If the interrupt dares to come in, raise the local mask against
1532 * it (this will result in all the CPU masks being raised
1533 * eventually).
1534 *
1535 * 3) To enable the interrupt, lower the mask on the local CPU and
1536 * broadcast an Interrupt enable CPI which causes all other CPUs to
1537 * adjust their masks accordingly. */
1538
1539static void
1540enable_vic_irq(unsigned int irq)
1541{
1542 /* linux doesn't to processor-irq affinity, so enable on
1543 * all CPUs we know about */
1544 int cpu = smp_processor_id(), real_cpu;
1545 __u16 mask = (1<<irq);
1546 __u32 processorList = 0;
1547 unsigned long flags;
1548
1549 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1550 irq, cpu, cpu_irq_affinity[cpu]));
1551 spin_lock_irqsave(&vic_irq_lock, flags);
1552 for_each_online_cpu(real_cpu) {
1553 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1554 continue;
1555 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1556 /* irq has no affinity for this CPU, ignore */
1557 continue;
1558 }
1559 if(real_cpu == cpu) {
1560 enable_local_vic_irq(irq);
1561 }
1562 else if(vic_irq_mask[real_cpu] & mask) {
1563 vic_irq_enable_mask[real_cpu] |= mask;
1564 processorList |= (1<<real_cpu);
1565 }
1566 }
1567 spin_unlock_irqrestore(&vic_irq_lock, flags);
1568 if(processorList)
1569 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1570}
1571
1572static void
1573disable_vic_irq(unsigned int irq)
1574{
1575 /* lazy disable, do nothing */
1576}
1577
1578static void
1579enable_local_vic_irq(unsigned int irq)
1580{
1581 __u8 cpu = smp_processor_id();
1582 __u16 mask = ~(1 << irq);
1583 __u16 old_mask = vic_irq_mask[cpu];
1584
1585 vic_irq_mask[cpu] &= mask;
1586 if(vic_irq_mask[cpu] == old_mask)
1587 return;
1588
1589 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1590 irq, cpu));
1591
1592 if (irq & 8) {
1593 outb_p(cached_A1(cpu),0xA1);
1594 (void)inb_p(0xA1);
1595 }
1596 else {
1597 outb_p(cached_21(cpu),0x21);
1598 (void)inb_p(0x21);
1599 }
1600}
1601
1602static void
1603disable_local_vic_irq(unsigned int irq)
1604{
1605 __u8 cpu = smp_processor_id();
1606 __u16 mask = (1 << irq);
1607 __u16 old_mask = vic_irq_mask[cpu];
1608
1609 if(irq == 7)
1610 return;
1611
1612 vic_irq_mask[cpu] |= mask;
1613 if(old_mask == vic_irq_mask[cpu])
1614 return;
1615
1616 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1617 irq, cpu));
1618
1619 if (irq & 8) {
1620 outb_p(cached_A1(cpu),0xA1);
1621 (void)inb_p(0xA1);
1622 }
1623 else {
1624 outb_p(cached_21(cpu),0x21);
1625 (void)inb_p(0x21);
1626 }
1627}
1628
1629/* The VIC is level triggered, so the ack can only be issued after the
1630 * interrupt completes. However, we do Voyager lazy interrupt
1631 * handling here: It is an extremely expensive operation to mask an
1632 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1633 * this interrupt actually comes in, then we mask and ack here to push
1634 * the interrupt off to another CPU */
1635static void
1636before_handle_vic_irq(unsigned int irq)
1637{
1638 irq_desc_t *desc = irq_desc + irq;
1639 __u8 cpu = smp_processor_id();
1640
1641 _raw_spin_lock(&vic_irq_lock);
1642 vic_intr_total++;
1643 vic_intr_count[cpu]++;
1644
1645 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1646 /* The irq is not in our affinity mask, push it off
1647 * onto another CPU */
1648 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1649 irq, cpu));
1650 disable_local_vic_irq(irq);
1651 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1652 * actually calling the interrupt routine */
1653 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1654 } else if(desc->status & IRQ_DISABLED) {
1655 /* Damn, the interrupt actually arrived, do the lazy
1656 * disable thing. The interrupt routine in irq.c will
1657 * not handle a IRQ_DISABLED interrupt, so nothing more
1658 * need be done here */
1659 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1660 irq, cpu));
1661 disable_local_vic_irq(irq);
1662 desc->status |= IRQ_REPLAY;
1663 } else {
1664 desc->status &= ~IRQ_REPLAY;
1665 }
1666
1667 _raw_spin_unlock(&vic_irq_lock);
1668}
1669
1670/* Finish the VIC interrupt: basically mask */
1671static void
1672after_handle_vic_irq(unsigned int irq)
1673{
1674 irq_desc_t *desc = irq_desc + irq;
1675
1676 _raw_spin_lock(&vic_irq_lock);
1677 {
1678 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1679#ifdef VOYAGER_DEBUG
1680 __u16 isr;
1681#endif
1682
1683 desc->status = status;
1684 if ((status & IRQ_DISABLED))
1685 disable_local_vic_irq(irq);
1686#ifdef VOYAGER_DEBUG
1687 /* DEBUG: before we ack, check what's in progress */
1688 isr = vic_read_isr();
1689 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1690 int i;
1691 __u8 cpu = smp_processor_id();
1692 __u8 real_cpu;
1693 int mask; /* Um... initialize me??? --RR */
1694
1695 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1696 cpu, irq);
1697 for_each_cpu(real_cpu, mask) {
1698
1699 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1700 VIC_PROCESSOR_ID);
1701 isr = vic_read_isr();
1702 if(isr & (1<<irq)) {
1703 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1704 real_cpu, irq);
1705 ack_vic_irq(irq);
1706 }
1707 outb(cpu, VIC_PROCESSOR_ID);
1708 }
1709 }
1710#endif /* VOYAGER_DEBUG */
1711 /* as soon as we ack, the interrupt is eligible for
1712 * receipt by another CPU so everything must be in
1713 * order here */
1714 ack_vic_irq(irq);
1715 if(status & IRQ_REPLAY) {
1716 /* replay is set if we disable the interrupt
1717 * in the before_handle_vic_irq() routine, so
1718 * clear the in progress bit here to allow the
1719 * next CPU to handle this correctly */
1720 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1721 }
1722#ifdef VOYAGER_DEBUG
1723 isr = vic_read_isr();
1724 if((isr & (1<<irq)) != 0)
1725 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1726 irq, isr);
1727#endif /* VOYAGER_DEBUG */
1728 }
1729 _raw_spin_unlock(&vic_irq_lock);
1730
1731 /* All code after this point is out of the main path - the IRQ
1732 * may be intercepted by another CPU if reasserted */
1733}
1734
1735
1736/* Linux processor - interrupt affinity manipulations.
1737 *
1738 * For each processor, we maintain a 32 bit irq affinity mask.
1739 * Initially it is set to all 1's so every processor accepts every
1740 * interrupt. In this call, we change the processor's affinity mask:
1741 *
1742 * Change from enable to disable:
1743 *
1744 * If the interrupt ever comes in to the processor, we will disable it
1745 * and ack it to push it off to another CPU, so just accept the mask here.
1746 *
1747 * Change from disable to enable:
1748 *
1749 * change the mask and then do an interrupt enable CPI to re-enable on
1750 * the selected processors */
1751
1752void
1753set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1754{
1755 /* Only extended processors handle interrupts */
1756 unsigned long real_mask;
1757 unsigned long irq_mask = 1 << irq;
1758 int cpu;
1759
1760 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1761
1762 if(cpus_addr(mask)[0] == 0)
1763 /* can't have no cpu's to accept the interrupt -- extremely
1764 * bad things will happen */
1765 return;
1766
1767 if(irq == 0)
1768 /* can't change the affinity of the timer IRQ. This
1769 * is due to the constraint in the voyager
1770 * architecture that the CPI also comes in on and IRQ
1771 * line and we have chosen IRQ0 for this. If you
1772 * raise the mask on this interrupt, the processor
1773 * will no-longer be able to accept VIC CPIs */
1774 return;
1775
1776 if(irq >= 32)
1777 /* You can only have 32 interrupts in a voyager system
1778 * (and 32 only if you have a secondary microchannel
1779 * bus) */
1780 return;
1781
1782 for_each_online_cpu(cpu) {
1783 unsigned long cpu_mask = 1 << cpu;
1784
1785 if(cpu_mask & real_mask) {
1786 /* enable the interrupt for this cpu */
1787 cpu_irq_affinity[cpu] |= irq_mask;
1788 } else {
1789 /* disable the interrupt for this cpu */
1790 cpu_irq_affinity[cpu] &= ~irq_mask;
1791 }
1792 }
1793 /* this is magic, we now have the correct affinity maps, so
1794 * enable the interrupt. This will send an enable CPI to
1795 * those cpu's who need to enable it in their local masks,
1796 * causing them to correct for the new affinity . If the
1797 * interrupt is currently globally disabled, it will simply be
1798 * disabled again as it comes in (voyager lazy disable). If
1799 * the affinity map is tightened to disable the interrupt on a
1800 * cpu, it will be pushed off when it comes in */
1801 enable_vic_irq(irq);
1802}
1803
1804static void
1805ack_vic_irq(unsigned int irq)
1806{
1807 if (irq & 8) {
1808 outb(0x62,0x20); /* Specific EOI to cascade */
1809 outb(0x60|(irq & 7),0xA0);
1810 } else {
1811 outb(0x60 | (irq & 7),0x20);
1812 }
1813}
1814
1815/* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1816 * but are not vectored by it. This means that the 8259 mask must be
1817 * lowered to receive them */
1818static __init void
1819vic_enable_cpi(void)
1820{
1821 __u8 cpu = smp_processor_id();
1822
1823 /* just take a copy of the current mask (nop for boot cpu) */
1824 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1825
1826 enable_local_vic_irq(VIC_CPI_LEVEL0);
1827 enable_local_vic_irq(VIC_CPI_LEVEL1);
1828 /* for sys int and cmn int */
1829 enable_local_vic_irq(7);
1830
1831 if(is_cpu_quad()) {
1832 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1833 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1834 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1835 cpu, QIC_CPI_ENABLE));
1836 }
1837
1838 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1839 cpu, vic_irq_mask[cpu]));
1840}
1841
1842void
1843voyager_smp_dump()
1844{
1845 int old_cpu = smp_processor_id(), cpu;
1846
1847 /* dump the interrupt masks of each processor */
1848 for_each_online_cpu(cpu) {
1849 __u16 imr, isr, irr;
1850 unsigned long flags;
1851
1852 local_irq_save(flags);
1853 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1854 imr = (inb(0xa1) << 8) | inb(0x21);
1855 outb(0x0a, 0xa0);
1856 irr = inb(0xa0) << 8;
1857 outb(0x0a, 0x20);
1858 irr |= inb(0x20);
1859 outb(0x0b, 0xa0);
1860 isr = inb(0xa0) << 8;
1861 outb(0x0b, 0x20);
1862 isr |= inb(0x20);
1863 outb(old_cpu, VIC_PROCESSOR_ID);
1864 local_irq_restore(flags);
1865 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1866 cpu, vic_irq_mask[cpu], imr, irr, isr);
1867#if 0
1868 /* These lines are put in to try to unstick an un ack'd irq */
1869 if(isr != 0) {
1870 int irq;
1871 for(irq=0; irq<16; irq++) {
1872 if(isr & (1<<irq)) {
1873 printk("\tCPU%d: ack irq %d\n",
1874 cpu, irq);
1875 local_irq_save(flags);
1876 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1877 VIC_PROCESSOR_ID);
1878 ack_vic_irq(irq);
1879 outb(old_cpu, VIC_PROCESSOR_ID);
1880 local_irq_restore(flags);
1881 }
1882 }
1883 }
1884#endif
1885 }
1886}
1887
1888void
1889smp_voyager_power_off(void *dummy)
1890{
1891 if(smp_processor_id() == boot_cpu_id)
1892 voyager_power_off();
1893 else
1894 smp_stop_cpu_function(NULL);
1895}
1896
1897void __init
1898smp_prepare_cpus(unsigned int max_cpus)
1899{
1900 /* FIXME: ignore max_cpus for now */
1901 smp_boot_cpus();
1902}
1903
1904void __devinit smp_prepare_boot_cpu(void)
1905{
1906 cpu_set(smp_processor_id(), cpu_online_map);
1907 cpu_set(smp_processor_id(), cpu_callout_map);
1908}
1909
1910int __devinit
1911__cpu_up(unsigned int cpu)
1912{
1913 /* This only works at boot for x86. See "rewrite" above. */
1914 if (cpu_isset(cpu, smp_commenced_mask))
1915 return -ENOSYS;
1916
1917 /* In case one didn't come up */
1918 if (!cpu_isset(cpu, cpu_callin_map))
1919 return -EIO;
1920 /* Unleash the CPU! */
1921 cpu_set(cpu, smp_commenced_mask);
1922 while (!cpu_isset(cpu, cpu_online_map))
1923 mb();
1924 return 0;
1925}
1926
1927void __init
1928smp_cpus_done(unsigned int max_cpus)
1929{
1930 zap_low_mappings();
1931}
diff --git a/arch/i386/mach-voyager/voyager_thread.c b/arch/i386/mach-voyager/voyager_thread.c
new file mode 100644
index 000000000000..9980eef31fda
--- /dev/null
+++ b/arch/i386/mach-voyager/voyager_thread.c
@@ -0,0 +1,167 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_thread.c
8 *
9 * This module provides the machine status monitor thread for the
10 * voyager architecture. This allows us to monitor the machine
11 * environment (temp, voltage, fan function) and the front panel and
12 * internal UPS. If a fault is detected, this thread takes corrective
13 * action (usually just informing init)
14 * */
15
16#include <linux/module.h>
17#include <linux/config.h>
18#include <linux/mm.h>
19#include <linux/kernel_stat.h>
20#include <linux/delay.h>
21#include <linux/mc146818rtc.h>
22#include <linux/smp_lock.h>
23#include <linux/init.h>
24#include <linux/bootmem.h>
25#include <linux/kmod.h>
26#include <linux/completion.h>
27#include <linux/sched.h>
28#include <asm/desc.h>
29#include <asm/voyager.h>
30#include <asm/vic.h>
31#include <asm/mtrr.h>
32#include <asm/msr.h>
33
34#include <linux/irq.h>
35
36#define THREAD_NAME "kvoyagerd"
37
38/* external variables */
39int kvoyagerd_running = 0;
40DECLARE_MUTEX_LOCKED(kvoyagerd_sem);
41
42static int thread(void *);
43
44static __u8 set_timeout = 0;
45
46/* Start the machine monitor thread. Return 1 if OK, 0 if fail */
47static int __init
48voyager_thread_start(void)
49{
50 if(kernel_thread(thread, NULL, CLONE_KERNEL) < 0) {
51 /* This is serious, but not fatal */
52 printk(KERN_ERR "Voyager: Failed to create system monitor thread!!!\n");
53 return 1;
54 }
55 return 0;
56}
57
58static int
59execute(const char *string)
60{
61 int ret;
62
63 char *envp[] = {
64 "HOME=/",
65 "TERM=linux",
66 "PATH=/sbin:/usr/sbin:/bin:/usr/bin",
67 NULL,
68 };
69 char *argv[] = {
70 "/bin/bash",
71 "-c",
72 (char *)string,
73 NULL,
74 };
75
76 if ((ret = call_usermodehelper(argv[0], argv, envp, 1)) != 0) {
77 printk(KERN_ERR "Voyager failed to run \"%s\": %i\n",
78 string, ret);
79 }
80 return ret;
81}
82
83static void
84check_from_kernel(void)
85{
86 if(voyager_status.switch_off) {
87
88 /* FIXME: This should be configureable via proc */
89 execute("umask 600; echo 0 > /etc/initrunlvl; kill -HUP 1");
90 } else if(voyager_status.power_fail) {
91 VDEBUG(("Voyager daemon detected AC power failure\n"));
92
93 /* FIXME: This should be configureable via proc */
94 execute("umask 600; echo F > /etc/powerstatus; kill -PWR 1");
95 set_timeout = 1;
96 }
97}
98
99static void
100check_continuing_condition(void)
101{
102 if(voyager_status.power_fail) {
103 __u8 data;
104 voyager_cat_psi(VOYAGER_PSI_SUBREAD,
105 VOYAGER_PSI_AC_FAIL_REG, &data);
106 if((data & 0x1f) == 0) {
107 /* all power restored */
108 printk(KERN_NOTICE "VOYAGER AC power restored, cancelling shutdown\n");
109 /* FIXME: should be user configureable */
110 execute("umask 600; echo O > /etc/powerstatus; kill -PWR 1");
111 set_timeout = 0;
112 }
113 }
114}
115
116static void
117wakeup(unsigned long unused)
118{
119 up(&kvoyagerd_sem);
120}
121
122static int
123thread(void *unused)
124{
125 struct timer_list wakeup_timer;
126
127 kvoyagerd_running = 1;
128
129 reparent_to_init();
130 daemonize(THREAD_NAME);
131
132 set_timeout = 0;
133
134 init_timer(&wakeup_timer);
135
136 sigfillset(&current->blocked);
137 current->signal->tty = NULL;
138
139 printk(KERN_NOTICE "Voyager starting monitor thread\n");
140
141 for(;;) {
142 down_interruptible(&kvoyagerd_sem);
143 VDEBUG(("Voyager Daemon awoken\n"));
144 if(voyager_status.request_from_kernel == 0) {
145 /* probably awoken from timeout */
146 check_continuing_condition();
147 } else {
148 check_from_kernel();
149 voyager_status.request_from_kernel = 0;
150 }
151 if(set_timeout) {
152 del_timer(&wakeup_timer);
153 wakeup_timer.expires = HZ + jiffies;
154 wakeup_timer.function = wakeup;
155 add_timer(&wakeup_timer);
156 }
157 }
158}
159
160static void __exit
161voyager_thread_stop(void)
162{
163 /* FIXME: do nothing at the moment */
164}
165
166module_init(voyager_thread_start);
167//module_exit(voyager_thread_stop);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 17:05:04 -0500